<p>In recent years, switch-mode power electronic converters have gained considerable popularity</p> <p>because of their compact size and high switching frequencies. This makes them</p> <p>suitable for power processing in various applications, including photovoltaic systems and</p> <p>electric vehicles. However, their high switching frequency capabilities have a drawback. A</p> <p>high-frequency common-mode voltage coupled with the switching of the power converters</p> <p>excites the parasitic capacitances of the system. It leads to the flow of common-mode current.</p> <p>Since the common-mode current flows through an unintended path, it can potentially</p> <p>interfere with the performance of system components. Passive filters can be used to mitigate</p> <p>common-mode currents. Using a common-mode inductor in conjunction with strategically</p> <p>placed capacitors makes it possible to limit the flow of common-mode current.</p> <p><br></p> <p>As part of this work, passive mitigation of common-mode current will be investigated in</p> <p>a variable frequency drive system. In this regard, the process of designing a three-phase ac</p> <p>common-mode inductor is explained. As a first step, a mitigation strategy is proposed and</p> <p>described. Next, the issue of self-capacitance of the inductor is discussed. Afterwards, the</p> <p>ac common-mode inductor is designed using a multi-objective optimization-based approach.</p> <p>Following this are the design results, concluding the dissertation.</p>

Biopotential signals are important to physicians for diagnosing medical conditions in patients. Traditionally, biopotentials are acquired using contact electrodes together with instrumentation amplifiers (INAs). The biopotentials are generally weak and in the presence of stronger common mode signals. The INA thus needs to have very good Common Mode Rejection Ratio (CMRR) to amplify the weak biopotential while rejecting the stronger common mode interferers. Opamp based INAs with a resistor-capacitor feedback are suitable for acquiring biopotentials with low power and low noise performance. However, CMRR of such INA topologies is typically very poor. In the presented research, a technique is proposed for improving the CMRR of opamp based INAs in RC feedback configurations by dynamically matching input and feedback capacitor pairs. Two instrumentation amplifiers (one fully differential and the other fully balanced fully symmetric) are designed with the proposed dynamic element matching scheme. Post layout simulation results show that with 1 percent mismatch between the limiting capacitor pairs, CMRR is improved to above 150dB when the proposed dynamic element matching scheme is used. The INAs draw about 10uA of quiescent current from a 1.5 dual power supply source. The input referred noise of the INAs is less than 3uV/sqrt(Hz).

The currently used DSL splitters or filters are designed for ADSL band up to 1104 KHz and ADSL2+ band up to 2208 KHz. To meet faster internet access, DSL technology has evolved from ADSL into VDSL2 with an operating band up to 30 MHz. However, the splitters in VDSL2 band have some design difficulties in longitudinal conversion loss and isolation. The main purpose of this thesis is to find some solutions to overcome these design difficulties for splitters operating in VDSL2 band. The proposed solutions include the use of common-mode choke and compensation circuit. The final testing results of the splitters can validate the proposed solutions.

Common mode (CM) electromagnetic interference (EMI) can compromise electronics systems, interfere with communication systems, and degrade mechanical systems. Multiple inverters can also generate excessive CM EMI that often exceeds individual inverter EMI standards. Due to their weight, volume, cost, and suboptimal performance, active and passive filters and chokes are inefficient as EMI mitigation options. By utilizing frequency modulation (FM) or spread spectrum frequency modulation (SSFM), EMI energy is dispersed. In spite of not requiring expensive, bulky, and heavy filters, these techniques produce significant ripples in output voltages and currents. This dissertation uses enhanced sinusoidal frequency modulation to reduce CM EMI output, bridging the gap between existing EMI solutions: 1) To reduce performance degradation, a state-of-the-art FM topology with duty cycle correction is proposed. Due to large output voltage and current ripples, FM techniques have limited bandwidth and utilization. Duty cycle correction allows for a wider FM bandwidth with better EMI attenuation while minimizing output ripple performance tradeoffs. 2) CM EMI accumulation is a growing concern in power converter networks. Even if each converter complies with EMI regulations, multiple converters may produce CM EMI that exceeds EMI standards in parallel operation. A novel algorithm is proposed to suppress CM EMI in a large-scale network using SFMCW frequency indexing. The algorithm minimizes aggregate EMI by minimizing switching frequency overlap among converters. 3) CM EMI noise in complex systems presents a critical challenge. Since standalone converters are rarely affected by CM EMI phases, they were usually overlooked in most studies until recently. CM currents generated by multiple converters can be added or subtracted based on phase differences. The CM currents in large systems with multiple inverters are distributed randomly, resulting in multiple peaks and nulls. In order to reduce network EMI, a sinusoidal FM technique with phase shift is proposed to attenuate CM EMI on multiple parallel inverters. This method overcomes conventional methods' critical disadvantages, including the need for accurate component characterization and modeling, and reducing CM EMI without additional passive components.

In recent year, the single-end transmission line is instead by differential transmission line . Differential signaling has been generally used in the high speed digital interconnection on the PCBs. The advantages of the differential signal with a low noise and high common-mode noise suppression, but the differential mode transmission signal is a very high quality requirements of circuit, the two line should have same length and symmetry, but in the practical package the circuit is not this case, In the limit space ,the differential signal should through the bend, it would lead to the phase skew and produce the differential to common mode conversion noise on the signal integrity and electromagnetic interference(EMI) problem. In this paper a new type of bend is proposed that reduces differential -to-common mode conversion noise for high speed digital circuit. This novel structure can reduce the mode conversion over 20dB at DC to 10GHz, and the differential insertion loss remains low. Also time domain the TDT common mode noise from 0.09V to 0.008V as compared with the bended differential transmission line using the edge couple bend. Moreover, the measurement on proposed structure show a close match with the full-wave simulation result. However, this structure does not have a reference plane, the return path is not complete, the current is easy to radiate out, so I design a guard trace to reduce the radiation in this structure.

We propose two kinds of 1.0 Gbps LVDS ( low voltage differential signaling ) transceivers for LCD ( liquid crystal display ) in this thesis. LVDS has become a popular choice for high-speed serial links in large-sized display units. Our designs are an I/O interface circuit for Gbps operation which is fully complied with the IEEE STD 1596.3 (LVDS). A step-down voltage regulator is employed to reject the noise coupled in the system power supply. In the first design of the transmitter, a CMFB (common mode feedback) circuitry is utilized to stabilize the common voltage in a pre-defined range. In the second design of the transmitter, we try to use a DC bias circuitry to stabilize output common mode voltage to further improve the stability of the common mode voltage. By contrast, a regenerative circuit which provides a positive feedback loop gain between the preamplifier and the output buffer in the receiver such that the received bit streams can be correctly restored

Differential signaling is suitable for high speed signal transmission due to lower noise induction and higher common-mode noise rejection compared to its single-ended signaling counterpart. However, for a high performance differential transmission-line pair, excellent symmetry and appropriate design for substrate layer stack-up is necessary. Especially for a practical IC package substrate, differential transmission-line pair is inevitable for asymmetry because of considering the locations of IC pads and solderballs. Furthermore, different differential transmission-line pair architectures are also demanded in consideration of limited substrate floorplan space and substrate layer stack-up structures. In this thesis, several differential pairs have been implemented on the conventional 4-layer laminate package substrate. The consequent high frequency performances are measured using vector network analyzer and then compared by converting into mixed-mode S-parameters.

Switch mode power supplies are widely used in different applications. High efficiency and high power density are two driving forces for power supply systems. However, high dv/dt and di/dt in switch mode power supplies will cause severe EMI noise issue. In a typical front-end converter, the EMI filter usually occupies 1/3 to 1/4 volume of total converter. Hence, reducing the EMI noise of power converter can help reduce the volume of EMI filter and improving the total power density of the converter. For off-line switch mode power supplies, DM noise is dominated by PFC converter. CM noise is a more complicated issue. It is contributed by both PFC converter and DC/DC converter. While many researches have focused on reducing CM noise for PFC converter, the CM noise of DC/DC converter still remains a challenge. The main objective of this thesis is provide a solution to have best CM noise reduction for DC/DC converters. The shielding concept and balance concept are combined to propose a novel balance double shielding technique. This method can have an effective CM noise reduction in the circuit level. In addition it is easy to design and implement in the real production. The balance condition is easily controlled and guarantees effective CM noise reduction in mass production. Then, a novel one-layer shielding method for PCB winding transformer is provided. This shielding technique can block CM noise from primary side and also cancel the CM noise from secondary side. In addition, shielding does not increase the loss of converter too much. Furthermore, this shielding technique can be applied to matrix transformer structure. For matrix transformer LLC converter, the inter-winding capacitor is very large and will cause severe CM noise problem. By adding shielding layer, CM noise has been greatly reduced. In addition, by modifying the secondary winding, the loss on shielding layer is minimized and experiments show that the total efficiency of converter has almost no impact. Furthermore, although this thesis uses flyback and LLC resonant converter as example to demonstrate the concept, the novel shielding technique can also be applied to other topologies that have similar transformer structure. / Master of Science

There are growing industrial demands for low-voltage supply and low-power consumption circuits and systems. This is especially true for very high integration level and very large scale integrated (VLSI) mixed-signal chips and system-on-a-chip. It is mainly due to the limited power dissipation within a small area and the costs related to the packaging and thermal management. In this research work, two low-voltage, low-power integrated circuits used for data communication systems are introduced. The first one is a high performance continuous-time linear phase filter with automatic frequency tuning. The filter can be used in hard disk driver systems and wired communication systems such as 1000Base-T transceivers. A pseudo-differential operational transconductance amplifier (OTA) based on transistors operating in triode region is used to achieve a large linear signal swing with low-voltage supplies. A common-mode (CM) control circuit that combines common-mode feedback (CMFB), common-mode feedforward (CMFF), and adaptive-bias has been proposed. With a 2.3V single supply, the filter’s total harmonic distortion is less than –44dB for a 2VPP differential input, which is due to the well controlled CM behavior. The ratio of the root mean square value of the ac signal to the power supply voltage is around 31%, which is much better than previous realizations. The second integrated circuit includes two LVDS drivers used for high-speed point-to-point links. By removing the stacked switches used in the conventional structures, both LVDS drivers can operate with ultra low-voltage supplies. Although the Double Current Sources (DCS) LVDS driver draws twice minimum static current as required by the signal swing, it is quite simple and achieves very high speed operation. The Switchable Current Sources (SCS) LVDS driver, by dynamically switching the current sources, draws minimum static current and reduces the power consumption by 60% compared to the previously reported LVDS drivers. Both LVDS drivers are compliant to the standards and operate at data rates up to gigabits-per-second.

There are growing industrial demands for low-voltage supply and low-power consumption circuits and systems. This is especially true for very high integration level and very large scale integrated (VLSI) mixed-signal chips and system-on-a-chip. It is mainly due to the limited power dissipation within a small area and the costs related to the packaging and thermal management. In this research work, two low-voltage, low-power integrated circuits used for data communication systems are introduced. The first one is a high performance continuous-time linear phase filter with automatic frequency tuning. The filter can be used in hard disk driver systems and wired communication systems such as 1000Base-T transceivers. A pseudo-differential operational transconductance amplifier (OTA) based on transistors operating in triode region is used to achieve a large linear signal swing with low-voltage supplies. A common-mode (CM) control circuit that combines common-mode feedback (CMFB), common-mode feedforward (CMFF), and adaptive-bias has been proposed. With a 2.3V single supply, the filter’s total harmonic distortion is less than –44dB for a 2VPP differential input, which is due to the well controlled CM behavior. The ratio of the root mean square value of the ac signal to the power supply voltage is around 31%, which is much better than previous realizations. The second integrated circuit includes two LVDS drivers used for high-speed point-to-point links. By removing the stacked switches used in the conventional structures, both LVDS drivers can operate with ultra low-voltage supplies. Although the Double Current Sources (DCS) LVDS driver draws twice minimum static current as required by the signal swing, it is quite simple and achieves very high speed operation. The Switchable Current Sources (SCS) LVDS driver, by dynamically switching the current sources, draws minimum static current and reduces the power consumption by 60% compared to the previously reported LVDS drivers. Both LVDS drivers are compliant to the standards and operate at data rates up to gigabits-per-second.