Terminal models have been used for various power electronic applications. In this work a two- and three-terminal black box model is proposed for electro-magnetic interference (EMI) characterization. The modeling procedure starts with a time-variant system at a particular operating condition, which can be a converter, set of converters, sub-system or collection of components. A unique, linear equivalent circuit is created for applications in the frequency domain. Impedances and current / voltage sources define the noise throughout the entire EMI frequency spectrum. All parameters needed to create the model are clearly defined to ensure convergence and maximize accuracy. The model is then used to predict the attenuation caused by a filter with increased accuracy over small signal insertion gain measurements performed with network analyzers. Knowledge of EMI filters interactions with the converter allows for advanced techniques and design constraints to optimize the filter for size, weight, and cost. Additionally, the model is also demonstrated when the operating point of the system does not remain constant, as with AC power systems. Modeling of a varying operating point requires information of all the operating conditions for a complete and accurate model. However, the data collection and processing quickly become unmanageable due to the large amounts of data needed. Therefore, simplification techniques are used to reduce the complexity of the model while maintaining accuracy throughout the frequency spectrum. The modeling approach is verified for linear and power electronic networks including: a dc-dc boost converter, phase-leg module, and a simulated dc-ac inverter. The accuracy of the model is confirmed up to 100 MHz in simulation and at least 50 MHz for experimental validation. / Ph. D.

This dissertation is to focus on the development of modeling and simulation methodology to predict conductive electromagnetic interference (EMI) for high power converters. Conventionally, the EMI prediction relies on the Fast Fourier Transformation (FFT) method with the time-domain simulation result that requires long hours of simulation and a large amount of data. The proposed approach is to use the frequency-domain analysis technique that computes the EMI spectrum directly by decomposing noise sources and their propagation paths. This method not only largely reduces the computational effort, but also provides the insightful information about the critical components of the EMI generation and distribution. The study was first applied to a dc/dc chopper circuit by deriving the high frequency equivalent circuit model for differential mode (DM) and common mode (CM) EMIs. The noise source was modeled as the trapezoidal current and voltage pulses. The noise cut-off frequency was identified as a function of the rise time and fall time of the trapezoidal waves. The noise propagation path was modeled as lumped parasitic inductors and capacitors, and additional noise cut-off frequency was identified as the function of parasitic components. . Using the noise source and path models, the proposed method effectively predicts the EMI performance, and the results were verified with the hardware experiments. With the well-proven EMI prediction methodology with a dc/dc chopper, the method was then extended to the prediction of DM and CM EMIs of three-phase inverters under complex pulse width modulation (PWM) patterns. The inverter noise source requires the double Fourier integral technique because its switching cycle and the fundamental cycle are in two different time scales. The noise path requires parasitic parameter extraction through finite element analysis for complex-structured power bus bar and printed circuit layout. After inverter noise source and path are identified, the effects of different modulation schemes on EMI spectrum are evaluated through the proposed frequency-domain analysis technique and verified by hardware experiment. The results, again, demonstrate that the proposed frequency-domain analysis technique is valid and is considered a promising approach to effectively predicting the EMI spectrum up to tens of MHz range. / Ph. D.

With GaN and SiC switching devices becoming more commercially available, higher switching frequency is being applied to achieve higher efficiency and power density in power converters. However, electro-magnetic interference (EMI) becomes a more severe problem as a result. In this thesis, the switching frequency effect on conducted EMI noise is assessed. As EMI noise increases, the EMI filter plays a more important role in a power converter. As a result, an effective EMI modeling technique of the power converter system is required in order to find an optimized size and effective EMI filter. The frequency-domain model is verified to be an efficient and easy model to explore the EMI noise generation and propagation in the system. Of the various models, the unterminated behavioral model can simultaneously predict CM input and output noise of an inverter, and the prediction falls in line with the measurement around 10 MHz or higher. The DM terminated behavioral model can predict the DM input or output noise of the motor drive higher than 20 MHz. These two models are easy to extract and have high prediction capabilities; this is verified on a 10 kHz-switching-frequency Si motor drive. It is worthwhile to explore the prediction capability of the two models when they are applied to a SiC-based power inverter with switching frequency ranges from 20 kHz to 70 kHz. In this thesis, the CM unterminated behavioral model is first applied to the SiC power inverter, and results show that the model prediction capability is limited by the noise floor of the oscilloscope measurement. The proposed segmented-frequency-range measurement is developed and verified to be a good solution to the noise floor. With the improved impedance fixtures, the prediction from CM model matches the measurement to 30 MHz. To predict the DM input and output noise of the SiC inverter, the DM terminated behavioral model can be used under the condition that the CM and DM noise are decoupled. With the system noise analysis, the DM output side is verified to be independent of the CM noise and input side. The DM terminated behavioral model is extracted at the inverter output and predicts the DM output noise up to 30 MHz after solving the noise floor and DM choke saturation problem. At the DM input side, the CM and DM are seen to be coupled with each other. It is found experimentally that the mixture of the CM and DM noise results from the asymmetric impedance of the system. The mixed mode terminated behavioral model is proposed to predict the DM noise when a mixed CM effect exists. The model can capture the DM noise up to to 30 MHz when the impedance between the inverter to CM ground is not balanced. The issue often happens in extraction of the model impedance and is solved by the curving-fitting optimization described in the thesis. This thesis ends with a summary of contributions, limitations, and some future research directions. / Master of Science

As wide-bandgap devices continue to experience deeper penetration in commercial applications, there are still a number of factors which make the adoption of such technologies difficult. One of the most notable issues with the application of wide-bandgap technologies is meeting existing noise requirements and regulations. Due to the faster dv/dt and di/dt of SiC devices, more noise is generated in comparison to Si IGBTs. Therefore, in order to fully experience the benefits offered by this new technology, the noise must either be filtered or mitigated by other means. A survey of various DC/DC topologies was conducted in order to find a candidate for a battery interface in a UPS system. A three-level NPC topology was explored for its potential benefit in terms of noise, efficiency, and additional features. This converter topology was modeled, simulated, and a hardware prototype constructed for evaluation within a UPS system, although its uses are not limited to such applications. A UPS system is a good example of an application with strict noise requirements which must be fulfilled according to IEC standards. Based on a newly devised mode of operation, this converter was verified to produce no common-mode voltage under ideal conditions, and was able to provide a 6 dB reduction in common-mode voltage emissions in the UPS prototype. This was done while achieving a peak efficiency in excess of 99% with the ability to provide bidirectional power flow between the UPS and battery backup. The converter was verified to operate at the rated UPS conditions of 20 kW while converting between a total DC bus voltage of 800 V and a nominal battery voltage of 540 V. / Master of Science / As material advancements allow for the creation of devices with superior electrical characteristics compared to their predecessors, there are still a number of factors which cause these devices to see limited usage in commercial applications. These devices, typically referred to as wide-bandgap devices, include silicon carbide (SiC) transistors. These SiC devices allow for much faster switching speeds, greater efficiencies, and lower system volume compared to their silicon counterparts. However, due to the faster switching of these devices, there is more electromagnetic noise generated. In many applications, this noise must be filtered or otherwise mitigated in order to meet international standards for commercial use. Consequently, new converter topologies and configurations are necessary to provide the most benefit of the new wide-bandgap devices while still meeting the strict noise requirements. A survey of topologies was conducted and the modeling, design, and testing of one topology was performed for use in an uninterruptible power supply (UPS). This converter was able to provide a noticeable reduction in noise compared to standard topologies while still achieving very high efficiency at rated conditions. This converter was also verified to provide power bidirectionally—both when the UPS is charging the battery backup, and when the battery is supplying power to the load.

Auxiliary power supply (APS) plays a key role in ensuring the safe operation of the main circuit elements including gate drivers, sensors, controllers, etc. in medium voltage (MV) silicon carbide (SiC)-based converter systems. Such a converter requires APS to have high insulation capability, low common-mode coupling capacitance (Ccm ), and high-power density. Furthermore, considering the lifetime and simplicity of the auxiliary power supply system design in the MV converter, partial discharge (PD) free and multi-load driving ability are the additional two factors that need to be addressed in the design. However, today’s state-of-the-art products have either low power rating or bulky designs, which does not satisfy the demands. To improve the current designs, this thesis presents a 1 MHz isolated APS design using gallium nitride (GaN) devices with MV insulation reinforcement. By adopting LCCL-LC resonant topology, the proposed APS is able to supply multiple loads simultaneously and realize zero voltage switching (ZVS) at any load conditions. Since high reliability under faulty load conditions is also an important feature for APS in MV converter, the secondary side circuit of APS is designed as a regulated stage. To achieve MV insulation (> 20 kV) as well as low Ccm value (< 5 pF), a current-based transformer with a single turn structure using MV insulation wire is designed. Furthermore, by introducing different insulated materials and shielding structures, the APS is capable to achieve different partial discharge inception voltages (PDIV). In this thesis, the transformer design, resonant converter design, and insulation strategies will be detailly explained and verified by experiment results. Overall, this proposed APS is capable to supply multiple loads simultaneously with a maximum power of 120 W for the sending side and 20 W for each receiving side in a compact form factor. ZVS can be realized regardless of load conditions. Based on different insulation materials, two different receiving sides were built. Both of them can achieve a breakdown voltage of over 20 kV. The air-insulated solution can achieve a PDIV of 6 kV with Ccm of 1.2 pF. The silicone-insulated solution can achieve a PDIV of 17 kV with Ccm of 3.9 pF. / M.S. / Recently, 10 kV silicon carbide (SiC) MOSFET receives strong attention for medium voltage applications. Asit can switch at very high speed, e.g. > 50 V/ns, the converter system can operate at higher switching frequency condition with very small switching losses compared to silicon (Si) IGBT [8]. However, the fast dv/dt noise also creates the common mode current via coupling capacitors distributed inside the converter system, thereby introducing lots of electromagnetic interference (EMI) issues. Such issues typically occur within the gate driver power supplies due to the high dv/dt noises across the input and output of the supply. Therefore, the ultra-small coupling capacitor (<5 pF) of a gate driver power supply is strongly desired.[37] To satisfy the APS demands for high power modular converter system, a solution is proposed in this thesis. This work investigates the design of 1 MHz isolated APS using gallium nitride (GaN) devices with medium voltage insulation reinforcement. By increasing switching frequency, the overall converter size could be reduced dramatically. To achieve a low Ccm value and medium voltage insulation of the system, a current-based transformer with a single turn on the sending side is designed. By adopting LCCL-LC resonant topology, a current source is formed as the output of sending side circuity, so it can drive multiple loads importantly with a maximum of 120 W. At the same time, ZVS can use realized with different load conditions. The receiving side is a regulated stage, so the output voltage can be easily adjusted and it can operate in a load fault condition. Different insulation solutions will be introduced and their effect on Ccm will be discussed. To further reduce Ccm, shielding will be introduced. Overall, this proposed APS can achieve a breakdown voltage of over 20 kV and PDIV up to 16.6 kV with Ccm<5 pF. Besides, multi-load driving ability is able to achieve with a maximum of 120 W. ZVS can be realized. In the end, the experiment results will be provided.

No / Recent work by Billinton et al. has highlighted the importance of employing more than one adverse weather state when modelling transmission line failures by Markov processes. In the present work the structure of the modelling Markov process is identified, allowing the rate matrix to be written in a closed form using Kronecker matrix operations. This approach allows larger models to be handled safely and with ease. The MAXIMA implementation of two asymptotic reliability indices for such systems is addressed, exemplifying the combination of symbolic and numerical steps, perhaps not seen in this context before. It is also indicated how the three-state weather model can be extended to a multi-state model, while retaining the scope of the proposed closed-form expression for the rate matrix. Some possible future work is discussed.

Vast attention has been paid to active continuous-time filters over the years. Thus as the cheap, readily available integrated circuit OpAmps replaced their discrete circuit versions, it became feasible to consider active-RC filter circuits using large numbers of OpAmps. Similarly the development of integrated operational transconductance amplifier (OTA) led to new filter configurations. This gave rise to OTA-C filters, using only active devices and capacitors, making it more suitable for integration. The demands on filter circuits have become ever more stringent as the world of electronics and communications has advanced. In addition, the continuing increase in the operating frequencies of modern circuits and systems increases the need for active filters that can perform at these higher frequencies; an area where the LC active filter emerges. What mainly limits the performance of an analog circuit are the non-idealities of the used building blocks and the circuit architecture. This research concentrates on the design issues of high frequency continuous-time integrated filters. Several novel circuit building blocks are introduced. A novel pseudo-differential fully balanced fully symmetric CMOS OTA architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. On the level of system architectures, a novel filter low-voltage 4th order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled-inductors, thus providing bandwidth tuning with small passband ripple. As part of a direct conversion dual-mode 802.11b/Bluetooth receiver, a BiCMOS 5th order low-pass channel selection filter is designed. The filter operated from a single 2.5V supply and achieves a 76dB of out-of-band SFDR. A digital automatic tuning system is also implemented to account for process and temperature variations. As part of a Bluetooth transmitter, a low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications.

Multilevel inverters play a major role in the modern day medium and high power energy conversion processes. The classic two level voltage source inverter generates PWM pole voltage output having two levels with strong fundamental component and harmonics centered around the switching frequency and its multiples. With higher switching frequency, its components can be easily filtered and results in better Total harmonic distortion (THD) output voltage and current. But with higher switching frequency, switching loss of power devices increases and electromagnetic interferences also increases. Also in two level inverter, pole voltage switches between zero and DC bus volt-age Vdc. This switching results in high dv=dt and causes EMI and increased stress on the motor winding insulation. The attractive features of multilevel inverters compared to a two level inverter are reduced switching frequency, reduced switching loss, improved volt-age and current THD, reduced dv=dt, etc. Because of these reasons, multilevel invertersultilevelinvertersplayamajorroleinthemoderndaymediumandhighpower find application in electric motor drives, transmission and distribution of power, transportation, traction, distributed generation, renewable energy systems like photo voltaic, hydel power, energy management, power quality, electric vehicle applications, etc. AC motor driven applications are consuming the significant part of the generated electrical energy (more than 60%) around the world. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low with lower out-put voltage dv=dt. Also by using multilevel inverters, the common mode voltage (CMV) switching can be made zero and associated motor bearing failure can be mitigated. For multilevel inverter topologies, as the number of level increases, the power circuit becomes more complex by the increase in the number of DC power supplies, capacitors, switching devices and associated control circuitry. The main focus of development in multilevel inverter for medium and high power applications is to obtain an optimized number of voltage levels with reduced number of switching devices, capacitors and DC power sources. In this thesis, a new hybrid seven level inverter topology with a single DC supply is proposed with reduced switch count. The inverter is realized by cascading two three level flying capacitor inverters with a half bridge module. Compared to the conventional seven level inverter topologies, the proposed inverter topology uses lesser number of semiconductor devices, capacitors and DC power supplies for its operation. For this topology, capacitor voltage balancing is possible for entire modulation range irrespective of the load power factor. Also capacitor voltage can be controlled over a switching cycle and this result in lowering the capacitor sizing for the proposed topology. A simple hysteresis band based capacitor voltage balancing scheme is implemented for the inverter topology. For a voltage source inverter fed induction motor drive system, the inverter pole voltage is the sum of motor phase voltage and common mode voltage. In induction motors, there exists a parasitic capacitance between stator winding and stator iron, and between stator winding and rotor iron. Common mode voltage with significant magnitude and high frequency switching causes leakage current through these parasitic capacitances and motor bearings. This leakage current can cause ash over of bearing lubricant and corrosion of ball bearings, resulting in an early mechanical failure of the drive system. In this thesis, analysis of extending the linear modulation range of a general n-level inverter by allowing reduced magnitude of common mode voltage (CMV) switching (only Vdc/18) is presented. A new hybrid seven level inverter topology, with a single DC supply and with reduced common mode voltage (CMV) switching is presented in this thesis for the first time. Inverter is operated with zero CMV for modulation index less than 86% and is operated with a CMV magnitude of Vdc/18 to extend the linear modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilizing the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology. In recent years, model predictive control (MPC) using the system model has proved to be a good choice for the control of power converter and motor drive applications. MPC predicts system behavior using a system model and current system state. For cascaded multilevel inverter topologies with a single DC supply, closed loop capacitor voltage control is necessary for proper operation. This thesis presents zero and reduced common mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state which minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96% the inverter can operate with reduced CMV magnitude ( Vdc/18) and reduced CMV switching frequency using the new space-vector PWM (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop V/f control scheme. The operation of a two level inverter in the over-modulation region (maximum peak phase fundamental output of inverter is greater than 0:577Vdc) results in lower order harmonics in the inverter output voltage. This lower order harmonics (mainly 5th, 7th, 11th, and 13th) causes electromagnetic torque ripple in motor drive applications. Also these harmonics causes extra losses and adversely affects the efficiency of the drive system. Also inverter control becomes non linear and special control algorithms are required for inverter operation in the over modulation region. In conventional schemes, maximum fundamental output voltage possible is 0:637Vdc. In that case inverter is operated in a square wave mode, also called six-step mode. This operation results in high dv=dt for the inverter output voltage. With multilevel inverters also, the inverter operation with peak phase fundamental output voltage above 0:577Vdc results in lower order harmonics in the inverter output voltage and results in electromagnetic torque pulsation. In this thesis, a new space vector PWM (SVPWM) method to extend the linear modulation range of a cascaded five level inverter topology with a single DC supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0:577Vdc to 0:637Vdc without increasing the DC bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0 Hz to 50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The ve level topology presented in this thesis is realized by cascading a two level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady state and dynamic operating conditions are presented. Zero common mode voltage (CMV) operation of multilevel inverters results in reduced DC bus utilization and reduced linear modulation range. In this thesis two reduced CMV SVPWM schemes are presented to extend the linear modulation range by allowing reduced CMV switching. But using these SVPWM schemes the peak phase fundamental output voltage possible is only 0:55Vdc in the linear region. In this thesis, a method to extend the linear modulation range of a CMV eliminated hybrid cascaded multilevel inverter with a single DC supply is presented. Using this method peak fundamental voltage can be increased from 0 to 0:637Vdc with zero CMV switching inside the linear modulation range. Also inverter can be controlled linearly for the entire modulation range. Also, various PWM switching sequences are analyzed in this thesis and the PWM sequence which gives minimum current ripple is used for the zero CMV operation of the inverter. The inverter topology with single DC supply is realized by cascading a two level inverter with two floating capacitor fed full bridge modules. Simulation and experimental results for steady state and dynamic operating conditions are presented to validate the proposed method. A three phase, 400 V, 3.7 kW, 50 Hz, two-pole induction motor drive with the open-loop V/f control scheme is implemented in the hardware for testing proposed inverter topology and proposed SVPWM algorithms experimentally. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V IGBT half-bridge modules (SKM-75GB-12T4). Optoisolated gate drivers with de-saturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation, TMS320F28335 DSP is used as the main controller and Xilinx SPARTAN-3 XC3S200 FPGA as the PWM signal generator with dead time of 2.5 s. Level shifted carrier-based PWM algorithm is implemented for the normal inverter operation and zero CMV operation. From the PWM algorithm, information about the pole voltage levels to be switched can be obtained for each phase. In the sampling period, for capacitor voltage balancing of each phase, the DSP selects a switching state using the capacitor voltage information, current direction and pole voltage data for each phase. This switching state information along with the PWM timing data is sent to an FPGA module. The FPGA module generates the gating signals with a dead time of 2.5 s for the gate driver module for all the three phases by processing the switching state information and PWM signals for the given sampling period. For fundamental frequencies above 10Hz, synchronous PWM technique was used for testing the inverter topology. For modulation frequencies 10Hz and below, a constant switching frequency of 900 Hz was used. Various steady state and transient operation results are provided to validate the proposed inverter topology and the zero and reduced CMV operation schemes and extending the linear modulation scheme presented in this thesis. With the advantages like reduced switch count, single DC supply requirement, zero and reduced CMV operation, extension of linear modulation range, linear control of induction motor over the entire modulation range with zero CMV, lesser dv=dt stresses on devices and motor phase windings, lower switching frequency, inherent capacitor balancing, the proposed inverter power circuit topologies, and the SVPWM methods can be considered as good choice for medium voltage, high power motor drive applications.

This dissertation presents design and implementation of continuous time analog filters for two specific applications: wideband analog systems such as disk drive channel and low-power wireless applications. Specific focus has been techniques that reduce the power requirements of the overall system either through improvement in architecture or efficiency of the analog building blocks. The first problem that this dissertation addresses is the implementation of wideband filters with high equalization gain. An efficient architecture that realizes equalization zeros by combining available transfer functions associated with a biquadratic cell is proposed. A 330MHz, 5th order Gm-C lowpass Butterworth filter with 24dB boost is designed using the proposed architecture. The prototype fabricated in standard 0.35um CMOS process shows -41dB of IM3 for 250mV peak to peak swing with 8.6mW/pole of power dissipation. Also, an LC prototype implemented using similar architecture is discussed in brief. It is shown that, for practical range of frequency and SNR, LC based design is more power efficient than a Gm-C one, though at the cost of much larger area. Secondly, a complementary current mirror based building block is proposed, which pushes the limits imposed by conventional transconductors on the powerefficiency of Gm-C filters. Signal processing through complementary devices provides good linearity and Gm/Id efficiency and is shown to improve power efficiency by nearly 7 times. A current-mode 4th order Butterworth filter is designed, in 0.13um UMC technology, using the proposed building. It provides 54.2dB IM3 and 55dB SNR in 1.3GHz bandwidth while consuming as low as 24mW of power. All CMOS filter realization occupies a relatively small area and is well suited for integration in deep submicron technologies. Thirdly, a 20MHz, 68dB dynamic range active RC filter is presented. This filter is designed for a ten bit continuous time sigma delta ADC architecture developed specifically for fine-line CMOS technologies. Inverter based amplification and a common mode feedback for such amplifiers are discussed. The filter consumes 5mW of power and occupies an area of 0.07 mm2.

Advanced pulse width modulation (PWM) techniques such as space vector PWM, active zero state PWM, discontinuous PWM, and near state PWM methods are used in three-phase AC motor drives for the purpose of obtaining low PWM current ripple, wide voltage linearity range, and reduced common mode voltage (CMV). In some applications, a filter is inserted between the inverter and the motor for the purpose of reducing the stresses in the motor. The motor current PWM ripple components, terminal voltage overshoots, shaft voltage, and bearing currents, etc. can all be reduced by means of PWM techniques and passive filters. Various PWM techniques and passive filter types exist. This thesis studies the combinations of PWM techniques and filters and evaluates the performance of the motor drive in terms of the discussed stresses in the motor. PWM techniques are reviewed, a generalized algorithm for the implementation of PWM techniques is developed, and implementation on a 4 kW rated drive is demonstrated. Filter types are studied, among them the common mode inductor and the pure sine filter (PSF) configurations are investigated in detail. Filters are designed and their laboratory performance is evaluated. In the final stage the advanced PWM techniques and filters are combined, the incompatibility problem of discontinuous PWM methods with the PSF is illustrated. A cure based on rate of change limiter is proposed and its feasibility proven in the laboratory experiments. With the use of the proposed PWM algorithm and PSF, a motor drive with ideal DC to AC conversion stage (DC to pure sine) is achieved and its performance is demonstrated in the laboratory.