Soft multiprocessor systems exploit the plentiful computational resources available in field programmable devices. By virtue of their adaptability and ability to support coarse grained parallelism, they serve as excellent platforms for rapid prototyping and design space exploration of embedded multiprocessor applications. As complex applications emerge, careful mapping, processor and interconnect customization are critical to the overall performance of the multiprocessor system. In this thesis, we have developed an automated scalable framework to efficiently map applications written in a high-level programmer-friendly language to customizable soft-cores. The framework allows the user to specify the application in a high-level language called Streamit. After an initial analysis of the application, a soft multiprocessor system is generated automatically using a set of customizable SPREE processors which communicate with each other over point-to-point FIFO connections. Several micro-architectural features of the processors are then automatically customized on a per-application basis to improve system area, performance and power consumption. The efficiency and scalability of this approach has been validated using a diverse set of eight audio, video and signal processing benchmarks on soft multiprocessor systems consisting of one to sixteen processors. Results show that generated soft multiprocessor systems consisting of sixteen processors can offer up to 6x speedup over a conventional single processor system. Our experiments with soft multiprocessor interconnection networks show that point-to-point topologies perform approximately 2x better than mesh topologies. Finally, we demonstrate that application-specific customizations on the instruction set, memory size, and inter-processor buffer size can improve the area and performance of the generated soft multiprocessor systems. The developed framework facilitates rapid design space exploration of soft multiprocessors.

The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous processor design, and propose a series of asynchronous designs to be used by students in tandem with traditional synchronous designs when taking an undergraduate computer architecture course.

The purpose of this paper was to use the Overall Equipment Effectiveness productivity formula in plant manufacturing and convert it to measuring productivity for forklifts. Productivity for a forklift was defined as being available and picking up and moving containers at port locations in Seattle and Alaska. This research uses performance measures in plant manufacturing and applies them to mobile equipment in order to establish the most effective means of analyzing reliability and productivity. Using the Internet of Things to collect data on fifteen forklift trucks in three different locations, this data was then analyzed over a six-month period to rank the forklifts’ productivity from 1 – 15 using the Operating Equipment Effectiveness formula (OPEE). This ranking was compared to the industry standard for utilization to demonstrate how this approach would yield a better performance analysis and provide a more accurate tool for operations managers to manage their fleets of equipment than current methods. This analysis was shared with a fleet operations manager, and his feedback indicated there would be considerable value to analyzing his operations using this process. The results of this research identified key areas for improvement in equipment reliability and the need for additional operator training on the proper use of machines and provided insights into equipment operations in remote locations to managers who had not visited or evaluated those locations on-site.

As small-form factor drones grow more intelligent, they increasingly require more sophisticated capabilities to record sensor data and system state, ensuring safe and improved operation. Already regulations for black boxes, electronic data recorders (EDRs), for determining liabilities and improving the safety of large-form factor autonomous vehicles are becoming established. Conventional techniques use hardened memory storage units that conserve all sensor (visual) and system operational state; and N-way redundant models for detecting uncertainty in system operation. For small-form factor drones, which are highly limited by weight, power, and computational resources, these techniques become increasingly prohibitive. In this paper, we propose a safety architecture for resource constrained autonomous vehicles that enables the development of safer and more efficient nano-drone systems. The insight for the proposed safety architecture is that the regular structure of data-driven models used to control drones can be exploited to efficiently compress and identify key events that should be conserved in the EDR subsystem. We describe an implementation of the architecture, including hardware and software support, and quantify the benefits of the approach. We show that the proposed techniques can increase the amount of recorded flight time by over 10x and reduce energy usage by over 10x for high-resolution systems.

Modern companies are increasingly relying on groups of individuals to reach organizational goals and objectives, however many organizations struggle to cultivate optimal teams that can maximize performance. Fortunately, existing research has established that group personality composition (GPC), across five dimensions of personality, is a promising indicator of team effectiveness. Additionally, recent advances in technology have enabled groups of humans to form real-time, closed-loop systems that are modeled after natural swarms, like flocks of birds and colonies of bees. These Artificial Swarm Intelligences (ASI) have been shown to amplify performance in a wide range of tasks, from forecasting financial markets to prioritizing conflicting objectives. The present research examines the effects of group personality composition on team performance and investigates the impact of measuring GPC through ASI systems. 541 participants, across 111 groups, were administered a set of well-accepted and vetted psychometric assessments to capture the personality configurations and social sensitivities of teams. While group-level personality averages explained 10% of the variance in team performance, when group personality composition was measured through human swarms, it was able to explain 29% of the variance, representing a 19% amplification in predictive capacity. Finally, a series of machine learning models were applied and trained to predict group effectiveness. Multivariate Linear Regression and Logistic Regression achieved the highest performance exhibiting 0.19 mean squared error and 81.8% classification accuracy.

<p>High-content screening (HCS) produces an immense amount of data, often on the scale of Terabytes. This requires considerable processing power resulting in long analysis time. As a result, HCS with a single-core processor system is an inefficient option because it takes a huge amount of time, storage and processing power. The situation is even worse because most of the image processing software is developed in high-level languages which make customization, flexibility and multi-processing features very challenging. Therefore, the goal of the project is to develop a multithreading model in C language. This model will be used to extract subcellular localization features, such as threshold adjacency statistics (TAS) from the HCS data. The first step of the research was to identify an appropriate dye for use in staining the MCF-7 cell line. The cell line has been treated with staurosporin kinase inhibitor, which can provide important physiological and morphological imaging information. The process of identifying a suitable dye involves treating cells with different dye options, capturing the fluorescent images of the treated cells with the Opera microscope, and analyzing the imaging properties of the stained cells. Several dyes were tested, and the most suitable dye to stain the cellular membrane was determined to be Di4-Anepps. The second part of the thesis was to design and develop a parallel program in C that can extract TAS features from the stained cellular images. The program reads the input cell images captured by Opera microscopes, converts it to TIFF format from the proprietary Opera format, identifies the region-of-interest contours of each cell, and computes the TAS features. A significant increase in speed in the order of four fold was obtained using the customized program. Different scalability tests using the developed software were compared against software developed in Acapella scripting language. The result of the test shows that the computational time is proportional to number of cells in the image and is inversely proportional to number of cores in a processor.</p> / Master of Applied Science (MASc)

Network security is an ongoing major problem in today’s Internet world. Even though there have been simulation studies related to denial of service and cache attacks, studies of attacks on real networks are still lacking in the research. In this thesis, the effects of cache attacks in real information-centric networking systems were investigated. Cache attacks were implemented in real networks with different cache sizes and with Least Recently Used, Random and First In First Out algorithms to fill the caches in each node. The attacker hits the cache with unpopular content, making the user request that the results be fetched from web servers. The cache hit, time taken to get the result, and number of hops to serve the request were calculated with real network traffic. The results of the implementation are provided for different topologies and are compared with the simulation results.

Powerful, handheld computing devices have proliferated among consumers in recent years. Combined with new cameras and sensors capable of detecting objects in three-dimensional space, new gesture-based paradigms of human computer interaction are becoming available. One possible application of these developments is an automated sign language recognition system. This thesis reviews the existing body of work regarding computer recognition of sign language gestures as well as the design of systems for speech recognition, a similar problem. Little work has been done to apply the well-known architectural patterns of speech recognition systems to the domain of sign language recognition. This work creates a functional prototype of such a system, applying three architectures seen in speech recognition systems, using a Hidden Markov classifier with 75-90% accuracy. A thorough search of the literature indicates that no cloud-based system has yet been created for sign language recognition and this is the first implementation of its kind. Accordingly, there have been no empirical performance analyses regarding a cloud-based Automatic Sign Language Recognition (ASLR) system, which this research provides. The performance impact of each architecture, as well as the data interchange format, is then measured based on response time, CPU, memory, and network usage across an increasing vocabulary of sign language gestures. The results discussed herein suggest that a partially-offloaded client-server architecture, where feature extraction occurs on the client device and classification occurs in the cloud, is the ideal selection for all but the smallest vocabularies. Additionally, the results indicate that for the potentially large data sets transmitted for 3D gesture classification, a fast binary interchange protocol such as Protobuf has vastly superior performance to a text-based protocol such as JSON.

In this world of growing technology, any small improvement in the present scenario would create a revolution. One of the popular revolutions in the computer science field is parallel computing. A single parallel execution is not sufficient to see its non-deterministic features, as same execution with the same data at different time would end up with a different path. In order to see how non deterministic a parallel execution can extend up to, creates the need of the ensemble of executions. This project implements a program to estimate the Gibbs Entropy for an ensemble of parallel executions. The goal is to develop tools for studying the non-deterministic feature of parallel code based on execution entropy and use these developed tools for current and future research.

Over the past decades, the shrinking transistor size enabled more transistors to be integrated into an IC chip, to achieve higher and higher computing performances. However, the semiconductor industry is now reaching a saturation point of Moore’s Law largely due to soaring power consumption and heat dissipation, among other factors. High chip temperature not only significantly increases packing/cooling cost, degrades system performance and reliability, but also increases the energy consumption and even damages the chip permanently. Although designing 2D and even 3D multi-core processors helps to lower the power/thermal barrier for single-core architectures by exploring the thread/process level parallelism, the higher power density and longer heat removal path has made the thermal problem substantially more challenging, surpassing the heat dissipation capability of traditional cooling mechanisms such as cooling fan, heat sink, heat spread, etc., in the design of new generations of computing systems. As a result, dynamic thermal management (DTM), i.e. to control the thermal behavior by dynamically varying computing performance and workload allocation on an IC chip, has been well-recognized as an effective strategy to deal with the thermal challenges. Over the past decades, the shrinking transistor size, benefited from the advancement of IC technology, enabled more transistors to be integrated into an IC chip, to achieve higher and higher computing performances. However, the semiconductor industry is now reaching a saturation point of Moore’s Law largely due to soaring power consumption and heat dissipation, among other factors. High chip temperature not only significantly increases packing/cooling cost, degrades system performance and reliability, but also increases the energy consumption and even damages the chip permanently. Although designing 2D and even 3D multi-core processors helps to lower the power/thermal barrier for single-core architectures by exploring the thread/process level parallelism, the higher power density and longer heat removal path has made the thermal problem substantially more challenging, surpassing the heat dissipation capability of traditional cooling mechanisms such as cooling fan, heat sink, heat spread, etc., in the design of new generations of computing systems. As a result, dynamic thermal management (DTM), i.e. to control the thermal behavior by dynamically varying computing performance and workload allocation on an IC chip, has been well-recognized as an effective strategy to deal with the thermal challenges. Different from many existing DTM heuristics that are based on simple intuitions, we seek to address the thermal problems through a rigorous analytical approach, to achieve the high predictability requirement in real-time system design. In this regard, we have made a number of important contributions. First, we develop a series of lemmas and theorems that are general enough to uncover the fundamental principles and characteristics with regard to the thermal model, peak temperature identification and peak temperature reduction, which are key to thermal-constrained real-time computer system design. Second, we develop a design-time frequency and voltage oscillating approach on multi-core platforms, which can greatly enhance the system throughput and its service capacity. Third, different from the traditional workload balancing approach, we develop a thermal-balancing approach that can substantially improve the energy efficiency and task partitioning feasibility, especially when the system utilization is high or with a tight temperature constraint. The significance of our research is that, not only can our proposed algorithms on throughput maximization and energy conservation outperform existing work significantly as demonstrated in our extensive experimental results, the theoretical results in our research are very general and can greatly benefit other thermal-related research.