Förslaget i betänkandet om informationsskyldighet för skatterådgivare är starkt influerat av arbetet som pågått inom EU för att motverka aggressiv skatteplanering. Eftersom länder inte har en enhetlig skattelagstiftning skapar det möjligheter att utnyttja kryphål när två eller flera länder uppvisar oförenligheter i lagstiftningen. Aggressiv skatteplanering torde främst vara ett förfarande som sker gränsöverskridande, varför det varit viktigt att inom EU samarbeta för att täppa igen kryphålen. Även inom svensk rätt har det länge pågått en diskussion för att motverka inhemsk aggressiv skatteplanering. Det har resulterat i att regeringen har lagt fram ett betänkande om informationsskyldighet för skatterådgivare, SOU 2018:91. Förslaget i betänkandet innebär att i första hand skatterådgivare åläggs en skyldighet att till Skatteverket inrapportera information angående skattearrangemang som denne utformat eller bistått sin klient med. Detta ska göras i syfte att Skatteverket ska få information tidigare i hanteringen för att på ett mer effektivt sätt kunna få kännedom om aggressiva skatteplaneringsförfaranden. Förslaget i betänkandet har dock fått omfattande kritik ur rättssäkerhetssynpunkt gällande såväl dess utformning som arbetet som ligger till grund för detta. I denna uppsats undersöks förslaget i dess helhet och en jämförelse med såväl skatteflyktslagen som kritiken som riktats mot förslaget görs utifrån de grundläggande rättsprinciper inom svensk rätt. Som slutsats konstateras det att förslaget i betänkandet inte uppfyller de grundläggande kraven på rättssäkerhet.

Digital-to-analog converters with a range over 50 volts are required for driving micro-electro mechanical system deformable mirrors used in adaptive optics. An existing tested and deployed DM driver has 1024 channels and resolution of 15mV per Least Significant Bit. DMs used in the search for exoplanets require 3mV per LSB resolution. A technique is presented to employ a secondary high resolution and low voltage DAC which has for it's ground the output of the high voltage DAC. The entire system then has the range of high voltage DAC yet the resolution of the low voltage DAC. A method for providing signal and power to the floating system is given. Rudimentary micro controller firmware and also PC software is presented to achieve complete functionality. The technique uses all off-the-shelf components. Resolution of 1.6mV per LSB, 60V range and 36mW of power per channel is achieved.

<p>Direct Digital Frequency Synthesi<em>s </em>(DDFS) is a method of producing an analog waveform by</p><p>generating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction.</p><p>At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sources which cannot be switched on simultaneously and have equal weights are shared. After sharing weights, the control signals are reduced to from 59 to 43 and current sources from 207 to 145.</p><p>Different control words are used by the DDFS system in order to generate different frequencies. The control word is successively added to the previous value in a 20-bit accumulator. Nine most significant bits out of these twenty bits are used for the DAC.</p><p>Since the Current Steering DAC architecture is suitable for high speed and high resolution purposes, so a 9-bit nonlinear current steering DAC is used to convert the output of bit products to the analog sine wave. Seven bits are used to generate one quarter of the sine wave. Eighth and ninth bits are used to generate the full sine wave.</p><p>HCMOS 9 (130 nm) ST Microelectronics process is used by employing high speed NMOS and PMOS transistors. The bit products (control signals) are computed by using complementary static CMOS logic which then act as control signals for the current sources after passing through D-flip flops. Practical design issues of current sources and parts of digital logic were studied and implemented using the Cadence full-custom design environment.</p>

<p>In the European research projects SIAM and 100GET, building blocks for 100Gbit Ethernet optical link have been implemented. Data are sent from a computer, modulated, converted to analog, mixed onto the RF-band, sent through an optical link, down-mixed, converted back to digital, demodulated and sent to a receiving computer. Signal Processing Devices Sweden AB is contributing to this project by their implementation PANDA. This thesis has been to study, as a proof of concept, and implement a prototype of PANDA as the component converting from digital to analog signal, the DAC, in 65nm SOI CMOS technology.</p><p>The idea of the system is to use the concept of time interleaving, where two or more components interact by performing the same operations on a different set of data, ideally scaling the performance linearly with the amount of components used.</p><p>This report presents design, implementation and verification at simulation level. It includes interfacing with off-chip components in low voltage specifications, clock generation, filtering and current-steered switches.</p>

In this master thesis work, the power dissipation in a current-steering digital- to-analog converter, DAC, has been studied. The digital as well as the analog power dissipation have been modelled in MATLAB and it is shown that the MATLAB models agrees well with simulation results from the circuit simulator (Spectre). A case study on a DAC designed at Ericsson Microelectronics AB in Linköping has also been done. The DAC is a thermometer-coded current-steering DAC suitable for telecommunications applications. The telecommunication standards that have been studied are asymmetric digital subscriber line, ADSL, very high speed data digital subscriber line, VDSL, and, wireless local area network, WLAN. The conlusion of the study is that the power dissipation of the specific DAC, used in ADSL applications, 75mW, is far from optimized. It can theoretically be lowered to 3.5mW.

In the European research projects SIAM and 100GET, building blocks for 100Gbit Ethernet optical link have been implemented. Data are sent from a computer, modulated, converted to analog, mixed onto the RF-band, sent through an optical link, down-mixed, converted back to digital, demodulated and sent to a receiving computer. Signal Processing Devices Sweden AB is contributing to this project by their implementation PANDA. This thesis has been to study, as a proof of concept, and implement a prototype of PANDA as the component converting from digital to analog signal, the DAC, in 65nm SOI CMOS technology. The idea of the system is to use the concept of time interleaving, where two or more components interact by performing the same operations on a different set of data, ideally scaling the performance linearly with the amount of components used. This report presents design, implementation and verification at simulation level. It includes interfacing with off-chip components in low voltage specifications, clock generation, filtering and current-steered switches.

This thesis includes two topics, which are a Self-sampled ALL-MOS ASK Demodulator and a Synchronous DAC with Self-calibration. An all-MOS ASK demodulator with a wide bandwidth for lower ISM band applications is presented in the first half of this thesis. The chip area is reduced without using any passive element. It is very compact to be integrated in an SOC (system-on-chip) for wireless biomedical applications, particularly in biomedical implants. Because of low area cost and low power consumption, the proposed design is also easily to be integrated in other mobile medical devices. The self-sampled loop with a MOS equivalent capacitor compensation mechanism enlarges the bandwidth, which is more than enough to be adopted in any application using lower ISM bands. To demonstrate this technique, an ASK demodulator prototype is implemented and measured using a TSMC 0.35 £gm standard CMOS process. The second topic reveals a synchronous DAC with self-calibration. The main idea is to use a calibration circuit to overcome large error of output voltage caused by the variation of the unit capacitor. When DAC is not calibrated, INL is larger than 1.7 LSB. After calibrated, INL is improved to be smaller than 0.5 LSB. To demonstrate this technique, a DAC prototype is implemented and measured using a TSMC 0.18 £gm standard CMOS process.

<p>In this master thesis work, the power dissipation in a current-steering digital- to-analog converter, DAC, has been studied. The digital as well as the analog power dissipation have been modelled in MATLAB and it is shown that the MATLAB models agrees well with simulation results from the circuit simulator (Spectre). </p><p>A case study on a DAC designed at Ericsson Microelectronics AB in Linköping has also been done. The DAC is a thermometer-coded current-steering DAC suitable for telecommunications applications. The telecommunication standards that have been studied are asymmetric digital subscriber line, ADSL, very high speed data digital subscriber line, VDSL, and, wireless local area network, WLAN. The conlusion of the study is that the power dissipation of the specific DAC, used in ADSL applications, 75mW, is far from optimized. It can theoretically be lowered to 3.5mW.</p>

Oversampled digital-to-analog converters typically employ an array of unit elements to drive out the analog signal. Manufacturing defects can create errors due to mismatch between the unit elements, leading to a sharp reduction in the effective dynamic range through the converter. Mismatch noise shaping is an established technique for alleviating these effects, but usually anchors the signal band to a fixed frequency location. In order to extend these advantages to tunable applications, this work explores a series of techniques that allow the suppression band of the mismatch noise shaping function to have an adjustable center frequency. The proposed techniques are implemented in hardware and evaluated according to mismatch shaping performance, latency and hardware complexity. / text

Nowadays, the multi-standard wireless receivers and multi-format video processors have created a great demand for integrating multiple standards into a single chip. The multiple standards usually require several Analog to Digital Converters (ADCs) with different specifications. A promising solution is adopting a power and area efficient reconfigurable ADC with tunable bandwidth and dynamic range. The advantage of the reconfigurable ADC over customized ADCs is that its power consumption can be scaled at different specifications, enabling optimized power consumption over a wide range of sampling rates and resulting in a more power efficient design. Moreover, the reconfigurable ADC provides IP reuse, which reduces design efforts, development costs and time to market. On the other hand, software radio transceiver has been introduced to minimize RF blocks and support multiple standards in the same chip. The basic idea is to perform the analog to digital (A/D) and digital to analog (D/A) conversion as close to the antenna as possible. Then the backend digital signal processor (DSP) can be programmed to deal with the digital data. The continuous time (CT) bandpass (BP) sigma-delta ADC with good SNR and low power consumption is a good choice for the software radio transceiver. In this work, a proposed 10-bit reconfigurable ADC is presented and the non-overlapping clock generator and state machine are implemented in UMC 90nm CMOS technology. The state machine generates control signals for each MDAC stage so that the speed can be reconfigured, while the power consumption can be scaled. The measurement results show that the reconfigurable ADC achieved 0.6-200 MSPS speed with 1.9-27 mW power consumption. The ENOB is about 8 bit over the whole speed range. In the second part, a 2-bit quantizer with tunable delay circuit and 2-bit DACs are implemented in TSMC 0.13um CMOS technology for the 4th order CT BP sigma-delta ADC. The 2-bit quantizer and 2-bit DACs have 6dB SNR improvement and better stability over the single bit quantizer and DACs. The penalty is that the linearity of the feedback DACs should be considered carefully so that the nonlinearity doesn't deteriorate the ADC performance. The tunable delay circuit in the quantizer is designed to adjust the excess loop delay up to +/- 10% to achieve stability and optimal performance.