Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / This work presents and analyzes a new family of electronic ballasts to supply metal halide lamps applied to interior lighting systems. These lamps present the best light quality among the high intensity discharge lamps, and its compactness results a good choice for interior lighting systems application. The electrical characteristics of the high intensity discharge lamps are evaluated, and it is presented an alternative for supplying these lamps in a safe and reliable way. This alternative consists of using high frequency DC/DC converters in order to supply the lamp with a low frequency, symmetrical square waveform. A family of electronic ballasts is presented, which all the topologies are obtained from the differential connection of DC/DC converters. The analysis of these proposed and designed systems brings the main advantages and disadvantages of using each topology, related both to the components design and to the restrictions implied by each topology. / Esse trabalho apresenta e analisa uma nova família de reatores eletrônicos capazes de acionar lâmpadas de multivapor metálico com tubo de descarga cerâmico. Essas lâmpadas apresentam, dentre as lâmpadas de descarga em alta pressão, a melhor qualidade do fluxo luminoso, além de se tratar de lâmpadas compactas, caracterizando-as como uma ótima alternativa a ser aplicada em sistemas de iluminação de ambientes interiores. As características das lâmpadas de descarga em alta pressão, com relação ao acionamento e controle, são avaliadas, e uma alternativa é apresentada para se alimentar tais lâmpadas de forma segura e confiável, através da utilização de conversores CC/CC operando em alta freqüência para alimentar a lâmpada com uma tensão quadrada, simétrica e em baixa freqüência. Dessa forma, uma família de reatores eletrônicos é apresentada, sendo que todas as topologias são derivadas da técnica de conexão diferencial de conversores CC/CC bidirecionais. O estudo de todos os sistemas propostos e implementados tem por finalidade caracterizar as principais vantagens e desvantagens do emprego de cada topologia apresentada, com relação ao dimensionamento de componentes e limitações impostas por cada topologia.

L’intégration ultime de convertisseurs à découpage repose sur deux axes de recherche. Le premier axe est de développer les convertisseurs à capacités commutées. Cette approche est compatible avec une intégration totale sur silicium, mais limitée en terme de densité de puissance. Le second axe est l’utilisation de convertisseurs à inductances, qui pâtissent d’imposants composants passifs. Une augmentation de la fréquence permet de réduire les valeurs des composants passifs. Cependant une augmentation de la fréquence implique une augmentation des pertes par commutation, ce qui est contrebalancé par l’utilisation d’une technologie de fabrication plus avancée. Ces technologies plus avancées souffrent quant à elles de limitations au niveau de leur tension d’utilisation. Convertir une tension de 3,3V vers une tension de 1,2V apparait donc comme un objectif ambitieux, particulièrement dans le cas où les objectifs de taille minimale et de rendement supérieur à 90 % sont visés. Un assemblage 3D des composants actifs et passifs permet de minimiser la surface du système. Un fonctionnement à haute fréquence est aussi considéré, ce qui permet de réduire les valeurs requises pour les composants passifs. Dans le contexte de l’alimentation « on-chip », la technologie silicium est contrainte par les fonctions numériques. Une technologie 40 nm CMOS de type « bulk » est choisie comme cas d’étude pour une tension d’entrée de 3,3 V. Les transistors 3,3 V présentent une figure de mérite médiocre, les transistors 1,2 V sont donc choisis. Ce choix permet en outre de présenter une meilleure compatibilité avec une future intégration sur puce. Une structure cascode utilisant trois transistors en série est étudiée est confrontée à une structure standard à travers des simulations et mesures. Une fréquence de +100MHz est choisie. Une technologie de capacités en tranchées est sélectionnée, et fabriquée sur une puce séparée qui servira d’interposeur et recevra la puce active et les inductances. Les inductances doivent être aussi fabriquées de manière intégrée afin de limiter leur impact sur la surface du convertisseur. Ce travail fournit un objet contenant un convertisseur de type Buck à une phase, avec la puce active retournée (« flip-chip ») sur l’interposeur capacitif, sur lequel une inductance est rapportée. Le démonstrateur une phase est compatible pour une démonstration à phases couplées. Les configurations standard et cascode sont comparées expérimentalement aux fréquences de 100 MHz et 200 MHz. La conception de la puce active est l’élément central de ce travail, l’interposeur capacitif étant fabriqué par IPDiA et les inductances par Tyndall National Institute. L’assemblage des différents sous-éléments est réalisé via des procédés industriels. Un important ensemble de mesures ont été réalisées, montrant les performances du convertisseur DC-DC délivré, ainsi que ses limitations. Un rendement pic de 91,5 % à la fréquence de 100 MHz a été démontré. / Ultimate integration of power switch-mode converter relies on two research paths. One path experiments the development of switched-capacitor converters. This approach fits silicon integration but is still limited in term of power density. Inductive DC-DC architectures of converters suffer by the values and size of passive components. This limitation is addressed with an increase in frequency. Increase in switching losses in switches leads to consider advanced technological nodes. Consequently, the capability with respect to input voltage is then limited. Handling 3.3 V input voltage to deliver an output voltage in the range 0.6 V to 1.2 V appears a challenging specification for an inductive buck converter if the smallest footprint is targeted at +90 % efficiency. Smallest footprint is approached through a 3D assembly of passive components to the active silicon die. High switching frequency is also considered to shrink the values of passive components as much as possible. In the context of on-chip power supply, the silicon technology is dictated by the digital functions. Complementary Metal-Oxide- Semiconductor (CMOS) bulk C40 is selected as a study case for 3.3 V input voltage. 3.3 V Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) features poor figure of merits and 1.2 V standard core, regular devices are preferred. Moreover future integration as an on-chip power supply is more compatible. A three-MOSFET cascode arrangement is experimented and confronted experimentally to a standard buck arrangement in the same technology. The coupled-phase architecture enables to reduce the switching frequency to half the operating frequency of the passive devices. +100MHz is selected for operation of passive devices. CMOS bulk C40 offers Metal-Oxide-Metal (MOM) and MOS capacitors, in density too low to address the decoupling requirements. Capacitors have to be added externally to the silicon die but in a tight combination. Trench-cap technology is selected and capacitors are fabricated on a separate die that will act as an interposer to receive the silicon die as well as the inductors. The work delivers an object containing a one-phase buck converter with the silicon die flip-chipped on a capacitor interposer where a tiny inductor die is reported. The one-phase demonstrator is suitable for coupled-phase demonstration. Standard and cascode configurations are experimentally compared at 100 MHz and 200 MHz switching frequency. A design methodology is presented to cover a system-to-device approach. The active silicon die is the central design part as the capacitive interposer is fabricated by IPDiA and inductors are provided by Tyndall National Institute. The assembly of the converter sub-parts is achieved using an industrial process. The work details a large set of measurements to show the performances of the delivered DC/DC converters as well as its limitations. A 91.5% peak efficiency at 100MHz switching frequency has been demonstrated.

The dissertation deals with simulations of the DC-DC converters in their basic configurations (Buck, Boost, Buck-boost, Cuk, SEPIC). In the first part of the thesis derivation of transfer functions Line-to-Output (LTO) and Control-To-Output (CTO) can be found. These symbolic responses are derived for three types of basic converters (Buck, Boost, Buck-boost) using well-known average model [1]. Derived expressions are very complicated. For reduction of these expressions symbolic approximation method was used, however the generality is lost. The average model was used to for decreasing the computational effort of analysis of DC-DC converters in the time domain. For these simulations VHDL-AMS language was used. The main topic of the thesis is harmonic balance method, which was adapted to DC-DC converters. Because conditions and assumptions for LTO and CTO functions are very different, harmonic balance method was derived into two variants. For obtaining of LTO response, duty cycle of switching signal can be considered as constant in time. Spectrum of this signal is simple as follows from well-known sinc function. For obtaining of CTO response PWM modulation must be used. Compared to sinc function spectrum of PWM modulation is richer (contains more combination frequencies). Many types of PWM modulation is described in [31]. For simulation PWM modulation with uniform sampling in two variants (single and double edge) was used. Non-ideal switching of PWM switch was modeled by PWM pulse with defined slew rate. Last section deals with comparison of all derived functions (LTO, CTO, modulation type, defined slew rate) with well-known averaged model.

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Recent research activities focused on improving the steady-state as well as the dynamic behavior of DC-DC converters for proper system performance, by proposing different design methods and control approaches with growing tendency to using digital implementation over analog practices. Because of the rapid advancement in semiconductors and microprocessor industry, digital control grew in popularity among PWM converters and is taking over analog techniques due to availability of fast speed microprocessors, flexibility and immunity to noise and environmental variations. Furthermore, increased interest in Field Programmable Gate Arrays (FPGA) makes it a convenient design platform for digitally controlled converters. The objective of this research is to propose new digital control schemes, aiming to improve the steady-state and transient responses of a high switching frequency FPGA-based digitally controlled DC-DC converters. The target is to achieve enhanced performance in terms of tight regulation with minimum power consumption and high efficiency at steady-state, as well as shorter settling time with optimal over- and undershoots during transients. The main task is to develop new and innovative digital PWM techniques in order to achieve: 1. Tight regulation at steady-state: by proposing high resolution DPWM architecture, based on Digital Clock Management (DCM) resources available on FPGA boards. The proposed architecture Window-Masked Segmented Digital Clock Manager-FPGA based Digital Pulse Width Modulator Technique, is designed to achieve high resolution operating at high switching frequencies with minimum power consumption. 2. Enhanced dynamic response: by applying a shift to the basic saw-tooth DPWM signal, in order to benefit from the best linearity and simplest architecture offered by the conventional counter-comparator DPWM. This proposed control scheme will help the compensator reach the steady-state value faster. Dynamically Shifted Ramp Digital Control Technique for Improved Transient Response in DC-DC Converters, is projected to enhance the transient response by dynamically controlling the ramp signal of the DPWM unit.

No description available.

The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response. The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts. A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved. At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.

Στην παρούσα διπλωματική εργασία προσομοιώθηκε, μέσω του προγράμματος Matlab και συγκεκριμένα μέσω της εργαλειοθήκης Simulink, ένα υβριδικό μικροδίκτυο το οποίο αποτελούνταν από μια φωτοβολταϊκή διάταξη των 85W, ένα συσσωρευτή ιόντων-λιθίου (Liion battery), δυο DC-DC μετατροπείς και ένα R-L φορτίο. Στην συνέχεια πραγματοποιήθηκαν 4 διαφορετικές τεχνικές ελέγχου σε 2 σημεία, έναν στην πλευρά του φωτοβολταϊκού και έναν στην πλευρά της μπαταρίας. Ο έλεγχος στην πλευρά του φωτοβολταϊκού στόχευε το ρεύμα του φωτοβολταϊκού κάθε χρονική στιγμή να έχει την κατάλληλη τιμή προκειμένου να επιτυγχάνεται η μέγιστη ισχύς μέσω σημείου απόδοσης της μέγιστης ισχύος (MPPT). Ο έλεγχος στην πλευρά της μπαταρίας έχει ως σκοπό την διατήρηση της τάσης του φορτίου στα 100 V.(Vload_reference=100V). Οι έλεγχοι που πραγματοποιήθηκαν ήταν με χρήση PI ελεγκτών, έλεγχοι εκμεταλλευόμενοι την παθητικότητα του Euler-Lagrange συστήματος (PBC), με χρήση ασαφών (fuzzy) ελεγκτών και με χρήση νευρο-ασαφών (neuro-fuzzy) ελεγκτών. / In this diploma thesis a DC hybrid microgrid was simulated by using the program Matlab and specifically the toolbox Simulink. The microgrid consists of a photovoltaic array, a Li-ion battery storage, two DC-DC converters and an R-L load. Four different control methods were then applied to our system in 2 places, one on the photovoltaic array and one on the battery. The one on the photovoltaic array aimed that the PV current would be such that every time the maximum power from the PV would be achieved through a maximum power point tracker. The one on the battery has the purpose of maintaining the load voltage at 100 Volts. The control methods which were implied were PI controllers, passivity based control, fuzzy controllers and neuro-fuzzy controllers.

The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response. The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts. A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved. At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.