¡@¡@Crushing the whole world in 2008, Global financial crisis caused a loss to Taiwan DRAM industry up to hundred billion dollar, which forced government and entrepreneur confront the problem of shortage of R&D. In order to improve the competitiveness of DRAM industry, Ministry of Economic Affairs set up TIMC. However, the corporation ended at the end of 2009 due to rejected by the Legislative Department. The problem still needs to be solved, so we will focus on how to improve this problem and use financial data of several main DRAM companies to analyze them by five categories, like production and investment capacity, asset use efficiency, earning capacity, financial flexibility and innovative capacity, etc. From analysis results we get the following problems: 1. Huge capital expenditure but competitiveness still weaken. 2. Single product portfolio couldn¡¦t help improve business cycle so that make insufficient capacity utilization. 3. Deteriorating financial situation and insufficient fund. 4. Lack of innovation ability, domestic industry has to rely on foreign technique authorization. In general, scattered resources, lack of autonomous technology and narrow product range are the key problems. We think integration sources and focused investment can avoid wasting funds. Besides, product diversification can offset the risk of gross margin decline and reduce business cycle fluctuations on gross margin. And developing autonomous technology can reduce using current OEM business model. Furthermore, this essay will propose a three-step scheme to DRAM industry for reference.

Memory wall is one of the major performance bottlenecks in modern computer systems. SRAM caches have been used to successfully bridge the performance gap between the processor and the memory. However, SRAM cache’s latency is inversely proportional to its size. Therefore, simply increasing the size of caches could result in negative impact on performance. To solve this problem, modern processors employ multiple levels of caches, each of a different size, forming the so called memory hierarchy. Upon a miss, the processor will start to lookup the data from the highest level (L1 cache) to the lowest level (main memory). Such a design can effectively reduce the negative performance impact of simply using a large cache. However, because SRAM has lower storage density compared to other volatile storage, the size of an SRAM cache is restricted by the available on-chip area. With modern applications requiring more and more memory, researchers are continuing to look at techniques for increasing the effective cache capacity. In general, researchers are approaching this problem from two angles: maximizing the utilization of current SRAM caches or exploiting new technology to support larger capacity in cache hierarchies. The first part of this thesis focuses on how to maximize the utilization of existing SRAM cache. In our first work, we observe that not all words belonging to a cache block are accessed around the same time. In fact, a subset of words are consistently accessed sooner than others. We call this subset of words as critical words. In our study, we found these critical words can be predicted by using access footprint. Based on this observation, we propose critical-words-only cache (co cache). Unlike the conventional cache which stores all words that belongs to a block, co-cache only stores the words that we predict as critical. In this work, we convert an L2 cache to a co-cache and use L1s access footprint information to predict critical words. Our experiments show the co-cache can outperform a conventional L2 cache in the workloads whose working-set-sizes are greater than the L2 cache size. To handle the workloads whose working-set-sizes fit in the conventional L2, we propose the adaptive co-cache (acocache) which allows the co-cache to be configured back to the conventional cache. The second part of this thesis focuses on how to efficiently enable a large capacity on-chip cache. In the near future, 3D stacking technology will allow us to stack one or multiple DRAM chip(s) onto the processor. The total size of these chips is expected to be on the order of hundreds of megabytes or even few gigabytes. Recent works have proposed to use this space as an on-chip DRAM cache. However, the tags of the DRAM cache have created a classic space/time trade-off issue. On the one hand, we would like the latency of a tag access to be small as it would contribute to both hit and miss latencies. Accordingly, we would like to store these tags in a faster media such as SRAM. However, with hundreds of megabytes of die-stacked DRAM cache, the space overhead of the tags would be huge. For example, it would cost around 12 MB of SRAM space to store all the tags of a 256MB DRAM cache (if we used conventional 64B blocks). Clearly this is too large, considering that some of the current chip multiprocessors have an L3 that is smaller. Prior works have proposed to store these tags along with the data in the stacked DRAM array (tags-in-DRAM). However, this scheme increases the access latency of the DRAM cache. To optimize access latency in the DRAM cache, we propose aggressive tag cache (ATCache). Similar to a conventional cache, the ATCache caches recently accessed tags to exploit temporal locality; it exploits spatial locality by prefetching tags from nearby cache sets. In addition, we also address the high miss latency issue and cache pollution caused by excessive prefetching. To reduce this overhead, we propose a cost-effective prefetching, which is a combination of dynamic prefetching granularity tunning and hit-prefetching, to throttle the number of sets prefetched. Our proposed ATCache (which consumes 0.4% of overall tag size) can satisfy over 60% of DRAM cache tag accesses on average. The last proposed work in this thesis is a DRAM-Cache-Aware (DCA) DRAM controller. In this work, we first address the challenge of scheduling requests in the DRAM cache. While many recent DRAM works have built their techniques based on a tagsin- DRAM scheme, storing these tags in the DRAM array, however, increases the complexity of a DRAM cache request. In contrast to a conventional request to DRAM main memory, a request to the DRAM cache will now translate into multiple DRAM cache accesses (tag and data). In this work, we address challenges of how to schedule these DRAM cache accesses. We start by exploring whether or not a conventional DRAM controller will work well in this scenario. We introduce two potential designs and study their limitations. From this study, we derive a set of design principles that an ideal DRAM cache controller must satisfy. We then propose a DRAM-cache-aware (DCA) DRAM controller that is based on these design principles. Our experimental results show that DCA can outperform the baseline over 14%.

Taiwan DRAM industry emerged on OEM basis, i.e. foundry manufactures based upon the technology authorized by the foreign owner. With the expansion of capacity, Taiwan DRAM industry has gradually increased its global market share. In particular, only those market players with 12¡¨foundry, which requires hefty capital investment and can significantly increases capacity, are able to compete in the market. The financial tsunami started in 2008, however, impacted severely on the global economy. DRAM industry could not immune from this, and the collapse was unprecedented. Majority of market players were suffering losses, and unable to afford the migration of manufacturing process. Taiwan players used to borrow to expand capacity. Four major Taiwan DRAM players carry an aggregate debt of TWD300 billion. Taiwan DRAM industry is almost destroyed by the high leverage during the financial tsunami. Facing the unprecedented difficulty of DRAM industry, Taiwan government raised an industry re-engineering (or consolidation, whichever is appropriate) proposal with an aim to enhance the competitiveness in the global market through changes in industry structure and business operation. Thanks to the industry recovery stemmed in the third quarter of 2009, DRAM price started rebounding. The financial difficulty of DRAM players was been resolved. The government¡¦s proposal for industry re-engineering was ended up with a failure.Taiwan DRAM players are still operating on OEM basis and lack of competitiveness in global market. Though Taiwan DRAM players have turned profitable, benefited from price rebound, it is still a question mark that these players can survive in the long run. As long as the structural problem remains unsolved, the industry players and the government will face the same issue again in future. When the next recession is coming, whether Taiwan players shall exit the market, or Taiwan government shall step in? Whether the industry shall go through a consolidation? This paper will present the migration of DRAM industry life cycle, change of business model, strategic alliance, and industry trend in future, analyze on business strategies adopted by Taiwan DRAM players under the competitive environment. Hopefully, this paper could provide a reference as to the development of business strategy for Taiwan DRAM players.

Recently the semiconductor industry tends to develop a smaller volume device and system with lower power consumption, lower leakage current, and high speed performance. SOI technology having many unique characteristics is one of the most hopeful methods in the direction. As semiconductor memory is concerned, The 1T-DRAM cell realized by the concept of floating body effect in a PD-SOI nMOSFET, that can allow DRAM cell to be scaled down in depth with less area occupied .In this paper, we will propose a new structure of 1T-DRAM cell, which has the buried oxide and block oxide around its body. It can suppress the junction capacitor between the S/D and the body of the cell. In addition it can also improve the programming window of the 1T-DRAM cell more than 80% by utilizing its own structural characteristic. We fabricated our new device in National Nano Device Laboratories. The device was carried out by depositing oxide and poly film on bulk Si wafer, just like TFT process. But doing by this way it has some issues about the polycrystalline channel and the S/D. Although it has some issues, but we made it successful using bulk Si wafer rather than expensive SOI wafer. It indeed reduces the cost of process.

In this paper, we propose a high-yield self-aligned process to form a silicon-on-insulator MOSFET with block oxide for 1T DRAM use. The new process can overcome the problem of the previous one [1], which cannot be used for a thin BOX devices. Based on the TCAD 10.0 simulation, we compared the conventional 1T-DRAM (PDSOI) with the partially depleted SOI with block oxide ¡]bPDSOI¡^ which used the new process presented in this thesis, We find that the device with block oxide embedded on body is not only obtain good short-channel effects immunity but also reduce leakage of the P-N junction between source/drain and the body and increase the gate controlability on the channel region. Moreover, it can decrease power consumption and raise the operation speed of the 1T-DRAM. Compare to the PDSOI DRAM to carry out 10 £gA programming window, the power consumption of the new 1T-DRAM is diminished 39% of write ¡§1¡¨ and 25% of write ¡§0¡¨. Furthermore, the energy consumption during memory operation is only 23% compared to that of the conventional PDSOI DRAM and it can short the operation time but achieve a long retention time.

This thesis presents an analysis of the implementation feasibility of RAM authentication and encryption. Past research as used simulations to establish that it is possible to authenticate and encrypt the contents of RAM with reasonable performance penalties by using clever implementations of tree data structures over the contents of RAM. However, previous work has largely bypassed implementation issues such as power consumption and silicon area required to implement the proposed schemes, leaving implementation details unspecified. This thesis studies the implementation cost of AES-GCM hardware and software solutions for memory authentication and encryption and shows that software solutions are infeasible because they are too costly in terms of performance and power, whereas hardware solutions are more feasible. / text

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As multi-core systems are becoming more popular in real time embedded systems, strict timing requirements for accessing shared resources must be met. In particular, a detailed latency analysis for Double Data Rate Dynamic RAM (DDR DRAM) is highly desirable. Several researchers have proposed predictable memory controllers to provide guaranteed memory access latency. However, the performance of such controllers sharply decreases as DDR devices become faster and the width of memory buses is increased. Therefore, a novel and composable approach is proposed that provides improved latency bounds compared to existing works by explicitly modeling the DRAM state. In particular, this new approach scales better with increasing number of cores and memory speed. Benchmark evaluation results show up to a 45% improvement in the worst case task execution time compared to a competing predictable memory controller for a system with 16 cores.

A computer system's memory is designed to accommodate the worst-case workloads with the highest memory requirement; as such, memory is underutilized when a system runs workloads with common-case memory requirements. Through a large-scale study of four production HPC systems, we find that memory underutilization problem in HPC systems is very severe. As unused memory is wasted memory, we propose exposing a compute node's unused memory to its CPU(s) through a user-transparent CPU-OS codesign. This can enable many new microarchitecture techniques that transparently leverage unused memory locations to help improve microarchitecture performance. We refer to these techniques as Free-memory-aware Microarchitecture Techniques (FMTs). In the context of HPC systems, we present a detailed example of an FMT called Free-memory-aware Replication (FMR). FMR replicates in-use data to unused memory locations to effectively reduce average memory read latency. On average across five HPC benchmark suites, FMR provides 13% performance and 8% system-level energy improvement. / M.S. / Random-access memory (RAM) or simply memory, stores the temporary data of applications that run on a computer system. Its size is determined by the worst-case application workload that the computer system is supposed to run. Through our memory utilization study of four large multi-node high-performance computing (HPC) systems, we find that memory is underutilized severely in these systems. Unused memory is a wasted resource that does nothing. In this work, we propose techniques that can make use of this wasted memory to boost computer system performance. We call these techniques Free-memory-aware Microarchitecture Techniques (FMTs). We then present an FMT for HPC systems in detail called Free-memory-aware Replication (FMR) that provides performance improvement of over 13%.

Software memory compression has been a common practice among operating systems. Since then, prior works have explored hardware memory compression to reduce the load on the CPU by offloading memory compression to hardware. However, prior works on hardware memory compression cannot provide critical isolation in multi-tenant systems like cloud servers. Our evaluation of prior work (TMCC) shows that a tenant can be slowed down by more than 12x due to the lack of isolation. This work, Compressed Memory Management Unit (CMMU), prototypes hardware compression for multi-tenant systems. CMMU provides critical isolation for multi-tenant systems.First, CMMU allows OS to control individual tenants' usage of physical memory. Second, CMMU compresses a tenant's memory to an OS-specified physical usage target. Finally, CMMU notifies the OS to start swapping the memory to the storage if it fails to compress the memory to the target. We prototype CMMU with a real compression module on an FPGA board. CMMU runs with a Linux kernel modified to support CMMU. The prototype virtually expands the memory capacity to 4X. CMMU stably supports the modified Linux kernel with multiple tenants and applications. While achieving this, CMMU only requires several extra cycles of overhead besides the essential data structure accesses. ASIC synthesis results show CMMU fits within 0.00931mm2 of silicon and operates at 3GHz while consuming 36.90mW of power. It is a negligible cost to modern server systems. / Master of Science / Memory is a critical resource in computer systems. Memory compression is a common technique to save memory resources. Memory compression consumes the computing resource, traditionally supplied by the CPU. In other words, memory compression traditionally competes with applications for CPU computing power. The prior work, TMCC, provides a design to perform memory compression in ASIC hardware, therefore no longer competing for CPU computing power. However, TMCC provides no isolation in a multitenant system like a modern cloud server. This thesis prototypes a new design, Compressed Memory Management Unit (CMMU), providing isolation in hardware memory compression. This prototype can speed up applications by 12x compared to without the isolation, with a 4x expansion in virtual memory capacity. CMMU supports a modified Linux OS running stably. CMMU also runs at high clock speed and offers little overhead in latency, silicon chip area, and power