In this thesis, the poly-Si TFTs with different channel width and channel length are successfully fabricated and characterized. In particular, by using the T-gate structure and body contact, we can measure the substrate current and body voltage. Therefore, short channel effects in polycrystalline silicon thin-film transistors are investigated clearly. In order to study impact ionization effect and floating body effect more carefully, we measure and compare the electrical behaviors of device with different grain boundary trap density, grain size, and channel dimension. The influences of these factors on the short channel effects are also discussed and explained. In this experiment, it is found that the devices with short channel length, exhibit improved normalized turn on current and smaller threshold voltage. But on the other hand the sever kink effect which generated by the impact ionization also observed. Moreover, the floating body under the channel region serve as a parasitic BJT as in silicon-on-insulator devices. The related single transistor latch-up is observed and discussed for short-channel devices with various channel width. The severe impact ionization effects in polycrystalline silicon thin-film transistors are investigated and characterized. By directly measuring the substrate current from conventional TFTs with body contact, the impact-ionization effects can be characterized and analyzed very clearly. An anomalous substrate current under high gate voltage is observed. The parasitic tunneling effect between inversion region and body region is proposed to explain this phenomenon. Finally, a physically-based model is established and compared with the measured substrate current. Good agreements are found when the vertical field scattering effect is included into the maximum electric field impact ionization model.

In this paper, we propose a high-yield self-aligned process to form a silicon-on-insulator MOSFET with block oxide for 1T DRAM use. The new process can overcome the problem of the previous one [1], which cannot be used for a thin BOX devices. Based on the TCAD 10.0 simulation, we compared the conventional 1T-DRAM (PDSOI) with the partially depleted SOI with block oxide ¡]bPDSOI¡^ which used the new process presented in this thesis, We find that the device with block oxide embedded on body is not only obtain good short-channel effects immunity but also reduce leakage of the P-N junction between source/drain and the body and increase the gate controlability on the channel region. Moreover, it can decrease power consumption and raise the operation speed of the 1T-DRAM. Compare to the PDSOI DRAM to carry out 10 £gA programming window, the power consumption of the new 1T-DRAM is diminished 39% of write ¡§1¡¨ and 25% of write ¡§0¡¨. Furthermore, the energy consumption during memory operation is only 23% compared to that of the conventional PDSOI DRAM and it can short the operation time but achieve a long retention time.

In this thesis, we carefully investigate the electrical characteristics of junctionless vertical MOSFET (JLVMOS) compared with the junctionless planar MOSFET (JLPMOS) and conversional junction vertical MOSFET (JVMOS). Also, we examine the advantages of the double-gate structure and the short-channel behavior of the junctionless transistors. According to the 2D simulation studies, the proposed JLVMOS can achieve better short-channel characteristics (JLVMOS: 62.04 mV/dec S.S., 23.96 mV/V DIBL; JLPMOS: 77.67 mV/dec S.S., 146.07 mV/V DIBL) as compared with the planar transistor, chiefly owing to the double-gate scheme. This proves that only the double-gate device has better gate controllability over the channel region to reduce the short-channel effect. More importantly is that the JLVMOS has a bulk Si starting material, in which the SOI-induced self-heating effects and the fabrication cost can be well suppressed and reduced, respectively. In comparison with the JVMOS, our proposed JLVMOS exhibits better S.S. and reduced DIBL. Furthermore, although the analog/RF properties of the JLVMOS are somewhat degraded, due to its simple fabrication process, our proposed JLVMOS can become one of the mainstream technology for future CMOS applications.

The prospect of producing nanometer channel-length thin film transistors (TFTs) for active matrix addressed pixelated arrays opens up new high-performance applications in which the most amenable device topology is the vertical thin film transistor (VTFT) in view of its small area. The previous attempts at fabricating VTFTs have yielded devices with a high drain leakage current, a low ON/OFF current ratio, and no saturation behaviour in the output current at high drain voltages, all induced by short channel effects. To overcome these adversities, particularly dominant as the channel length approaches the nano-scale regime, the reduction of the gate dielectric thickness is essential. However, the problems with scaling the gate dielectric thickness are the high gate leakage current and early dielectric breakdown of the insulator, deteriorating the device performance and reliability. A novel ultra-thin SiNx film suitable for the application as the gate dielectric of short channel TFTs and VTFTs is developed. The deposition is performed in a standard 13.56MHz PECVD system with silane and ammonia precursor gasses diluted in nitrogen. The deposited 50nm SiNx films demonstrate excellent electrical characteristics in terms of a leakage current of 0.1 nA/cm?? and a breakdown electric field of 5.6MV/cm. Subsequently, the state of the art performances of 0.5??m channel length VTFTs with 50 and 30nm thick SiNx gate dielectrics are presented in this thesis. The transistors exhibit ON/OFF current ratios over 10^9, the subthreshold slopes as sharp as 0.23 V/dec, and leakage currents in the fA range. More significantly, a high associated yield is obtained for the fabrication of these devices on 3-inch rigid substrates. Finally, to illustrate the tremendous potential of the VTFT for the large area electronics, a 2.2-inch QVGA AMOLD display with in-pixel VTFT-based driver circuits is designed and fabricated. An outstanding value of 56% compared to the 30% produced by conventional technology is achieved as the aperture ratio of the display. Moreover, the initial measurement results reveal an excellent uniformity of the circuit elements.

Scaling has been pivotal in the success of the Moore's law. Using scaling techniques to improve the MOSFET comes at a risk of growing short channel effects. This publication deals with the theoretical study of impact of gate length scaling on planar bulk MOSFET. A systematical study shows that the impact of short channel effects like drain induced barrier lowering, subthreshold leakage, hot carrier generation and channel length modulation grows with gate length scaling. Thereby degrading the MOSFET performance. In addition to the numerical device simulation an analytical modelling of the device is also performed. Though the analytical model explains the device characteristic trends, it is found to be quantitative inaccurate in comparison to the numerical model especially when scaling below deep sub-micrometer regime.

No description available.

<div>Silicon based semiconductor technology is facing more and more challenges to continue the Moore's law due to its fundamental scaling limitations. To continue the pace of progress of device performance for both logic and memory devices, researchers are exploring new low-dimensional materials, e.g. nanowire, nanotube, graphene and hexagonal boron nitride. Transition metal dichalcogenides (TMDs) are attracted considerable attention due their atomically thin nature and proper bandgap at the initial study. Recently, more and more interesting properties are found in these materials, which will bring out more potential usefulness for electronic applications. Competing with the silicon device performance is not the only goal in the potential path finding of beyond silicon. Low-dimensional materials may have other outstanding performances as an alternative materials in many application realms. </div><div><br></div><div>This thesis explores the potential of TMD based devices in memory and logic applications. For the memory application, TMD based vertical devices are fully studied. Two-terminal vertical transition metal dichalcogenide (TMD) based memory selectors were firstly built and characterized, exhibiting better overall performance compared with some traditional selectors. Polymorphism is one of unique properties in TMD materials. 2D phase engineering in TMDs attracted great attention. While electric switching between semiconductor phase to metallic phase is the most desirable. In this thesis, electric field induced structural transition in MoTe₂ and Mo_1-xW_xTe₂ is firstly presented. Reproducible bipolar resistive random access (RRAM) behavior is observed in MoTe₂ and Mo_1-xW_xTe₂ based vertical devices. Direct confirmation of a phase transition from a 2H semiconductor to a distorted 2H_d metallic phase was obtained after applying an electric field. Set voltage is changed with flake thickness, and switching speed is less than 5 ns. Different from conventional RRAM devices based on ionic migration, the MoTe₂-based RRAMs offer intrinsically better reliability and control. In comparison to phase change memory (PCM)-based devices that operate based on a change between an amorphous and a crystalline structure, our MoTe₂-based RRAM devices allow faster switching due to a transition between two crystalline states. Moreover, utilization of atomically thin 2D materials allows for aggressive scaling and high-performance flexible electronics applications. Both of the studies shine lights on the new application in the memory field with two-dimensional materials.<br></div><div><br></div><div>For the logic application, the ultra thin body nature of TMDs allows for more aggressive scaling compared with bulk material - silicon. Two aspects of scaling properties in TMD based devices are discussed, channel length scaling and channel width scaling. A tunability of short channel effects in MoS₂ field effect transistor (FET) is reported. The electrical performance of MoS₂ flakes is governed by an unexpected dependence on the effective body thickness of the device which in turn depends on the amount of intercalated water molecules that exist in the layered structure. In particular, we observe that the doping stage of a MoS₂ FET strongly depends on the environment (air/vacuum). For the channel width scaling, the impact of edge states in three types of TMDs, metallic T_d-phase WTe₂ as well as semiconducting 2H-phase MoTe₂ and MoS₂ were explored, by patterning thin flakes into ribbons with varying channel widths. No obvious charge depletion at the edges is observed for any of these three materials, which is different from what has been observed in graphene nanoribbon devices. </div>

This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Design Systems. The research presented in this thesis reveals a configuration that allows the multiplier to run at a speed of 8.2 GHz with end-point nonlinearity less than 5%. The high speed and low nonlinearity make this circuit ideal for applications such as filtering and digital to analog conversion.