<p>Here at ISY research is performed on network processors. In order to evaluate the processors there is a need to have full control of every aspect of the transmission. This is not the case if you use a proprietary technology. Therefore the need for a well documented gigabit Ethernet network interface has emerged. </p><p>The purpose of this thesis work has been to design and implement an open source gigabit Ethernet controller in a FPGA together with a device driver for the Linux operating system Implementation has been done in Verilog for the hardware part and the software was developed in C.</p><p>We have implemented a fully functional gigabit Ethernet interface onto a Xilinx Virtex II-1500 FPGA together with a Linux device driver. The design uses approximately 7200 LUTs and 48 block RAMs including the opencores PCI bridge.</p>

<p>Antalet kretskort som monteras i multikortssystem, till exempel telekommunikationssystem, ökar ständigt. Samtidigt som ytmonteringstekniken och packningstekniken blir allt bättre utvecklas även tillverkningsmetoderna för olika integrerade komponenter, vilket medför att varje kretskort rymmer allt fler integrerade komponenter. Detta gör att testning av integrerade komponenter och multikortsystem blir alltmer komplex. En förutsättning för att kunna genomföra effektiv testning är standarder. Standarder över hur testning ska genomföras medför att en komponent som uppfyller kraven från en standard är direkt utbytbar mot en komponent från en annan tillverkare som uppfyller kraven från samma standard. En god standard bidrar även till att utvecklingen drivs åt samma håll istället för att varje tillverkare har sin egen lösning och ett eget gränssnitt, vilket dessutom leder till att ett antal olika gränssnittsomvandlare behövs för att koppla samman olika komponenter. Internal Joint Test Action Group (IJTAG) arbetar just nu med att ta fram en standard för inbäddade testinstrument på mikronivå. De inbäddade instrumenten kan stödja karaktärisering av komponenter likväl som strukturell och funktionell testning. På makronivå arbetar System Joint Test Action Group (SJTAG) med att ta fram en standard för testadministration. Den främsta uppgiften är att koppla samman IJTAG-standarden med systemtestadministrationen. Behovet av ett kommunikationsprotokoll mellan dessa båda är stort. I denna rapport utvärderas Standard Test and Programming Language (STAPL) i syfte att se hur det passar som länk mellan testmanager och inbäddade instrument. Vidare identifieras ett antal brister i STAPL och ett förslag på en vidareutveckling av språket tas fram. Denna vidareutveckling syftar till att göra språket mer dynamiskt och passande för inbäddad testning via Boundary-Scan-protokollet. Slutligen implementeras en demonstrator som består av mjukvara som exekveras på en PC och en Field Programmable Gate Array (FPGA) som tjänar som testobjekt.</p>

<p>This report proposes a modular Application Programmer's Interface (API) for handling the mental layer of intelligent virtual agents for a wide range of application types, with the aim of reducing the work required to program a completely new AI engine, and describes its implementation. One of the key elements and major difficulties in its design is the need to make it general enough to suit most types of applications, while preserving its usefulness and keeping it both efficient and reliable. A sample application interfacing with the API is created to demonstrate its capabilities, various AI algorithms are looked into and their respective suitability for the API is evaluated, and some techniques are implemented as modules in the API.</p>

<p>As the embedded devices has become more and more generalized and as their product cycles keeps shrinking the field has opened up for the Application Specific Instruction set Processor. A mix between the classic generalized microcontroller and the specialized ASIC the ASIP keeps a set of general processing instructions for executing embedded software but combines that with a set of heavily specialized instructions for speeding up the data intense application core algorithms. One important aspect of the ASIP design flow</p><p>research is cutting design time and cost. One way of that is automation of the instruction set design. In order to do so a process is needed where the algorithm to be ASIPed is analyzed and critical operations are found and exposed so that they can be implemented in special hardware. This process is called profiling. This thesis describes an implementation of a fine grained source code profiler for use in an ASIP design flow. The profiler software is based on a static-dynamic workflow where data is assembled from both static</p><p>analysis and dynamic execution of the program and then analyzed together in an specially made analysis software.</p>

<p>This master thesis consists of implementation and evaluation of an AEC, Acoustic Echo Canceller, algorithm in a floating-point architecture. The most important question this thesis will try to answer is to determine benefits or drawbacks of using a floating-point architecture, relative a fixed-point architecture, to do AEC. In a telephony system there is two common forms of echo, line echo and acoustic echo. Acoustic echo is introduced by sound emanating from a loudspeaker, e.g. in a handsfree or speakerphone, being picked up by a microphone and then sent back to the source. The problem with this feedback is that the far-end speaker will hear one, or multiple, time-delayed version(s) of her own speech. This time-delayed version of speech is usually perceived as both confusing and annoying unless removed by the use of AEC. In this master thesis the performance of a floating-point version of a normalized least-mean-square AEC algorithm was evaluated in an environment designed and implemented to approximate live telephony calls. An instruction-set simulator and assembler available at the initiation of this master thesis were extended to enable; zero-overhead loops, modular addressing, post-increment of registers and register-write forwarding. With these improvements a bit-true assembly version was implemented capable of real-time AEC requiring 15 million instructions per second. A solution using as few as eight mantissa bits, in an external format used when storing data in memory, was found to have an insignificant effect on the selected AEC implementation’s performance. Due to the relatively low memory requirement of the selected AEC algorithm, the use of a small external format has a minor effect on the required memory size. In total this indicates that the possible reduction of the memory requirement and related energy consumption, does not justify the added complexity and energy consumption of using a floating-point architecture for the selected algorithm. Use of a floating-point format can still be advantageous in speech-related signal processing when the introduced time delay by a subband, or a similar frequency domain, solution is unacceptable. Speech algorithms that have high memory use and small introduced delay requirements are a good candidate for a floating-point digital signal processor architecture.</p>

<p>Ett ramverk för kontraktbaserad schemaläggning av dynamisk resursfördelning i realtidsoperativsystem ska rapporteras till operativsystemet OSE. Ramverket, som utvecklats i ett EU-forskningsprojekt, kräver uppmätt process exekveringstid för att fatta riktiga schemaläggningsbeslut. Sådana mätningar görs för närvarande inte i ENEAs RTOS OSE och examensarbetets syfte har därför varit att undersöka möjligheterna att implementera en sådan funktion. Alternativ har hittats och utvärderats, slutligen har ett valts för implementation. Funktionalilteten har verifierats och slutlilgen har prestanda utvärderats hos den implementerade mätningsmetoden.</p>

<p>Future parallel computer systems for embedded real-time applications,where each node in itself can be a parallel computer, are predicted to havevery high bandwidth demands on the interconnection network. Otherimportant properties are time-deterministic latency and guarantees to meetdeadlines. In this thesis, a fiber-optic passive optical star network with amedium access protocol for packet switched communication in distributedreal-time systems is proposed. By using WDM (Wavelength DivisionMultiplexing), multiple channels, each with a capacity of several Gb/s, areobtained.</p><p>A number of protocols for WDM star networks have recently been proposed.However, the area of real-time protocols for these networks is quiteunexplored. The protocol proposed in this thesis is based on TDMA (TimeDivision Multiple Access) and uses a new distributed slot-allocationalgorithm with real-time properties. Services for both guarantee-seekingmessages and best-effort messages are supported for single destination,multicast, and broadcast transmission. Slot reserving can be used toincrease the time-deterministic bandwidth, while still having an efficientbandwidth utilization due to a simple slot release method.</p><p>By connecting several clusters of the proposed WDM star network by abackbone star, thus forming a star-of-stars network, we get a modular andscalable high-bandwidth network. The deterministic properties of thenetwork are theoretically analyzed for both intra-cluster and inter-clustercommunication, and computer simulations of intra-cluster communicationare reported. Also, an overview of high-performance fiber-opticcommunication systems is presented.</p>

No description available.

<p>In recent years, so many networks are being built and some of the organizations are able to provide security to their networks. The performance of a network depends on the amount of security implemented on the network without compromising the network capabilities. For building a secure network, administrators should know all the possible attacks and their mitigation techniques and should perform risk analysis to find the risks involved in designing the network. And they must also know how to design security policies for implement the network and to educate the employees, to protect the organization’s information. The goal behind this case-study is to build a campus network which can sustain from reconnaissance attacks.</p><p>This thesis describes all the network attacks and explores their mitigation techniques. This will help an administrator to be prepared for the coming attacks. This thesis explains how to perform risk analysis and the two different ways to perform risk analysis. It also describes the importance of security policies and how security policies are designed in real world.</p>

<p>Denna rapporten är en jämförelse av forensiska verktyg, i detta fallet är verktygen EnCase och BackTrack. Vi kommer i den här rapporten att jämföra vissa utvalda verktyg som representeras i båda programmen, och analysera resultatet av detta. Analysen och jämförelsen kommer därefter ligga till grund för om man kan få fram lika bra resultat med ett open-source program som med ett program man betalar för. Vi kommer att utföra analysen genom att använda en bevisfil och utföra tester på den i både BackTrack och EnCase. Resultatet kommer att diskuteras och presenteras i denna rapport.För att få fram bästa möjliga resultat kommer vi även att intervjua vissa utvalda personer med erfarenhet utav att arbeta med dessa program, för att få fram deras synpunkter</p>