This thesis describes an optical fibre network that uses a bus topology and Code Division Multiple Access (CDMA). Various potential configurations are analysed and compared and it is shown that a serious limitation of optical CDMA schemes using incoherent correlators is the effect of optical beating due to the presence of multiple incoherent optical signals at the receiver photodiode. The network proposed and analysed in this thesis avoids beating between multiple optical fields because it only uses a single, shared, optical source. It does this through the SLIM (Single Light-source with In-line Modulation) configuration in which there is a continuously-operating light source at the head-end of a folded bus, and modulators at the nodes to impose signals on the optical field in the form of pulses of darkness which propagate along the otherwise continuously bright bus. Optical CDMA can use optical-fibre delay-line correlators as matched filters, and these may be operated either coherently or incoherently.Coherent operation is significantly more complex than incoherent operation, but incoherent correlators introduce further beating even in a SLIM network. A new design of optical delay-line correlator, the hybrid correlator, is therefore proposed, analysed and demonstrated. It is shown to eliminate beating. A model of a complete network predicts that a SLIMbus using optical CDMA with hybrid correlators can be operated at TeraBaud rates with the number of simultaneous users limited by multiple access interference (MAI), determined only by the combinatorics of the code set.

International Telemetering Conference Proceedings / October 25-28, 1993 / Riviera Hotel and Convention Center, Las Vegas, Nevada / In order to reduce the measuring channels for the single-transient signals, the author propose the time division multiplex technique and introduce the method of SAW delay line in this paper. That used method of SAW tap-delay line in this system is different from previous methods consists in making traditional method, which is one-path signal input different delayed multi- path signals output, alter new method, which is simultaneous multi-path signal inputs that are respectively delayed and one-path signal serial output.

ITC/USA 2011 Conference Proceedings / The Forty-Seventh Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2011 / Bally's Las Vegas, Las Vegas, Nevada / This paper describes the development and test results of a Frequency Modulated Continuous Wave (FMCW) L-Band radar testbed designed to detect obstacles in the proximity of an Unmanned Aerial Vehicle (UAV). From laboratory loopback tests, it was calculated that with pulse compression and a transmit power of 150 mW (22 dBm), the radar is capable of detecting an object with a 0.014-m2 radar cross-sectional area at ranges between 500 ft to 1 mi. Analysis shows that post processing of the collected data would reveal information about the obstacle such as its range and location relative to the aircraft. Design and testing procedures are discussed.

International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California / This paper analyzes the probability of bit error for PCM-FM over a standard IRIG channel subject to multipath interference modeled by the aeronautical fading channel. The aeronautical channel model assumes a mobile transmitter and a stationary receiver and specifies the correlation of the fading component. This model describes fading which is typical of that encountered at military test ranges. An expression for the bit error rate on the fading channel with a delay line demodulator is derived and compared with the error rate for the Gaussian channel. The increase in bit error rate over that of the Gaussian channel is determined along with the power penalty caused by the fading. In addition, the effects of several channel parameters on the probability of bit error are determined.

This work presents design techniques for the implementation of high-speed analog integrated circuits for wireless and wireline communications systems. Limitations commonly found in high-speed switched-capacitor (SC) circuits used for intermediate frequency (IF) filters in wireless receivers are explored. A model to analyze the aliasing effects due to periodical non-uniform individual sampling, a technique used in high-Q high-speed SC filters, is presented along with practical expressions that estimate the power of the generated alias components. The results are verified through circuit simulation of a 10.7MHz bandpass SC filter in TSMC 0.35mu-m CMOS technology. Implications on the use of this technique on the design of IF filters are discussed. To improve the speed at which SC networks can operate, a continuous-time common-mode feedback (CMFB) with reduced loading capacitance is proposed. This increases the achievable gain-bandwidth product (GBW) of fully-differential ampli- fiers. The performance of the CMFB is demonstrated in the implementation of a second-order 10.7MHz bandpass SC filter and compared with that of an identical filter using the conventional switched-capacitor CMFB (SC-CMFB). The filter using the continuous-time CMFB reduces the error due to finite GBW and slew rate to less than 1% for clock frequencies up to 72MHz while providing a dynamic range of 59dB and a PSRR- > 22dB. The design of high-speed transversal equalizers for wireline transceivers requires the implementation of broadband delay lines. A delay line based on a third-order linear-phase filter is presented for the implementation of a fractionally-spaced 1Gb/s transversal equalizer. Two topologies for a broadband summing node which enable the placement of the parasitic poles at the output of the transversal equalizer beyond 650MHz are presented. Using these cells, a 5-tap 1Gb/s equalizer was implemented in TSMC 0.35mu-m CMOS technology. The results show a programmable frequency response able to compensate up to 25dB loss at 500MHz. The eye-pattern diagrams at 1Gb/s demonstrate the equalization of 15 meters and 23 meters of CAT5e twistedpair cable, with a vertical eye-opening improvement from 0% (before the equalizer) to 58% (after the equalizer) in the second case. The equalizer consumes 96mW and an area of 630mu-m x 490mu-m.

Nowadays, Multi-GHz analog-to-digital converters (ADCs) are becoming more and more popular in radar systems, software-de ned radio (SDR) and wideband communications, because they can realize much higher operation speed through using many interleaved sub-ADCs to relax ADC sampling rates. Although the time interleaved ADC has some issues such as gain mismatch, o set mismatch and timing skew between each ADC channel, these deterministic errors can be solved by previous works such as digital calibration technique. However, time-interleaved ADCs require a precise sample clock to achieve an acceptable e ective-numberof- bits (ENOB) which can be degraded by jitter in the sample clock. The clock generation circuits presented in this work achieves sub-picosecond jitter performance in 180nm CMOS which is suitable for time-interleaved ADC. Two di erent test chips were fabricated in 180nm CMOS to investigate the low jitter design technique. The low jitter delay line in two chips were designed in two di erent ways, but both of them utilized the low jitter design technique. In rst test chip, the measured RMS jitter is 0.1061ps for each delay stage. The second chip uses the proposed low jitter Delay-Locked Loop can work from 80MHz to 120MHz, which means it can provide the time interleaved ADC with 2.4GHz to 3.6GHz low jitter sample clock, the measured delay stage jitter performance in second test chip is 0.1085ps.

Neutron imaging is a non-destructive technique with many applications in diverse fields such as industrial quality assurance, archaeology, and border security. However with the high cost of the standard fill gas 3He and the high cost of scaling conventional digital imaging systems to large areas its applications are limited. Here is presented the proof of concept for a gaseous neutron imaging system utilizing a 10B4C solid state converter and THGEM technology and 2D passive delay line readout. THGEMs used for signal amplification can be produced cost effectively and in large areas by PCB manufacturers. This combined with the reduced channel processing requirements of delay lines over individual pixel readouts results in a cost-effective and scalable system when compared to similar designs using solid state multipliers such as silicon photomultipliers. Here is presented a proof of concept of this imaging system with data acquisition accomplished by digitization and offline image reconstruction achieving mean X and Y resolution of <sigma_x> = (1.37+-0.24) mm and <sigma_y> = (1.15+-0.13) mm respectively. Studied in parallel with this system is the effectiveness of gadolinium oxide based paint as a thermal neutron shield and image contrast agent. / Thesis / Doctor of Philosophy (PhD) / In this work is presented the development process of a novel and cost-effective neutron imaging system capable of imaging soft biological and dense materials that X-rays are unable to penetrate. Such a system may be scaled to large areas for many applications including the study of large archeological objects or employed as a security measure to monitor border checkpoints for transportation of controlled radioactive materials.

The fusion of voice and data applications, along with the demand for high data-rate applications such as video-on-demand, is making radio frequency (RF) spectrum an increasingly expensive commodity for current and future communications. Although bandwidth-efficient digital modulation alleviates part of the problem by requiring a minimal use of spectral resources, they put an extra design burden on RF engineers. RF transmitters and power amplifiers account for more than half the total maintenance cost of a base-station, while occupying nearly the same portion of space. Therefore, power amplifiers become a bottleneck for digital systems in terms of space and power consumption. However, power-efficient use of the amplifiers, although desirable, is extremely detrimental to end-to-end performance due to the very high peak-to-average power ratios of modulations that are used today. In order to reduce distortion while maintaining high power conversion efficiency in a power amplifier, linearization schemes are needed. In addition, significant frequency-dependent Memory Effects result in high power amplifiers operating on wideband signals. Therefore, these effects need to be considered during any attempt to minimize amplifier distortion. In this thesis, we present two schemes to cancel nonlinear distortion of a power amplifier, along with its memory effects and results for one of the schemes. The results highlight the fact that in the presence of significant memory effects, cancellation of these effects is necessary to achieve reasonable improvement in performance through linearization. We focus on predistortive schemes due to their digital- friendly structure and simple implementation. The operating environment consists of a multi-carrier W-CDMA signal. All of the studies are performed using numerical simulation on MATLAB and Agilent's Advanced Design System (ADS). / Master of Science

<p>With an increasing number of transistors integrated on a single die, the need for global on-chip interconnectivity is growing. Long interconnects, in turn, have very large capacitances which consume a large share of a chip’s total power budget.</p><p>Power consumption can be lowered in several ways, mainly by reduction of switching activity, reduction of total capacitance and by using low voltage swing. In this project, the issue is addressed by proposing a new encoding based on Pulse Width Modulation (PWM). The implementation of this encoding will both lower the switching activity and decrease the capacitance between nearby wires. Hence, the total effective capacitance will be reduced considerably. Schematic level implementation of a robust transmitter and receiver circuit was carried out in CMOS090, designed for speeds up to 100 MHz. On a 10 mm wire, this implementation would give a 40% decrease in power dissipation compared to a parallel bus having the same metal footprint. The proposed encoding can be efficiently applied for global interconnects in sub-micron systems-on-chip (SoC).</p>

<p>Class D amplifiers are becoming increasingly popular in audio devices. The strongest reason is the high efficiency which makes it advantageous for portable battery-driven products.</p><p>Infineon Technologies is developing products in this area, and has recently filed a patent application regarding an implementation of a part of the class D amplifier. The aim of this Master’s thesis is to evaluate a digital open-loop implementation of a class D amplifier, using the pending patent solution, and discuss the differences from an analog closed-loop implementation.</p><p>The focus has been on generating a high resolution PWM signal with a relatively low clock frequency. To achieve this, a hybrid of a counter and a self-calibrating tapped delay-line are used as a pulse generator. A model of the pulse generator was developed which made it possible to study how sampling frequency and different types of quantization affected quality parameters such as THD and SNR. With the results from the model two systems were implemented and simulated in HDL and as circuit schematics.</p><p>The proposed digital open-loop class D amplifier was found to be useful in voice-band applications and for music. Since the open-loop structure suffers from poor rejection of power supply ripple, either error correction or a regulated power supply is needed. If much effort is put on the different parts of the amplifier the result can be really good but, depending on other constraints on the system, it may be simpler and less time consuming to use the analog circuit with feedback to achieve hi-fi quality.</p><p>In summary, the combination of a counter and a self-calibrating tapped delay-line as a pulse generator is very useful in high resolution low-power systems. To avoid errors the delay-line and calibration can be made very accurate but with the expense of higher power consumption and area. However, the technique benefits from the small and fast logic devices available in deep sub-micron process technologies, which may finally lead to an advantage in power consumption and cost over the closed-loop analog solution.</p>