<p>The Stressometer system is a measurement and control system used in cold rolling to improve the flatness of a metal strip. In order to achieve this goal the system employs a multiple input multiple output (MIMO) control system that has a considerable number of sensors and actuators. As a consequence the computational load on the Stressometer control system becomes very high if too advance functions are used. Simultaneously advances in rolling mill mechanical design makes it necessary to implement more complex functions in order for the Stressometer system to stay competitive. Most industrial players in this market considers improved computational power, for measurement, control and modeling applications, to be a key competitive factor. Accordingly there is a need to improve the computational power of the Stressometer system. Several different approaches towards this objective have been identified, e.g. exploiting hardware parallelism in modern general purpose and graphics processors.</p><p>Another approach is to implement different applications in FPGA-based hardware, either tailored to a specific problem or as a part of hardware/software co-design. Through the use of a hardware/software co-design approach the efficiency of the Stressometer system can be increased, lowering overall demand for processing power since the available resources can be exploited more fully. Hardware accelerated platforms can be used to increase the computational power of the Stressometer control system without the need for major changes in the existing hardware. Thus hardware upgrades can be as simple as connecting a cable to an accelerator platform while hardware/software co-design is used to find a suitable hardware/software partition, moving applications between software and hardware.</p><p>In order to determine whether this hardware/software co-design approach is realistic or not, the feasibility of implementing simulator, computational and control applications in FPGAbased hardware needs to be determined. This is accomplished by selecting two specific applications for a closer study, determining the feasibility of implementing a Stressometer measuring roll simulator and a parallel Cholesky algorithm in FPGA-based hardware.</p><p>Based on these studies this work has determined that the FPGA device technology is perfectly suitable for implementing both simulator and computational applications. The Stressometer measuring roll simulator was able to approximate the force and pulse signals of the Stressometer measuring roll at a relative modest resource consumption, only consuming 1747 slices and eight DSP slices. This while the parallel FPGA-based Cholesky component is able to provide performance in the range of GFLOP/s, exceeding the performance of the personal computer used for comparison in several simulations, although at a very high resource consumption. The result of this thesis, based on the two feasibility studies, indicates that it is possible to increase the processing power of the Stressometer control system using the FPGA device technology.</p>

HARDWARE TESTING is commonly used to check whether faults exist in a digital system. Much research has been devoted to the development of advanced hardware testing techniques and methods to support design for testability (DFT). However, most existing DFT methods deal only with testability issues at low abstraction levels, while new modelling and design techniques have been developed for design at high abstraction levels due to the increasing complexity of digital systems. The main objective of this thesis is to address test problems faced by the designer at the system level. Considering the testability issues at early design stages can reduce the test problems at lower abstraction levels and lead to the reduction of the total test cost. The objective is achieved by developing several new methods to help the designers to analyze the testability and improve it as well as to perform test scheduling and test access mechanism design. The developed methods have been integrated into a systematic methodology for the testing of system-on-chip. The methodology consists of several efficient techniques to support test scheduling, test access mechanism design, test set selection, test parallelization and test resource placement. An optimization strategy has also been developed which minimizes test application time and test access mechanism cost, while considering constraints on tests, power consumption and test resources. Several novel approaches to analyzing the testability of a system at behavioral level and register-transfer level have also been developed. Based on the analysis results, difficult-to-test parts of a design are identified and modified by transformations to improve testability of the whole system. Extensive experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodology and techniques. The experimental results show clearly the advantages of considering testability in the early design stages at the system level.

The Stressometer system is a measurement and control system used in cold rolling to improve the flatness of a metal strip. In order to achieve this goal the system employs a multiple input multiple output (MIMO) control system that has a considerable number of sensors and actuators. As a consequence the computational load on the Stressometer control system becomes very high if too advance functions are used. Simultaneously advances in rolling mill mechanical design makes it necessary to implement more complex functions in order for the Stressometer system to stay competitive. Most industrial players in this market considers improved computational power, for measurement, control and modeling applications, to be a key competitive factor. Accordingly there is a need to improve the computational power of the Stressometer system. Several different approaches towards this objective have been identified, e.g. exploiting hardware parallelism in modern general purpose and graphics processors. Another approach is to implement different applications in FPGA-based hardware, either tailored to a specific problem or as a part of hardware/software co-design. Through the use of a hardware/software co-design approach the efficiency of the Stressometer system can be increased, lowering overall demand for processing power since the available resources can be exploited more fully. Hardware accelerated platforms can be used to increase the computational power of the Stressometer control system without the need for major changes in the existing hardware. Thus hardware upgrades can be as simple as connecting a cable to an accelerator platform while hardware/software co-design is used to find a suitable hardware/software partition, moving applications between software and hardware. In order to determine whether this hardware/software co-design approach is realistic or not, the feasibility of implementing simulator, computational and control applications in FPGAbased hardware needs to be determined. This is accomplished by selecting two specific applications for a closer study, determining the feasibility of implementing a Stressometer measuring roll simulator and a parallel Cholesky algorithm in FPGA-based hardware. Based on these studies this work has determined that the FPGA device technology is perfectly suitable for implementing both simulator and computational applications. The Stressometer measuring roll simulator was able to approximate the force and pulse signals of the Stressometer measuring roll at a relative modest resource consumption, only consuming 1747 slices and eight DSP slices. This while the parallel FPGA-based Cholesky component is able to provide performance in the range of GFLOP/s, exceeding the performance of the personal computer used for comparison in several simulations, although at a very high resource consumption. The result of this thesis, based on the two feasibility studies, indicates that it is possible to increase the processing power of the Stressometer control system using the FPGA device technology.

Une des avancées les plus notables de ces dernières années en cryptographie est sans contredit l’introduction du premier schéma de chiffrement complètement homomorphe par Craig Gentry. Ce type de système permet de réaliser des calculs arbitraires sur des données chiffrées, sans les déchiffrer. Cette particularité permet de répondre aux exigences de sécurité et de protection des données, par exemple dans le cadre en plein développement de l'informatique en nuage et de l'internet des objets. Les algorithmes mis en œuvre sont actuellement très coûteux en temps de calcul, et généralement implantés sous forme logicielle. Les travaux de cette thèse portent sur l’accélération matérielle de schémas de chiffrement homomorphes. Une étude des primitives utilisées par ces schémas et la possibilité de leur implantation matérielle est présentée. Ensuite, une nouvelle approche permettant l’implantation des deux fonctions les plus coûteuses est proposée. Notre approche exploite les capacités offertes par la synthèse de haut niveau. Elle a la particularité d’être très flexible et générique et permet de traiter des opérandes de tailles arbitraires très grandes. Cette particularité lui permet de viser un large domaine d’applications et lui autorise d’appliquer des optimisations telles que le batching. Les performances de notre architecture de type co-conception ont été évaluées sur l’un des cryptosystèmes homomorphes les plus récents et les plus efficaces. Notre approche peut être adaptée aux autres schémas homomorphes ou plus généralement dans le cadre de la cryptographie à base de réseaux. / One of the most significant advances in cryptography in recent years is certainly the introduction of the first fully homomorphic encryption scheme by Craig Gentry. This type of cryptosystem allows performing arbitrarily complex computations on encrypted data, without decrypting it. This particularity allows meeting the requirements of security and data protection, for example in the context of the rapid development of cloud computing and the internet of things. The algorithms implemented are currently very time-consuming, and most of them are implemented in software. This thesis deals with the hardware acceleration of homomorphic encryption schemes. A study of the primitives used by these schemes and the possibility of their hardware implementation is presented. Then, a new approach allowing the implementation of the two most expensive functions is proposed. Our approach exploits the high-level synthesis. It has the particularity of being very flexible and generic and makes possible to process operands of arbitrary large sizes. This feature allows it to target a wide range of applications and to apply optimizations such as batching. The performance of our co-design was evaluated on one of the most recent and efficient homomorphic cryptosystems. It can be adapted to other homomorphic schemes or, more generally, in the context of lattice-based cryptography.

Este trabalho consiste na especificação e desenvolvimento da arquitetura de um Comutador Digital para TDM Determinístico E1, visando sua posterior implementação em microeletrônica. Inicialmente são apresentados os conceitos gerais sobre os Sistemas de Comutação, bem como das principais modalidades de comutação, seguidos de um estudo aprofundado da Comutação de Circuitos e suas técnicas mais utilizadas, devido a sua Intima relação com a multiplexação TDM e a hierarquia E1. Do mesmo modo, são descritas as características das Redes Corporativas E1 e dos multiplexadores E1, junto com as funções principais do Comutador dentro do ambiente de uma rede ponto-a-ponto. Com base no estudo prévio, e proposta a arquitetura de um Comutador Digital baseado em técnicas TSI capaz de fornecer funções de comutação local e remota entre os dispositivos conectados aos multiplexadores El, que formam os nos de uma Rede Corporativa com controle centralizado. 0 projeto logico e a simulação do Comutador Digital foram realizados dentro do framework SOLO/Cadence, usando a biblioteca de Standard Cells da tecnologia CMOS de 1.2µ. O simulador lógica SILOS, disponível no SOLO/Cadence, foi utilizado para validar a arquitetura proposta. Detalhes de implementação e resultados de simulação são apresentados. O módulo de controle do Comutador Digital e apenas especificado. / This work consists in the specification and development of a Digital Circuit Switch architecture for E1l Deterministic TDM, looking toward a future microelectronics implementation. First, general concepts about Switching Systems and its basic elements, as well as the main kinds of switching are presented. Also, a meticulous study about Circuit Switching and its more used techniques is realized, because of the intrinsec relation with TDM and E1 hierarchy. In the same way, the characteristics of E1 Corporate Networks and E1 multiplexers are described, along with the main functions of the Digital Switch into an end-to-end network. Taking into account the previous study, the architecture of a Digital Switch based on TSI techniques, is proposed. This architecture is able to perform local and remote switching between the devices connected to E1 multiplexers, which form the network nodes of an end-to-end Corporate Network. The logic design and the circuit simulation of the Digital Switch were performed within SOLO/Cadence Standard Cells desing framework, using CMOS 1.2µ technology. The logic simulator SILOS was used to validate the proposed architecture. Implementation details and simulation results are presented. The Control module of the Digital Switch is only specified.

Este trabalho apresenta os mecanismos de gerencia de configurações para o ambiente STAR. STAR é uma plataforma para o desenvolvimento de ambientes para projetos de circuitos e sistemas eletrônicos que está sendo desenvolvido na Universidade Federal do Rio Grande do Sul em cooperação com o Centro Científico da IBM no Rio de Janeiro. Seus objetos de projeto caracterizam-se como sistemas complexos e são representados através de um modelo de dados hierárquico, que tem por base a composição de objetos. Para expressar a evolução dos objetos de projeto no tempo utiliza-se versões, que mantêm as descrições dos objetos num determinado instante de tempo. O mecanismo de gerência de versões é fortemente relacionado à representação dos dados, suportando as diferentes dimensões que essa representação permite: visões, alternativas e revisões. A utilização de versões associada à composição de objetos faz com que se possa ter diversas possibilidades de descrição para um mesmo sistema complexo, em função da combinação das versões. Para que se possa submeter um objeto de projeto a uma ferramenta, como um simulador, épreciso selecionar versões de modo a obter uma descrição única, que é a sua configuração. A existência de um gerente de configurações dá agilidade a essa tarefa, pois ele oferece recursos para facilitar e tornar mais rápida a construção de configurações, através de manipulação e consultas a informações obtidas junto ao ambiente sobre os objetos de projeto. As configurações no STAR são determinadas a partir do atributo de referência dos componentes ou através da definição de um objeto - configuração. O gerente de configurações proposto para o ambiente neste trabalho suporta o estabelecimento de configurações estáticas, dinâmicas e abertas. Elas podem ser estabelecidas manualmente, através de escolhas do usuário, automaticamente, através da escolha entre um dos critérios pré-estabelecidos, ou de modo semi-automático, através da definição de uma expressão de configuração. Os critérios pré-estabelecidos têm por base a versão corrente e a versão mais recente. A utilização de expressões de configuração permite que se selecione versões com mais objetividade, uma vez que sua construção é feita a partir de características dos objetos, dadas por seus atributos, que permitem restringir as versões selecionadas àquelas cujas características são desejadas. A linguagem que permite a definição de expressões de configuração é um dos recursos estabelecidos que facilitam a tarefa do usuário. Outro recurso provido é a possibilidade de armazenar configurações. Isso torna possível sua reutilização em outros momentos e também por outros objetos, e preserva a flexibilidade de mantê-las como dinâmicas, ou abertas, apesar de já ter-se escolhido versões para complementá-las. Para tanto, tem-se como parte do modelo de dados os objetos-configuração, sobre os quais foram estabelecidas operações de criação, alteração, cópia, remoção, consulta e escolha de objetos. O funcionamento destas operações é a base do processo de configuração. / This work presents the mechanisms for configuration management in the STAR framework. STAR is an electronic design automation framework, under development at the University of Rio Grande do Sul in cooperation with the IBM Rio Scientific Center at Rio de Janeiro, Brazil. The design objects supported are complex systems and they are represented through a hierarchical data model. Versions are used to express the evolution process of design objects. The version management mechanism developed is strongly related with the data representation, and it supports the different dimensions of versions: views, alternatives and revisions. The use of versions associated with composite objects allows the existence of many possibilities of description for the same complex system, as a consequence of different versions combination. When submitting a design object to a design tool, like a simulator, it is necessary to select versions for components in order to obtain a single object description, called the object configuration. A configuration manager offers resources, as manipulation and query on design objects in the framework, to make version selection in configuration construction easy and fast. STAR configurations are established through component reference attributes or through a configuration object definition. The configuration management mechanism developed for the STAR framework in this work supports static, dynamic and open configurations. They are established in a manual, automatic or semi-automatic way. In the manual way, the user is responsible for choosing the selected versions. In the automatic way, it is possible to choose between the current version and the most recent version, which are pre-defined criteria. The user can define and use configuration expressions in a semi-automatic way. These expressions make the version selection objective, due to use of objects attributes, representing objects characteristics in the expression. The use of configuration expressions allows the selection of versions with specific characteristics. A language is available for the definition of configuration expressions. The possibility to store configurations is provided. Configurations may be reused in another time and by other objects. The possibility to store configurations allows them remain either dynamic or open, even if the choose of versions to complement them had been done. To make this possible, configuration objects are integrated in the data model. Operations on configuration objects are: create, update, copy, delete, query and select. These operations are the basis of the configuration process.

Este trabalho apresenta os mecanismos de gerencia de configurações para o ambiente STAR. STAR é uma plataforma para o desenvolvimento de ambientes para projetos de circuitos e sistemas eletrônicos que está sendo desenvolvido na Universidade Federal do Rio Grande do Sul em cooperação com o Centro Científico da IBM no Rio de Janeiro. Seus objetos de projeto caracterizam-se como sistemas complexos e são representados através de um modelo de dados hierárquico, que tem por base a composição de objetos. Para expressar a evolução dos objetos de projeto no tempo utiliza-se versões, que mantêm as descrições dos objetos num determinado instante de tempo. O mecanismo de gerência de versões é fortemente relacionado à representação dos dados, suportando as diferentes dimensões que essa representação permite: visões, alternativas e revisões. A utilização de versões associada à composição de objetos faz com que se possa ter diversas possibilidades de descrição para um mesmo sistema complexo, em função da combinação das versões. Para que se possa submeter um objeto de projeto a uma ferramenta, como um simulador, épreciso selecionar versões de modo a obter uma descrição única, que é a sua configuração. A existência de um gerente de configurações dá agilidade a essa tarefa, pois ele oferece recursos para facilitar e tornar mais rápida a construção de configurações, através de manipulação e consultas a informações obtidas junto ao ambiente sobre os objetos de projeto. As configurações no STAR são determinadas a partir do atributo de referência dos componentes ou através da definição de um objeto - configuração. O gerente de configurações proposto para o ambiente neste trabalho suporta o estabelecimento de configurações estáticas, dinâmicas e abertas. Elas podem ser estabelecidas manualmente, através de escolhas do usuário, automaticamente, através da escolha entre um dos critérios pré-estabelecidos, ou de modo semi-automático, através da definição de uma expressão de configuração. Os critérios pré-estabelecidos têm por base a versão corrente e a versão mais recente. A utilização de expressões de configuração permite que se selecione versões com mais objetividade, uma vez que sua construção é feita a partir de características dos objetos, dadas por seus atributos, que permitem restringir as versões selecionadas àquelas cujas características são desejadas. A linguagem que permite a definição de expressões de configuração é um dos recursos estabelecidos que facilitam a tarefa do usuário. Outro recurso provido é a possibilidade de armazenar configurações. Isso torna possível sua reutilização em outros momentos e também por outros objetos, e preserva a flexibilidade de mantê-las como dinâmicas, ou abertas, apesar de já ter-se escolhido versões para complementá-las. Para tanto, tem-se como parte do modelo de dados os objetos-configuração, sobre os quais foram estabelecidas operações de criação, alteração, cópia, remoção, consulta e escolha de objetos. O funcionamento destas operações é a base do processo de configuração. / This work presents the mechanisms for configuration management in the STAR framework. STAR is an electronic design automation framework, under development at the University of Rio Grande do Sul in cooperation with the IBM Rio Scientific Center at Rio de Janeiro, Brazil. The design objects supported are complex systems and they are represented through a hierarchical data model. Versions are used to express the evolution process of design objects. The version management mechanism developed is strongly related with the data representation, and it supports the different dimensions of versions: views, alternatives and revisions. The use of versions associated with composite objects allows the existence of many possibilities of description for the same complex system, as a consequence of different versions combination. When submitting a design object to a design tool, like a simulator, it is necessary to select versions for components in order to obtain a single object description, called the object configuration. A configuration manager offers resources, as manipulation and query on design objects in the framework, to make version selection in configuration construction easy and fast. STAR configurations are established through component reference attributes or through a configuration object definition. The configuration management mechanism developed for the STAR framework in this work supports static, dynamic and open configurations. They are established in a manual, automatic or semi-automatic way. In the manual way, the user is responsible for choosing the selected versions. In the automatic way, it is possible to choose between the current version and the most recent version, which are pre-defined criteria. The user can define and use configuration expressions in a semi-automatic way. These expressions make the version selection objective, due to use of objects attributes, representing objects characteristics in the expression. The use of configuration expressions allows the selection of versions with specific characteristics. A language is available for the definition of configuration expressions. The possibility to store configurations is provided. Configurations may be reused in another time and by other objects. The possibility to store configurations allows them remain either dynamic or open, even if the choose of versions to complement them had been done. To make this possible, configuration objects are integrated in the data model. Operations on configuration objects are: create, update, copy, delete, query and select. These operations are the basis of the configuration process.

Este trabalho consiste na especificação e desenvolvimento da arquitetura de um Comutador Digital para TDM Determinístico E1, visando sua posterior implementação em microeletrônica. Inicialmente são apresentados os conceitos gerais sobre os Sistemas de Comutação, bem como das principais modalidades de comutação, seguidos de um estudo aprofundado da Comutação de Circuitos e suas técnicas mais utilizadas, devido a sua Intima relação com a multiplexação TDM e a hierarquia E1. Do mesmo modo, são descritas as características das Redes Corporativas E1 e dos multiplexadores E1, junto com as funções principais do Comutador dentro do ambiente de uma rede ponto-a-ponto. Com base no estudo prévio, e proposta a arquitetura de um Comutador Digital baseado em técnicas TSI capaz de fornecer funções de comutação local e remota entre os dispositivos conectados aos multiplexadores El, que formam os nos de uma Rede Corporativa com controle centralizado. 0 projeto logico e a simulação do Comutador Digital foram realizados dentro do framework SOLO/Cadence, usando a biblioteca de Standard Cells da tecnologia CMOS de 1.2µ. O simulador lógica SILOS, disponível no SOLO/Cadence, foi utilizado para validar a arquitetura proposta. Detalhes de implementação e resultados de simulação são apresentados. O módulo de controle do Comutador Digital e apenas especificado. / This work consists in the specification and development of a Digital Circuit Switch architecture for E1l Deterministic TDM, looking toward a future microelectronics implementation. First, general concepts about Switching Systems and its basic elements, as well as the main kinds of switching are presented. Also, a meticulous study about Circuit Switching and its more used techniques is realized, because of the intrinsec relation with TDM and E1 hierarchy. In the same way, the characteristics of E1 Corporate Networks and E1 multiplexers are described, along with the main functions of the Digital Switch into an end-to-end network. Taking into account the previous study, the architecture of a Digital Switch based on TSI techniques, is proposed. This architecture is able to perform local and remote switching between the devices connected to E1 multiplexers, which form the network nodes of an end-to-end Corporate Network. The logic design and the circuit simulation of the Digital Switch were performed within SOLO/Cadence Standard Cells desing framework, using CMOS 1.2µ technology. The logic simulator SILOS was used to validate the proposed architecture. Implementation details and simulation results are presented. The Control module of the Digital Switch is only specified.

Made available in DSpace on 2014-10-09T12:53:57Z (GMT). No. of bitstreams: 0 / Made available in DSpace on 2014-10-09T14:09:29Z (GMT). No. of bitstreams: 0 / Tese (Doutoramento) / IPEN/T / Instituto de Pesquisas Energéticas e Nucleares - IPEN-CNEN/SP

Este trabalho consiste na especificação e desenvolvimento da arquitetura de um Comutador Digital para TDM Determinístico E1, visando sua posterior implementação em microeletrônica. Inicialmente são apresentados os conceitos gerais sobre os Sistemas de Comutação, bem como das principais modalidades de comutação, seguidos de um estudo aprofundado da Comutação de Circuitos e suas técnicas mais utilizadas, devido a sua Intima relação com a multiplexação TDM e a hierarquia E1. Do mesmo modo, são descritas as características das Redes Corporativas E1 e dos multiplexadores E1, junto com as funções principais do Comutador dentro do ambiente de uma rede ponto-a-ponto. Com base no estudo prévio, e proposta a arquitetura de um Comutador Digital baseado em técnicas TSI capaz de fornecer funções de comutação local e remota entre os dispositivos conectados aos multiplexadores El, que formam os nos de uma Rede Corporativa com controle centralizado. 0 projeto logico e a simulação do Comutador Digital foram realizados dentro do framework SOLO/Cadence, usando a biblioteca de Standard Cells da tecnologia CMOS de 1.2µ. O simulador lógica SILOS, disponível no SOLO/Cadence, foi utilizado para validar a arquitetura proposta. Detalhes de implementação e resultados de simulação são apresentados. O módulo de controle do Comutador Digital e apenas especificado. / This work consists in the specification and development of a Digital Circuit Switch architecture for E1l Deterministic TDM, looking toward a future microelectronics implementation. First, general concepts about Switching Systems and its basic elements, as well as the main kinds of switching are presented. Also, a meticulous study about Circuit Switching and its more used techniques is realized, because of the intrinsec relation with TDM and E1 hierarchy. In the same way, the characteristics of E1 Corporate Networks and E1 multiplexers are described, along with the main functions of the Digital Switch into an end-to-end network. Taking into account the previous study, the architecture of a Digital Switch based on TSI techniques, is proposed. This architecture is able to perform local and remote switching between the devices connected to E1 multiplexers, which form the network nodes of an end-to-end Corporate Network. The logic design and the circuit simulation of the Digital Switch were performed within SOLO/Cadence Standard Cells desing framework, using CMOS 1.2µ technology. The logic simulator SILOS was used to validate the proposed architecture. Implementation details and simulation results are presented. The Control module of the Digital Switch is only specified.