Analyzing modern day's information systems that produce humongous multi-dimensional data in form of logs, traces or events that unfold over time can be tedious without adequate visualization, thereby, advocating the need for an intelligible visualization. This thesis researched and developed a visualization framework that represents multi-dimensional dynamic and temporal process data in a potentially intelligible and actionable form. A prototype showing four different views using notional malware data abstracted from Normal Sandbox behavioral traces were developed. In particular, the B-matrix view representing the DLL files used by the malware to attack a system. This representation is aimed at visualizing large data sets without losing emphasis on the process unfolding over multiple dimensions.

As the CMOS technology continues to scale into the deep sub-micron regime, the demand for higher frequencies and higher levels of integration poses a significant challenge for the clock generation and distribution design of microprocessors. Hence, skew optimization schemes are necessary to limit clock inaccuracies to a small fraction of the clock period. In this thesis, a crude deskew buffer (CDB) is designed to facilitate an adaptive deskewing scheme that reduces the clock skew in an ASIC clock network under manufacturing process, supply voltage, and temperature (PVT)variations. The crude deskew buffer adopts a DLL structure and functions on a 1GHz nominal clock frequency with an operating frequency range of 800MHz to 1.2GHz. An approximate 91.6ps phase resolution is achieved for all simulation conditions including various process corners and temperature variation. When the crude deskew buffer is applied to seven ASIC clock networks with each under various PVT variations, a maximum of 67.1% reduction in absolute maximum clock skew has been achieved. Furthermore, the maximum phase difference between all the clock signals in the seven networks have been reduced from 957.1ps to 311.9ps, a reduction of 67.4%. Overall, the CDB serves two important purposes in the proposed deskewing methodology: reducing the absolute maximum clock skew and synchronizes all the clock signals to a certain limit for the fine deskewing scheme. By generating various clock phases, the CDB can also be potentially useful in high speed debugging and testing where the clock duty cycle can be adjusted accordingly. Various positive and negative duty cycle values can be generated based on the phase resolution and the number of clock phases being “hot swapped”. For a 500ps duty cycle, the following values can be achieved for both the positive and negative duty cycle: 224ps, 316ps, 408ps, 592ps, 684ps, and 776ps.

As the CMOS technology continues to scale into the deep sub-micron regime, the demand for higher frequencies and higher levels of integration poses a significant challenge for the clock generation and distribution design of microprocessors. Hence, skew optimization schemes are necessary to limit clock inaccuracies to a small fraction of the clock period. In this thesis, a crude deskew buffer (CDB) is designed to facilitate an adaptive deskewing scheme that reduces the clock skew in an ASIC clock network under manufacturing process, supply voltage, and temperature (PVT)variations. The crude deskew buffer adopts a DLL structure and functions on a 1GHz nominal clock frequency with an operating frequency range of 800MHz to 1.2GHz. An approximate 91.6ps phase resolution is achieved for all simulation conditions including various process corners and temperature variation. When the crude deskew buffer is applied to seven ASIC clock networks with each under various PVT variations, a maximum of 67.1% reduction in absolute maximum clock skew has been achieved. Furthermore, the maximum phase difference between all the clock signals in the seven networks have been reduced from 957.1ps to 311.9ps, a reduction of 67.4%. Overall, the CDB serves two important purposes in the proposed deskewing methodology: reducing the absolute maximum clock skew and synchronizes all the clock signals to a certain limit for the fine deskewing scheme. By generating various clock phases, the CDB can also be potentially useful in high speed debugging and testing where the clock duty cycle can be adjusted accordingly. Various positive and negative duty cycle values can be generated based on the phase resolution and the number of clock phases being “hot swapped”. For a 500ps duty cycle, the following values can be achieved for both the positive and negative duty cycle: 224ps, 316ps, 408ps, 592ps, 684ps, and 776ps.

Simultaneous multithreading (SMT) processors can issue multiple instructions from distinct processes or threads in the same cycle. This technique effectively increases the overall throughput by keeping the pipeline resources more occupied at the potential expense of reducing single thread performance due to resource sharing. In the software domain, an increasing number of Dynamically Linked Libraries (DLL) are used by applications and operating systems, providing better flexibility and modularity, and enabling code sharing. It is observed that a significant amount of execution time in software today is spent in executing standard DLL instructions, that are shared among multiple threads or processes. However, for an SMT processor with a virtually-indexed based cache implementation, existing instruction fetching mechanisms can induce unnecessary false cache misses caused by the DLL-based instructions, which were intended to be shared. This problem is more conspicuous when multiple independent threads are executing concurrently in an SMT processor. This work investigates an often-neglected form of contention between running threads in the I-TLB and I-cache caused by DLLs. To address these shortcomings, we propose a system level technique involving a light-weight modification in the microarchitecture and the OS. By exploiting the nature of the DLLs in our new architecture, we are able to reinstate physical sharing of the DLLs in an SMT machine. Using Microsoft Windows based applications, our simulation results show that the optimized instruction fetching mechanism can reduce the number of DLL misses up to 5.5 times and improve the instruction cache hit rates by up to 62%, resulting in upto 30% DLL IPC improvements and upto 15% overall IPC improvements.

Effiziente Prozesse sind Voraussetzung für die Wettbewerbsfähigkeit von Unternehmen. In den Ingenieurwissenschaften stellt dies eine strukturierte, zügige und gut dokumentierte Arbeit dar. Der folgende Artikel zeigt Möglichkeiten zur Effizienzsteigerung bei der Nutzung von Mathcad® durch den Einsatz von DLLs. Diese können mit MACCONEX automatisch aus dem Mathcad®- Arbeitsblatt erzeugt werden.

Mathcad gilt in den unterschiedlichsten Bereichen, z.B. in den Ingenieurwissenschaften, der Mathematik, der Physik, der Biologie oder sogar der Qualitätssicherung als hervorragendes Werkzeug zur übersichtlichen Darstellung komplexer Berechnungen. Sollten die enthaltenen Funktionalitäten nicht mehr ausreichen, besteht die Möglichkeit, Mathcad mit Hilfe von User-DLLs zu erweitern. Diese Erweiterung kann perfekt als Schnittstelle zwischen Mathcad und anderen Softwarepaketen genutzt werden. Die von der inuTech GmbH entwickelte Klassenbibliothek Diffpack zur Simulation und numerischen Lösung von Differentialgleichungen aus den verschiedensten Bereichen eignet sich hervorragend, erforderliche Funktionalitäten für Mathcad zu implementieren. Mathcad kann somit zur Parametrisierung, für Berechnungen und zur Darstellung der Ergebnisse verwendet werden, während Diffpack die Lösung der partiellen Differentialgleichung, z.B. mittels FEM, übernimmt.

Technological advancements in video technology have placed stringent requirements on video analog front ends (AFEs) to deliver high resolutions crisp images while consuming low power to deliver optimal performance. One of the vital parts of an AFE is a delay locked loop (DLL). The DLL is a first order system that aligns  a delayed signal with respect to a reference signal while working in a feedback manner. DLLs find their applications in many electronic devices that deal with clocks in their operation. They are used to improve timing margins and clock delays in microprocessors, memory elements and other such applications. The vital function of a DLL is to delay the input clock (one period delay), by passing it through delay line and aligning the input clock and the delayed clock of the DLL through phase detector. Once this is done multiple phases canbe derived from various stages of the delay line with each providing a stable clock signal that is a delayed version of the input clock. Due to the increasing clock speeds this task of deriving multiple phases has become quite cumbersome. The task may become complicated due to noise generated from switching activity in digital circuits thus resulting in jitter at DLL output. As the design of analog circuits becomes quite exigent especially below the 100 nm mark, the goal hereis to design an all digital DLL to take advantage of the 65 nm process and a simplified design cycle. The aim of this thesis is to implement an all digital delay locked loop with an input frequency range of 60 MHz to 300 MHz with a worst case jitter of 66 ps.The DLL provides 32 uniformly spaced phases between input and output clocks.The DLL operation is divided in to two stages. In the first step the first delayline quantizes input clock period with the help of a binary time to digital converter.Based on this quantization information second delay line introduces actual delay between input and output clocks with 32 intermediate phases in between.The entire process takes up to 9 clock cycles until a lock state is achieved. These 32 phases provide a greater phase resolution enhancing the sync processing characteristics of the video AFE thus improving the one screen display characteristics.

Time-to-digital converters (TDC) are widely used in light-detection-and-ranging (LIDAR) systems to measure the time-of-flight. Conventional TDCs are sensitivity to process, voltage, and temperature (PVT) variations. Recent work utilizing the stochastic delay-line TDC architecture has demonstrated excellent robustness against PVT variations. But important issues affecting the linearity of a stochastic delay-line TDC has yet to be recognized and addressed.This thesis rigorously analyzes the problem of linearity of a stochastic delay-line TDC and formulates an intuitive theory to predict the linearity performance. Apolarvisualization of the phase distribution of a delay line is proposed to aid the analysis. Based on the results of this study, this thesis proposes a stochastic delay-line TDC employing a delay-locked loop (DLL) to guarantee linearity over PVT variations and to reduce the number of redundant bits. The proposed TDC is implemented in a 0.18 µm CMOS process to validate the linearity theory and the proposed solution. The 8-bit TDC samples at 60 MHz and demonstrates a linear-number-of-bit of 6.36 with only 2-bit redundancy. Consuming 25 mW from a 1.8 V supply, the TDC yields a figure-of-merit of 5.04 pJ/conversion-step. With the DLL turned off, the integral nonlinearity (INL) degrades by about a factor of two, verifying the effectiveness of the proposed solution. The TDC is measured at different temperatures and supply voltages to demonstrate robustness against PVT variations. The measurement results show excellent agreement with the behavioral simulations.

Mathcad gilt in den unterschiedlichsten Bereichen, z.B. in den Ingenieurwissenschaften, der Mathematik, der Physik, der Biologie oder sogar der Qualitätssicherung als hervorragendes Werkzeug zur übersichtlichen Darstellung komplexer Berechnungen. Sollten die enthaltenen Funktionalitäten nicht mehr ausreichen, besteht die Möglichkeit, Mathcad mit Hilfe von User-DLLs zu erweitern. Diese Erweiterung kann perfekt als Schnittstelle zwischen Mathcad und anderen Softwarepaketen genutzt werden. Die von der inuTech GmbH entwickelte Klassenbibliothek Diffpack zur Simulation und numerischen Lösung von Differentialgleichungen aus den verschiedensten Bereichen eignet sich hervorragend, erforderliche Funktionalitäten für Mathcad zu implementieren. Mathcad kann somit zur Parametrisierung, für Berechnungen und zur Darstellung der Ergebnisse verwendet werden, während Diffpack die Lösung der partiellen Differentialgleichung, z.B. mittels FEM, übernimmt.

Ever since we were children the phrase "In case of an emergency, walk, DON'T run, to the nearest exit" has been drilled into our heads. How to evacuate a large number of people from a given area as quickly and safely as possible has been a question of great importance since the first congregation of man; a question that has yet to be optimally answered. There have been many attempts at finding an answer and many more yet to be made. In light of recent world events, 9/11 for instance, the need for a better answer is apparent. While finding a solution to this problem is the end objective, the goal of this thesis is to develop an application or tool that will aid in the search of an answer to this problem. There are several aspects of traditional evacuation plans that make them inherently suboptimal. First among these is that they are static by nature. When a building is designed, there is some care taken in analyzing its floor plan and finding an optimal evacuation route for everyone. These plans are made under several assumptions and with the obvious constant that they cannot be modified during the actual emergency. Yes, it is possible for such a plan to actually end up being the optimal plan during any given evacuation, but the likelihood of this being the case is most definitely less then 100%. There are many reasons for this. The most obvious is this: the situation that the plan is trying to solve is a very dynamic one. People will not be where they should be or in the quantities that the static plan was prepared for. Many of them will probably not know what they should do in an emergency and so most likely will follow any large group of people, like lemmings. Finally, most situations that require the evacuation of a building or area occur because all or part of the building has become, or is becoming, unsafe. It is impossible for a static evacuation plan to take into account the way a fire or poisonous gas is spreading, or the state of the structural stability of the building. What is needed during a crisis is an artificially intelligent and dynamic evacuation system that is capable of (1) analyzing the state of the building and its occupants, (2) coming up with a plan to get everyone out as fast as possible, and (3) directing all occupants along the best exit routes. Furthermore, the system should be able to modify its plan as the evacuation progresses. This application is intended to provide researchers in this area the means to quickly and accurately simulate different evacuation theories and ideas. That being the case, it will have powerful graphical capabilities, thus allowing the researchers to easily see the real-time results of their work. It will be able to use diverse modeling techniques in order to handle the many different ways of approaching this problem. It will provide a simple way for equations and mathematical models to be entered which can affect the behavior of most aspects of the world being simulated. This work is in conjunction with, and closely tied to, Dr Pushkin Kachroo's research on this same topic. The application is designed so that future developers can quickly add to and modify its design to meet their specifications. It is not the goal of this work to provide an application that directly solves the optimal evacuation problem, or one that inherently simulates everything perfectly. It is the job of the researchers using this application to define the specific physics equations and models for each component of the simulation. This application provides an easy way to add these definitions into the simulation calculations. In brief, this Escape Simulator is a client server application. All of the graphics and human interaction are handled client side using Win32 and Direct3D. The actual simulation world calculations are handled server side, and both the client and server communicate via DirectPlay. The algorithm being used to model the objects and world by the server will be completely configurable. In fact, everything in the world, including the world physics, will be completely modifiable. Though the researchers will need to write the necessary pluggins that to define the actual models and algorithms used by the agents, objects, and world, ultimately this will give them much more power and flexibility. It will also allow for third parties to develop libraries of commonly used algorithms and resources that the researchers can use. This research was supported in part from the National Science Foundation through grant no. CMS-0428196 with Dr. S. C. Liu as the Program Director. This support is gratefully acknowledged. Any opinion, findings, and conclusions or recommendations expressed in this study are those of the writer and do not necessarily reflect the views of the National Science Foundation. / Master of Science