There is a compelling need to explore different material options as well as device structures to facilitate smooth transistor scaling for higher speed, higher density and lower power. The enormous potential of nanoelectronics, and nanotechnology in general, offers us the possibility of designing devices with added functionality. However, at the same time, the new materials come with their own challenges that need to be overcome. In this work, we have addressed some of these challenges in the context of quasi-2D Silicon, III-V semiconductor and graphene. Bulk Si is the most widely used semiconductor with an indirect bandgap of about 1.1 eV. However, when Si is thinned down to sub-10nm regime, the quasi-2D nature of the system changes the electronic properties of the material significantly due to the strong geometrical confinement. Using a tight-binding study, we show that in addition to the increase in bandgap due to quantization, it is possible to transform the original in direct bandgap to a direct one. The effective masses at different valleys are also shown to vary uniquely in an anisotropic way. This ultra-thin Si, when used as a channel in a double gate MOSFET structure, creates so called “volume in version” which is extensively investigated in this work. It has been found that the both the quantum confinement as well as the gating effect play a significant role in determining the spatial distribution of the charge, which in turn has an important role in the characteristics of transistor. Compound III-V semiconductors, like Inx Ga1-xAs, provide low effective mass and low density of states. This, when coupled with strong confinement in a nanowire channel transistor, leads to the “Ultimate Quantum Capacitance Limit” (UQCL) regime of operation, where only the lowest subband is occupied. In this regime, the channel capacitance is much smaller than the oxide capacitance and hence dominates in the total gate capacitance. It is found that the gate capacitance change qualitatively in the UQCL regime, allowing multi-peak, non-monotonic capacitance-voltage characteristics. It is also shown that in an ideal condition, UQCL provides improved current saturation, on-off ratio and energy-delay product, but a degraded intrinsic gate delay. UQCL shows better immunity towards series resistance effect due to increased channel resistance, but is more prone to interfacial traps. A careful design can provide a better on-off ratio at a given gate delay in UQCL compared to conventional MOSFET scenario. To achieve the full advantages of both FinFET and HEMT in III-V domain, a hybrid structure, called “HFinFET” is proposed which provides excellent on performance like HEMT with good gate control like FinFET. During on state, the carriers in the channel are provided using a delta-doped layer(like HEMT) from the top of a fin-like non-planar channel, and during off state, the gates along the side of the fin(like FinFET) help to pull-off the carriers from the channel. Using an effective mass based coupled Poisson-Schrodinger simulation, the proposed structure is found to outperform the state of the art planar and non-planar MOSFETs. By careful optimization of the gate to source-drain underlap, it is shown that the design window of the device can be increased to meet ITRS projections at similar gate length. In addition, the performance degradation of HFinFET in presence of interface traps has been found to be significantly mitigated by tuning the underlap parameter. Graphene is a popular 2D hexagonal carbon crystal with extraordinary electronic, mechani-cal and chemical properties. However, the zero band gap of grapheme has limited its application in digital electronics. One could create a bandgap in grapheme by making quasi-1D strips, called nanoribbon. However, the bandgap of these nanoribbons depends on the the type of the edge, depending on which, one can obtain either semiconducting or metallic nanoribbon. It has been shown that by the application of an external transverse field along the sides of a nanoribbon, one could not only modulate the magnitude of the bandgap, but also change it from direct to indirect. This could open up interesting possibilities for novel electronic and optoelectronic applications. The asymmetric potential distribution inside the nanoribbon is found to result in such direct to indirect bandgap transition. The corresponding carrier masses are also found to be modulated by the external field, following a transition from a“slow”electron to a“fast” electron and vice-versa. Experimentally, it is difficult to control the bandgap in nanoribbons as precise edge control at nanometer scale is nontrivial. One could also open a bandgap in a bilayer graphene, by the application of vertical electric field, which has raised a lot of interest for digital applications. Using a self-consistent tight binding theory, it is found that, inspite of this bandgap opening, the intrinsic bias dependent electronic structure and the screening effect limit the subthreshold slope of a metal source drain bilayer grapheme transistor at a relatively higher value-much above the Boltzmann limit. This in turn reduces the on-off ratio of the transistor significantly. To overcome this poor on-off ratio problem, a semiconductor source-drain structure has been proposed, where the minority carrier injection from the drain is largely switched off due to the bandgap of the drain. Using a self-consistent Non-Equilibrium Green’s Function(NEGF) approach, the proposed device is found to be extremely promising providing unipolar grapheme devices with large on-off ratio, improved subthreshold slope and better current saturation. At high drain bias, the transport properties of grapheme is extremely intriguing with a number of nontrivial effects. Optical phonons in monolayer grapheme couple with carriers in a much stronger way as compared to a bilayer due to selection rules. However, it is difficult to experimentally probe this through transport measurements in substrate supported grapheme as the surface polar phonons with typical low activation energy dominates the total scattering. However, at large drain field, the carriers obtain sufficient energy to interact with the optical phonons, and create so called ‘hot phonons’ which we have experimentally found to result in a negative differential conductance(NDC). The magnitude of this NDC is found to be much stronger in monolayer than in bilayer, which agrees with theoretical calculations. This NDC has also been shown to be compensated by extra minority carrier injection from drain at large bias resulting in an excellent current saturation through a fundamentally different mechanism as compared to velocity saturation. A transport model has been proposed based on the theory, and the experimental observations are found to be in agreement with the model.

No description available.

Résumé: Aujourd’hui plusieurs obstacles technologiques et limitations physiques s’opposent à la poursuite de la miniaturisation de la technologie CMOS : courants de fuite, effet de canal court, effet de porteurs chauds et fiabilité des oxydes de grille. Le transistor à un électron (SET) fait partie des composants émergents candidats pour remplacer les transistors CMOS ou pour constituer une technologie complémentaire à celle-ci. Ce travail de thèse traite de l’amélioration des caractéristiques électriques du transistor à un électron en optimisant ses jonctions tunnel. Cette optimisation commence tout d’abord par une étude des modes de conduction à travers la jonction tunnel. Elle se conclut par le développement d’une jonction tunnel optimisée basée sur un empilement de matériaux diélectriques (principalement Al[indice inférieur 2]O[indice inférieur 3], H[florin]O[indice inférieur 2] et TiO[indice inférieur 2]) ayant des propriétés différentes en termes de hauteurs de barrières et de permittivités relatives. Ce manuscrit présente, la formulation des besoins du SET et de ses jonctions tunnel, le développement d’outils de simulation appropriés - basés sur les Matrices de transmission - pour la simulation du courant des jonctions tunnel du SET, l’identification des stratégies d’optimisation de ces dernières, grâce aux simulations et finalement l’étude expérimentale et l’intégration technologique des jonctions tunnel optimisées dans le procédé de fabrication de SET métallique en utilisant la technique de dépôt par couches atomiques (ALD). Ces travaux nous ont permis de prouver l’intérêt majeur de l’ingénierie des jonctions tunnel du SET pour accroitre son courant à l’état passant, réduire son courant de fuite et étendre son fonctionnement à des températures plus élevées. / Abstract: Today, several technological barriers and physical limitations arise against the miniaturization of the CMOS: leakage current, short channel effects, hot carrier effect and the reliability of the gate oxide. The single electron transistor (SET) is one of the emerging components most capable of replacing CMOS technology or provide it with complementary technology. The work of this thesis deals with the improvement of the electrical characteristics of the single electron transistor by optimizing its tunnel junctions. This optimization initially starts with a study of conduction modes through the tunnel junction. It concludes with the development of an optimized tunnel junction based on a stack of dielectric materials (mainly Al[subscript 2]O[subscript 3], H[florin]O[subscript 2] and TiO[subscript 2]), having different properties in terms of barrier heights and relative permittivities. This document, therefore, presents the theoretical formulation of the SET’s requirements and of its tunnel junctions, the development of appropriate simulation tools - based on the transmission matrix model- for the simulation of the SET tunnel junctions current, the identification of tunnel junctions optimization strategies from the simulations results and finally the experimental study and technological integration of the optimized tunnel junctions into the metallic SET fabrication process using the atomic layer deposition (ALD) technique. This work allowed to démonstrate the significance of SET tunnel junctions engineering in order to increase its operating current while reducing leakage and improving its operation at higher temperatures.

Ce travail de recherche a été principalement motivé par les avantages importants apportés par la technologie UTBB FDSOI aux applications analogiques et RF de faible puissance. L'objectif principal est d'étudier le comportement dynamique du transistor MOSFET du type UTBB FDSOI et de proposer des modèles prédictifs et des recommandations pour la conception de circuits intégrés RF, en mettant un accent particulier sur le régime d'inversion modérée. Après une brève analyse des progrès réalisés au niveau des architectures du transistor MOSFET, un état de l’art de la modélisation du transistor MOSFET UTBB FDSOI est établi. Les principaux effets physiques impliqués dans le transistor à double grille avec une épaisseur du film de 7 nm sont passés en revue, en particulier l’impact de la grille arrière, à l’aide de mesures et de simulations TCAD. La caractéristique gm/ID en basse fréquence et la caractéristique ym/ID proposée pour la haute fréquence sont étudiées et utilisées dans une conception analogique efficace. Enfin, le modèle NQS haute fréquence proposé reproduit les mesures dans toutes les conditions de polarisation y compris l’inversion modérée jusqu’à 110 GHz. / This research work has been motivated primarily by the significant advantages brought about by the UTBB FDSOI technology to the Low power Analog and RF applications. The main goal is to study the dynamic behavior of the UTBB FDSOI MOSFET in light of the recent technology advances and to propose predictive models and useful recommendations for RF IC design with particular emphasis on Moderate Inversion regime. After a brief review of progress in MOSFET architectures introduced in the semiconductor industry, a state-of-the-art UTBB FDSOI MOSFET modeling status is compiled. The main physical effects involved in the double gate transistor with a 7 nm thick film are reviewed, particularly the back gate impact, using measurements and TCAD. For better insight into the Weak Inversion and Moderate Inversion operations, both the low frequency gm/ID FoM and the proposed high frequency ym/ID FoM are studied and also used in an efficient first-cut analog design. Finally, a high frequency NQS model is developed and compared to DC and S-parameters measurements. The results show excellent agreement across all modes of operation including very low bias conditions and up to 110 GHz.

Dans les années à venir, l’industrie de la microélectronique doit développer de nouvelles filières technologiques qui pourront devenir des successeurs ou des compléments de la technologie CMOS ultime. Parmi ces technologies émergentes relevant du domaine ‘‘Beyond CMOS’’, ce travail de recherche porte sur les transistors mono-électroniques (SET) dont le fonctionnement est basé sur la quantification de la charge électrique, le transport quantique et la répulsion Coulombienne. Les SETs doivent être étudiés à trois niveaux : composants, circuits et système. Ces nouveaux composants, utilisent à leur profit le phénomène dit de blocage de Coulomb permettant le transit des électrons de manière séquentielle, afin de contrôler très précisément le courant véhiculé. Ainsi, le caractère granulaire de la charge électrique dans le transport des électrons par effet tunnel, permet d’envisager la réalisation de transistors et de cellules mémoires à haute densité d’intégration, basse consommation. L’objectif principal de ce travail de thèse est d’explorer et d’évaluer le potentiel des transistors mono-électroniques double-grille métalliques (DG-SETs) pour les circuits logiques numériques. De ce fait, les travaux de recherches proposés sont divisés en trois parties : i) le développement des outils de simulation et tout particulièrement un modèle analytique de DG-SET ; ii) la conception de circuits numériques à base de DGSETs dans une approche ‘‘cellules standards’’ ; et iii) l’exploration d’architectures logiques versatiles à base de DG-SETs en exploitant la double-grille du dispositif. Un modèle analytique pour les DG-SETs métalliques fonctionnant à température ambiante et au-delà est présenté. Ce modèle est basé sur des paramètres physiques et géométriques et implémenté en langage Verilog-A. Il est utilisable pour la conception de circuits analogiques ou numériques hybrides SET-CMOS. A l’aide de cet outil, nous avons conçu, simulé et évalué les performances de circuits logiques à base de DG-SETs afin de mettre en avant leur utilisation dans les futurs circuits ULSI. Une bibliothèque de cellules logiques, à base de DG-SETs, fonctionnant à haute température est présentée. Des résultats remarquables ont été atteints notamment en terme de consommation d’énergie. De plus, des architectures logiques telles que les blocs élémentaires pour le calcul (ALU, SRAM, etc.) ont été conçues entièrement à base de DG-SETs. La flexibilité offerte par la seconde grille du DG-SET a permis de concevoir une nouvelle famille de circuits logiques flexibles à base de portes de transmission. Une réduction du nombre de transistors par fonction et de consommation a été atteinte. Enfin, des analyses Monte-Carlo sont abordées afin de déterminer la robustesse des circuits logiques conçus à l'égard des dispersions technologiques. / In this work, we have presented a physics-based analytical SET model for hybrid SET-CMOS circuit simulations. A realistic SET modeling approach has been used to provide a compact SET model that takes several conduction mechanisms into account and closely matches experimental SET characteristics. The model is implemented in Verilog-A language, and can provide suitable environment to simulate hybrid SET-CMOS architectures. We have presented logic circuit design technique based on double gate metallic SET at room temperature. We have also shown the flexibility that the second gate can bring in order to configure the SET into P-type and N-type. Given that the same device is utilized, the circuit design approach exhibits regularity of the logic gate that simplifies the design process and leads to reduce the increasing process variations. Afterwards, we have addressed a new Boolean logic family based on DG-SET. An evaluation of the performance metrics have been carried out to quantify SET technology at the circuit level and compared to advanced CMOS technology nodes. SET-based static memory was achieved and performances metrics have been discussed. At the architectural level, we have investigated both full DG-SET based arithmetic logic blocks (FA and ALU) and programmable logic circuits to emphasize the low power aspect of the technology. The extra power reduction of SETs based logic gates compared to the CMOS makes this technology much attractive for ultra-low power embedded applications. In this way, architectures based on SETs may offer a new computational paradigm with low power consumption and low voltage operation. We have also addressed a flexible logic design methodology based on DG-SET transmission gates. Unlike conventional design approach, the XOR / XNOR behavior can be efficiently implemented with only 4 transistors. Moreover, this approach allows obtaining reconfigurable XOR / XNOR gates by swapping the cell biasing. Given that the same device is utilized, the structure can be physically implemented and established in a regular manner. Finally, complex logic gates based on DG-SET transmission gates offer an improvement in terms of transistor device count and power consumption compared to standard complementary SETs implementations.Process variations are introduced through our model enabling then a statistical study to better estimate the SET-based circuit performances and robustness. SET features low power but limited operating frequency, i.e. the parasitics linked to the interconnects reduce the circuit operating frequency as the SET Ion current is limited to the nA range. In term of perspectives: i) detailed studying the impact on SET-based logic cells of process variation and random back ground charge ii) considering multi-level computational model and their associate architectures iii) investigating new computation paradigms (neuro-inspired architectures, quantum cellular automata) should be considered for future works.

Aujourd’hui plusieurs obstacles technologiques et limitations physiques s’opposent à la poursuite de la miniaturisation de la technologie CMOS : courants de fuite, effet de canal court, effet de porteurs chauds et fiabilité des oxydes de grille. Le transistor à un électron (SET) fait partie des composants émergents candidats pour remplacer les transistors CMOS ou pour constituer une technologie complémentaire à celle-ci. Ce travail de thèse traite de l’amélioration des caractéristiques électriques du transistor à un électron en optimisant ses jonctions tunnel. Cette optimisation commence tout d’abord par une étude des modes de conduction à travers la jonction tunnel. Elle se conclut par le développement d’une jonction tunnel optimisée basée sur un empilement de matériaux diélectriques (principalement Al2O3, HfO2 et TiO2) ayant des propriétés différentes en termes de hauteurs de barrières et de permittivités relatives. Ce manuscrit présente, la formulation des besoins du SET et de ses jonctions tunnel, le développement d’outils de simulation appropriés - basés sur les matrices de transmission - pour la simulation du courant des jonctions tunnel du SET, l’identification des stratégies d’optimisation de ces dernières, grâce aux simulations et finalement l’étude expérimentale et l’intégration technologique des jonctions tunnel optimisées dans le procédé de fabrication de SET métallique en utilisant la technique de dépôt par couches atomiques (ALD). Ces travaux nous ont permis de prouver l’intérêt majeur de l’ingénierie des jonctions tunnel du SET pour accroitre son courant à l’état passant, réduire son courant de fuite et étendre son fonctionnement à des températures plus élevées. / Today, several technological barriers and physical limitations arise against the miniaturization of the CMOS: leakage current, short channel effects, hot carrier effect and the reliability of the gate oxide. The single electron transistor (SET) is one of the emerging components most capable of replacing CMOS technology or provide it with complementary technology. The work of this thesis deals with the improvement of the electrical characteristics of the single electron transistor by optimizing its tunnel junctions. This optimization initially starts with a study of conduction modes through the tunnel junction. It concludes with the development of an optimized tunnel junction based on a stack of dielectric materials (mainly Al2O3, HfO2 and TiO2), having different properties in terms of barrier heights and relative permittivities. This document, therefore, presents the theoretical formulation of the SET’s requirements and of its tunnel junctions, the development of appropriate simulation tools - based on the transmission matrix model- for the simulation of the SET tunnel junctions current, the identification of tunnel junctions optimization strategies from the simulations results and finally the experimental study and technological integration of the optimized tunnel junctions into the metallic SET fabrication process using the atomic layer deposition (ALD) technique. This work allowed to demonstrate the significance of SET tunnel junctions engineering in order to increase its operating current while reducing leakage and improving its operation at higher temperatures.

No description available.