Cette thèse s'intéresse à la définition de mécanismes, aussi bien au niveau logiciel que matériel, facilitant la gestion des systèmes-sur-puce hétérogènes et dynamiquement reconfigurable (HRSoC). L'hétérogénéité de ses architectures se manifeste par la présence à la fois de processeurs de calcul généralistes et de modules matériels reconfigurables. L'objectif de cette thèse est de permettre à un développeur d'application de s'abstraire de cette hétérogénéité en ce qui concerne l'allocation des tâches sur les différentes unités de calcul disponibles. Cette abstraction passe par une première phase d'homogénéisation des interfaces utilisateurs (API) et la définition d'un modèle de thread matériel, au même titre qu'il existe des threads logiciels. Cette homogénéisation se poursuit ensuite dans la gestion de ces threads matériels. Nous avons implémenté des services au niveau du système d'exploitation permettant de sauvegarder, préempter, et restaurer le contexte d'un thread matériel. Des outils de conception ont également été développés afin de surpasser le problème de la relocation d'un thread matériel au sein d'un FPGA. Enfin, la dernière étape a été d'étendre l'accès aux services offerts par tous les systèmes d'exploitation distribués au sein de la plateforme à tous les threads s'exécutant sur celle-ci, indépendamment de leur localisation. Ceci a été réalisé via une implémentation originale de l'API MRAPI. Avec ces trois étapes, nous avons apporté une base solide afin, dans le futur, de proposer au développeur un flot de conception dédié aux architectures HRSoC lui permettant de procéder à une exploration architecturale précise de son système. Finalement, afin d'éprouver le fonctionnement de ces mécanismes, nous avons réalisé une plateforme de démonstration sur FPGA Virtex 5 mettant en scène une application de suivi de cibles dynamique. / This thesis aims to define software and hardware mechanisms helping in the management the Heterogeneous and dynamically Reconfigurable Systems-on-Chip (HRSoC). The heterogeneity is due to the presence of general processing units and reconfigurable IPs. Our objective is to provide to an application developer an abstracted view of this heterogeneity, regarding the task mapping on the available processing elements. First, we homogenize the user interface defining a hardware thread model. Then, we pursue with the homogenization of the hardware threads management. We implemented OS services permitting to save and restore a hardware thread context. Conception tools have also been developed in order to overcome the relocation issue. The last step consisted in extending the access to the distributed OS services to every thread running on the platform. This access is provided independently from the thread location and is is realized implementing the MRAPI API. With these three steps, we build a solid basis to, in future work, provide to the developer, a conception flow dedicated to HRSoC allowing to perform precise architectural space explorations. Finally, to validate these mechanisms, we realize a demonstration platform on a Virtex 5 FPGA running a dynamic tracking application.

Malgré des avantages certains en terme d'adaptabilité et en gain de surface, la reconfiguration dynamique sur FPGA a du mal à être utilisée dans l'industrie. Le manque de moyens et de méthodes d'évaluation d'une telle architecture en est la cause majeure. Pire, aucun outil officiel ne permet aux développeurs de déterminer facilement un ordonnancement de la reconfiguration adapté pour une architecture donnée. Cette thèse s'inscrit dans ce contexte et propose une méthodologie de modélisation SystemC d'architectures reconfigurables dynamiquement. Cet outil d'aide à la conception permet de faire gagner un temps considérable lors de la phase de conception en fournissant une première estimation des performances et des ressources nécessaires au développement de l'architecture. Il permet également le développement et la validation de scénarios d'ordonnancement de la reconfiguration, tout en respectant les contraintes temps réel liées à l'application. Afin de valider notre modèle sur une application réelle, des IP de transcodage vidéo ont été développées et seront détaillées. Cette application consiste en la réalisation d'un transcodeur H.264/MPEG-2, rendu auto-adaptable grâce à l'utilisation de la reconfiguration dynamique. Ces travaux ont été menés dans le cadre du projet ARDMAHN financé par l'Agence Nationale de la Recherche portant la référence ANR-09-SEGI-001 / Despite clear benefits in terms of fexibility and surface efficiency, dynamic reconfiguration of FPGAs is still finding it hard to break through into massive industrial project. One of the main reasons is the lack of means and methods for evaluation of reconfigurable architectures. Worse, main FPGA vendors do not provide official tools allowing developers to easily determine an optimal scheduling reconfiguration for a specific architecture. Within this framework, the proposed research work described in this thesis proposes a methodology for modeling dynamically reconfigurable architectures based on SystemC. The proposed methodology allows designers to save significant time during the design phases of an application specific reconfigurable architecture by providing an initial estimate of performance and resources needed for its development. It also allows development and validation of scheduling reconfiguration scenarios, while respecting real-time constraints associated with the given application. To validate our methodology on a real application, video transcoding IP have been developed and tested. This application consists in the realization of a H.264/MPEG-2 transcoder made self-adaptable through the use of dynamic reconfiguration. This work was conducted as a part of the ARDMAHN project sponsored by the National Research Agency (Agence Nationale de Recheche) with the reference number ANR-09-SEGI-001

Les travaux présentés dans cette thèse sont effectuées dans le cadre des Systèmes sur puce (SoC, Systemon Chip) et la conception de systèmes embarqués en temps réel, notamment dédiés au domaine de la reconfiguration dynamique, liés à ces systèmes complexes. Dans ce travail, nous présentons un nouveau flot de conception basé sur l'Ingénierie Dirigée par les Modèles (IDM/MDE) et le profilMARTE pour la conception conjointe du SoC, la spécification et la mise en oeuvre de ces systèmes sur puce reconfigurables, afin d'élever les niveaux d'abstraction et de réduire la complexité du système. La première contribution relative à cette thèse est l'identification des parties de systèmes sur puce reconfigurable dynamiquement qui peuvent être modélisées au niveau d'abstraction élevé. Cette thèse adapte une approche dirigée par l'application et cible les modèles d'application de haut niveau pour être traités comme des régions dynamiques des SoCs reconfigurables. Nous proposons aussi des modèles de contrôle générique pour la gestion de ces régions au cours de l'exécution en temps réel. Bien que cette sémantique puisse être introduite à différents niveaux d'abstraction d'un environnent pour la conception conjointe du SoC, nous insistons tout particulièrement sur sa fusion au niveau du déploiement, qui relie la propriété intellectuelle avec les éléments modélisés à haut niveau de conception. En outre, ces concepts ont été intégrés dans le méta-modèleMARTE et le profil correspondant afin de fournir une extension adéquate pour exprimer les caractéristiques de reconfiguration à la modélisation de haut niveau. La seconde contribution est la proposition d'un méta-modèle intermédiaire, qui isole les concepts présents au niveau transfert de registre (RTL-Register Transfer Level). Ce méta-modèle intègre les concepts chargés de l'exécution matérielle des applications modélisées, tout en enrichissant la sémantique de contrôle, provoquant la création d'un accélérateur matériel reconfigurable dynamiquement avec plusieurs implémentations disponibles. Enfin, en utilisant les transformations de modèlesMDE et les principes correspondants, nous sommes en mesure de générer des codeHDL équivalents à différentes implémentations de l'accélérateur reconfigurable ainsi que différents codes source en langage C/C++ liés au contrôleur de reconfiguration, qui est finalement responsable de la commutation entre les différentes mplémentations. Enfin, notre flot de conception a été vérifié avec succès dans une étude de cas liée à un système anti-radar de détection de collision. Une composante clé intégrante de ce système a été modélisée en utilisant les spécifications MARTE étendu et le code généré a été utilisé dans la conception et la mise en oeuvre d'un SoC sur un FPGA reconfigurable dynamiquement.

<p>During the last years the need for real-time database services has increased due to the growing number of data-intensive applications needing to enforce real-time constraints. The COMponent-based Embedded real-Time database (COMET) is a real-time database developed to meet these demands. COMET is developed using the AspeCtual COmponent-based Real-time system Development (ACCORD) design method, and consists of a number of components and aspects, which can be composed into a number of different configurations depending on system demands, e.g., Quality of Service (QoS) management can be used in unpredictable environments. </p><p>In embedded systems with requirementson high up-time it may not be possible to temporarily shut down the system for reconfiguration. Instead it is desirable to enable dynamic reconfiguration of the system, exchanging components during run-time. This in turn sets demands on the feedback control of the system to adjust to these new conditions, since a new time variant system has been created. </p><p>This thesis project implements improvements in COMET to create a more stable database suitable for further development. A mechanism for dynamic reconfiguration of COMET is implemented, thus, enabling components and aspects to be swapped during run-time. Adaptive feedback control algorithms are also implemented in order to better adjust to workload variations and database reconfiguration.</p>

Aspect-oriented middleware is a promising technology for the realisation of dynamic reconfiguration in heterogeneous distributed systems. However, like other dynamic reconfiguration approaches, AO-middleware-based reconfiguration requires that the consistency of the system is maintained across reconfigurations. AO-middleware-based reconfiguration is an ongoing research topic and several consistency approaches have been proposed. However, most of these approaches tend to be targeted at specific contexts, whereas for distributed systems it is crucial to cover a wide range of operating conditions. In this paper we propose an approach that offers distributed, dynamic reconfiguration in a consistent manner, and features a flexible framework-based consistency management approach to cover a wide range of operating conditions. We evaluate our approach by investigating the configurability and transparency of our approach and also quantify the performance overheads of the associated consistency mechanisms.

Submitted by Johnny Rodrigues (johnnyrodrigues@ufcg.edu.br) on 2018-08-13T20:41:07Z No. of bitstreams: 1 LUIZ BRUNELLI - TESE PPGEE 2005..pdf: 3761170 bytes, checksum: e05b83824a2a7e6d3aca6ea19daf1396 (MD5) / Made available in DSpace on 2018-08-13T20:41:07Z (GMT). No. of bitstreams: 1 LUIZ BRUNELLI - TESE PPGEE 2005..pdf: 3761170 bytes, checksum: e05b83824a2a7e6d3aca6ea19daf1396 (MD5) Previous issue date: 2005-02 / CNPq / Nesta tese descreve-se uma nova solução para o tratamento da complexidade das interconexões entre os elementos de processamento das redes neuronais artificiais (RNAs). Ela possibilita implementar RNAs em hardware, de tecnologia digital, com um número maior de neurônios do que se faz atualmente. As RNAs têm sido usadas como solução em vários problemas complexos. Em alguns destes problemas faz-se necesário a sua implementação em hardware. Vários s˜ao os compromissos que devem ser satisfeitos durante o projeto e implementa¸c˜ao das RNAs, dentre eles o das interconexões entre os neurônios. Atualmente encontram-se implementações neuronais utilizando circuitos integrados especificamente desenvolvidos para uma dada arquitetura de rede neuronal e também o uso de circuitos integrados configurados pelo usuário. Dentre estes circuitos existem os FPGAs reconfigur´aveis dinamicamente (DR-FPGAs) que podem ter suas características alteradas durante a sua opera¸c˜ao, sem sofrer interrupções em seu funcionamento normal. Estes dispositivos têm sido utilizados na implementação de RNAs. Propõe-se uma solução para o problema das interconexões entre os neurônios artificiais utilizando os DR-FPGAs e uma nova forma de computação: as Figuras de Execução (F.E.). As F.E. permitem teoricamente reduzir o impacto das interconexões através da eliminação do transporte de dados via barramento, além de outras vantagens e desvantagens durante o processamento da computação. As F.E. não parecem estar restritas apenas as aplicações de RNAs. Elas podem ser utilizadas pela computação reconfigurável em problemas massivamente paralelos e/ou que necessitem trocar informações entre os vários elementos de processamento do sistema. / In this thesis a new solution for the treatment of the complexity in the interconnections among the processing elements of the artificial neural networks (ANNs) is described. It enables realize ANNs digital hardware implementation with a larger number of neurons than does nowadays. The ANNs have been used as a solution in various complex problems. Some of these problems require hardware implementation. A lot of constraints must be satisfied during the project flow of the implementations of ANNs, such as the neural interconnections. Nowadays, neural implementations are done using integrated circuits, specifically developed for a given neural network architecture or integrated circuits configured by the user. Among these circuits exist the dynamically reconfigured FPGAs (DR-FPGAs) which can have their characteristics changed during operation without suffering interruptions in their execution. These devices have been usedforANNimplementations. Itpresentsaproposaltosolvethe interconnection problem for artificial neurons using DR-FPGAs in a new computational way: the Execution Patterns1 (EPs). The EPs allow, theoretically, to reduce the influence of interconnections through the removal of data transport via busses, besides other advantages and disadvantages. TheEPsdoesnotseemtoberestrictedonlytoANNapplications. They can be used by reconfigurable computation in massive parallel problems and/or problems that demand information exchange among the various elements in a processing system.

[pt] Ao mesmo tempo em que sistemas de processamento de fluxo de dados devem prover serviços de análise e manipulação de dados ininterruptamente (disponibilidade 24x7), eles comumente também precisam lidar com mudanças em seus ambientes de execução (e.g., alterar a topologia da rede) e nos requisitos que eles devem cumprir (e.g., adição de novas funções de processamento dos fluxos de dados). Por um lado, reconfiguração dinâmica de software (i.e., a capacidade de substituir parte do software em tempo de execução) é uma característica desejável. Por outro lado, sistemas de fluxo de dados podem sofrer com a interrupção e sobrecarga causada pela reconfiguração. Por conta da necessidade de reconfigurar (i.e., evoluir) o sistema ao mesmo tempo em que o sistema não pode ser interrompido (i.e., bloqueado), reconfiguração consistente e não bloqueante é ainda considerada um problema em aberto na literatura. Esta tese apresenta e valida uma abordagem não quiescente para reconfiguração dinâmica de software que preserva a consistência de sistemas de fluxo de dados distribuídos. A abordagem proposta permite que o sistema seja reconfigurado gradual e suavemente, sem precisar interromper o processamento do fluxo de dados ou atingir a quiescência. A avaliação indica que a abordagem proposta realiza reconfiguração distribuída consistentemente e tem um impacto desprezível sobre a diminuição na disponibilidade e no desempenho do sistema. Além disto, a implementação da abordagem proposta teve um desempenho melhor em todos os testes comparativos. / [en] While many data stream systems have to provide continuous (24x7) services with no acceptable downtime, they also have to cope with changes in their execution environments and in the requirements that they must comply (e.g., moving from on-premises architecture to a cloud system, changing the network technology, adding new functionality or modifying existing parts). On one hand, dynamic software reconfiguration (i.e., the capability of evolving on the fly) is a desirable feature. On the other hand, stream systems may suffer from the disruption and overhead caused by the reconfiguration. Due to the necessity of reconfiguring (i.e., evolving) the system whilst the system must not be disrupted (i.e., blocked), consistent and non-disruptive reconfiguration is still considered an open problem. This thesis presents and validates a non-quiescent approach for dynamic software reconfiguration that preserves the consistency of distributed data stream processing systems. Unlike many works that require the system to reach a safe state (e.g., quiescence) before performing a reconfiguration, the proposed approach enables the system to smoothly evolve (i.e., be reconfigured) in a non-disruptive way without reaching quiescence. The evaluation indicates that the proposed approach supports consistent distributed reconfiguration and has negligible impact on availability and performance. Furthermore, the implementation of the proposed approach showed better performance results in all experiments than the quiescent approach and Upstart.

Les domaines de recherche actuels, tels que l'informatique ubiquitaire et l'informatique en nuage (cloud computing), considèrent que ces environnements d’exécution sont en changement continue. Les applications dynamiques, où les composants peuvent être ajoutés et supprimés pendant l'exécution, permettent à un logiciel de s'adapter et de s'ajuster à l'évolution des environnements, et de tenir compte de l’évolution du logiciel. Malheureusement, les applications dynamiques soulèvent des questions de conception et de développement qui n'ont pas encore été pleinement explorées.Dans cette thèse, nous montrons que le dynamisme est une préoccupation transversale qui rompt avec un grand nombre d’hypothèses que les développeurs d’applications classiques sont autorisés à prendre. Le dynamisme affecte profondément la conception et développement de logiciels. S'il n'est pas manipulé correctement, le dynamisme peut « silencieusement » corrompre l'application. De plus, l'écriture d'applications dynamiques est complexe et sujette à erreur. Et compte tenu du niveau de complexité et de l’impact du dynamisme sur le processus du développement, le logiciel ne peut pas devenir dynamique sans (de large) modification et le dynamisme ne peut pas être totalement transparent (bien que beaucoup de celui-ci peut souvent être externalisées ou automatisées).Ce travail a pour but d’offrir à l’architecte logiciel le contrôle sur le niveau, la nature et la granularité du dynamisme qui est nécessaire dans les applications dynamiques. Cela permet aux architectes et aux développeurs de choisir les zones de l'application où les efforts de programmation des composants dynamiques seront investis, en évitant le coût et la complexité de rendre tous les composants dynamiques. L'idée est de permettre aux architectes de déterminer l'équilibre entre les efforts à fournir et le niveau de dynamisme requis pour les besoins de l'application. / Current areas of research, such as ubiquitous and cloud computing, consider execution environments to be in a constant state of change. Dynamic applications—where components can be added, removed and substituted during execution—allow software to adapt and adjust to changing environments, and to accommodate evolving features. Unfortunately, dynamic applications raise design and development issues that have yet to be fully addressed. In this dissertation we show that dynamism is a crosscutting concern that breaks many of the assumptions that developers are otherwise allowed to make in classic applications. Dynamism deeply impacts software design and development. If not handled correctly, dynamism can silently corrupt the application. Furthermore, writing dynamic applications is complex and error-prone, and given the level of complexity and the impact dynamism has on the development process, software cannot become dynamic without (extensive) modification and dynamism cannot be entirely transparent (although much of it may often be externalized or automated). This work focuses on giving the software architect control over the level, the nature and the granularity of dynamism that is required in dynamic applications. This allows architects and developers to choose where the efforts of programming dynamic components are best spent, avoiding the cost and complexity of making all components dynamic. The idea is to allow architects to determine the balance between the efforts spent and the level of dynamism required for the application's needs. At design-time we perform an impact analysis using the architect's requirements for dynamism. This serves to identify components that can be corrupted by dynamism and to—at the architect's disposition—render selected components resilient to dynamism. The application becomes a well-defined mix of dynamic areas, where components are expected to change at runtime, and static areas that are protected from dynamism and where programming is simpler and less restrictive. At runtime, our framework ensures the application remains consistent—even after unexpected dynamic events—by computing and removing potentially corrupt components. The framework attempts to recover quickly from dynamism and to minimize the impact of dynamism on the application. Our work builds on recent Software Engineering and Middleware technologies—namely, OSGi, iPOJO and APAM—that provide basic mechanisms to handle dynamism, such as dependency injection, late-binding, service availability notifications, deployment, lifecycle and dependency management. Our approach, implemented in the Robusta prototype, extends and complements these technologies by providing design and development-time support, and enforcing application execution consistency in the face of dynamism.

Made available in DSpace on 2016-08-17T14:53:27Z (GMT). No. of bitstreams: 1 Marcio Augusto Sekeff.pdf: 1014650 bytes, checksum: 620b3ce1069bc8032552ed7d6cbf8d41 (MD5) Previous issue date: 2007-12-14 / Modern computing environments are characterized by a high degree of dynamism that, along with the heterogeneity of computational devices and communication infrastructure, demand the development of a new range of applications that must be able to self-adapt dynamically and transparently according to changes in its execution environment. A computational grid is an example of a modern environment where it is common to notice a high variation on resource availability, node instability, variations on load distribution, and heterogeneity of computational devices and network technology. Another example is mobile computing, where the great diversity of computational devices, wireless network dynamism, limitations regarding available resources (such as, battery power) and mobility require the software to able to adapt to environmental changes. This paper presents the Adapta framework, a reflective middleware that provides the means to develop self-adaptive distributed applications, separating the business code from the one responsible for adaptation. Adapta also provides a runtime execution environment that monitors computational resources and noticies application components about the occurrence of important events that should trigger reconfiguration actions. Adapta provides a XML based reconfiguration language that defines how the application must adapt in response to environmental changes. Statements of the reconfiguration language can also be applied at runtime, which allows to dynamically change the reconfiguration mechanism itself. / Sistemas computacionais modernos são caracterizados por um alto grau de dinamismo que, junto com a heterogeneidade dos dispositivos computacionais e da infraestrutura de comunicação, requerem o desenvolvimento de um novo grupo de aplicações capazes de se auto-adaptar dinamica e transparentemente de acordo com mudanças em seu ambiente de execução. Um exemplo destes ambientes é o compreendido por grade computacionais, onde é comum observar alta variabilidade na disponibilidade de recursos, instabilidade de nós, variações no balanceamento de carga e heterogeneidade dos dispositivos computacionais e tecnologia de rede. Outro example são os ambientes de computação móvel, nos quais a grande diversidade de dispositivos computacionais, o dinamismo das redes sem fio, as limitações na disponibilidade de recursos (por exemplo, bateria) e a questão da mobilidade exigem a habilidade do software de se adaptar a mudan ças do ambiente. Este trabalho apresenta o arcabouço Adapta, um middleware reflexivo que provê os meios para desenvolver aplicações distribuídas auto-adaptativas, separando as regras de negócio do código responsável pela adaptação. Adapta também consiste em um sistema em execução que monitora recursos computacionais e notifica componentes da aplicações da importância de eventos que devem disparar ações de reconfiguração. O Adapta define uma linguagem de reconfiguração baseada em XML através da qual é possível especificar como a aplicação deve se adaptar em resposta a mudanças ambientais. Sentenças desta linguagem de reconfiguração podem ser aplicadas em tempo de execução, o que permite alterar dinamicamente o próprio mecanismo de reconfiguração.

During the last years the need for real-time database services has increased due to the growing number of data-intensive applications needing to enforce real-time constraints. The COMponent-based Embedded real-Time database (COMET) is a real-time database developed to meet these demands. COMET is developed using the AspeCtual COmponent-based Real-time system Development (ACCORD) design method, and consists of a number of components and aspects, which can be composed into a number of different configurations depending on system demands, e.g., Quality of Service (QoS) management can be used in unpredictable environments. In embedded systems with requirementson high up-time it may not be possible to temporarily shut down the system for reconfiguration. Instead it is desirable to enable dynamic reconfiguration of the system, exchanging components during run-time. This in turn sets demands on the feedback control of the system to adjust to these new conditions, since a new time variant system has been created. This thesis project implements improvements in COMET to create a more stable database suitable for further development. A mechanism for dynamic reconfiguration of COMET is implemented, thus, enabling components and aspects to be swapped during run-time. Adaptive feedback control algorithms are also implemented in order to better adjust to workload variations and database reconfiguration.