As the microelectronic industry moves toward stacking of dies to achieve greater performance and smaller footprint, there are several reliability concerns when assembling the stacked dies on current organic substrates. These concerns include excessive warpage, interconnect cracking, die cracking, and others. Silicon interposers are being developed to assemble the stacked dies, and then the silicon interposers are assembled on organic substrates. Although such an approach could address stacked-die to interposer reliability concerns, there are still reliability concerns between the silicon interposer and the organic substrate. This work examines the use of diced glass panel as an interposer, as glass provides intermediate coefficient of thermal expansion between silicon and organics, good mechanical rigidity, large-area panel processing for low cost, planarity, and better electrical properties. However, glass is brittle and low in thermal conductivity, and there is very little work in existing literature to examine glass as a potential interposer material. Starting with a 150 x 150 mm glass panel with a thickness of 100 µm, this work has built alternating layers of dielectric and copper on both sides of the panel. The panels have gone through typical cleanroom processes such as lithography, electroplating, etc. Upon fabrication, the panels are diced into individual substrates of 25 x 25 mm and a 10 x 10 mm flip chip with a solder bump pitch of 75 um is then reflow attached to the glass substrate followed by underfill dispensing and curing. The warpage of the flip-chip assembly is measured. In parallel to the experiments, numerical models have been developed. These models account for viscoplastic behavior of the solder. The models also mimic material addition and etching through element “birth-and-death” approach. The warpage from the models has been compared against experimental measurements for glass substrates with flip chip assembly. It is seen that the glass substrates provide significantly lower warpage compared to organic substrates, and thus could be a potential candidate for future 3D systems.

One of the main challenges in the electronics manufacturing and packaging development is how to integrate more functions inside the same or even smaller size. To meet the demand for higher integration, the interest toward passive and active component embedding has been increasing during the past few years. One of the main reasons for the growing interest toward embedded active components, in addition to demand for higher packaging density, is the need for better electrical performance of the component assemblies. However, it is little known how embedded IC and passives affect the reliability of IC packaging. Solder joints have been used in the electronic industry as both structural and electrical interconnections between electronic packages and printed circuit boards (PCB). When solder joints are under thermal cyclic loading, mismatch in coefficients of thermal expansion (CTE) between the printed circuit boards and the solder balls creates thermal strains and stresses on the joints, which may finally result in cracking. Consequently, the mechanical interconnection is lost, leading to electrical failures (such as hard/intermittent open, parametric failure), which in turn causes malfunction of the circuit or whole system. When a die is embedded into a substrate, Young's modulus of the die is larger than one of the core of the substrate and the CTEs of the die is smaller than those of the substrate. As a result, mismatch in coefficients of thermal expansions (CTE) between the substrate with the embedded device and the solder balls may increase. In the present study, the stress of chip scale packages (CSP) with an embedded die under thermal cycling conditions is evaluated using the finite element method. The viscoplastic model for solders including matrix dislocation mechanism and grain boundary sliding model developed by Yi et al. (2002) is employed.

To reduce electronics packaging lead time and potentially to reduce manufacturing cost, an innovative packaging process targeting rapid package prototyping (RPP) has been developed. The developed RPP process, which is based on a data-driven chip-first approach, provides electrical functionality as well as form factors for micro-systems packages. The key component of the RPP process is the nano-particle silver (NPS) interconnect. However, NPS has not yet been adequately proven for use in electronics packaging applications. Moreover, its adhesion to electronics packaging materials such as polyimide, benzocyclobutene (BCB), copper, and aluminum is found to be weak. Thus, improving the adhesion strength of NPS will be a key issue for reliable package prototypes with NPS interconnects. In this research, the adhesion of NPS to substrate materials is found to be attributed to particle adhesion and more specifically, van der Waals forces. An adhesion model based on the van der Waals force is suggested in order to predict NPS adhesion strength to packaging materials. A new adhesion test method that is based on a die shear test and a button shear test is developed to validate the NPS adhesion prediction model. The newly developed adhesion test method is generic in nature and can be extended to other thin films' adhesion tests. The NPS adhesion model provides a general and explicit relation between NPS tensile bond strength and adhesion factors such as substrate hardness, adhesion distance, van der Waals constant, and particle diameter. The NPS adhesion model is verified as a first order adhesion model using experimental data from seventeen packaging materials. Substrate hardness is identified as a primary factor in NPS adhesion. Adhesion distance and van der Waals constant are also significant in organic and inorganic materials. Diffusion or other interfacial reaction between NPS and metal substrates such as copper and silver seems to exist. Finally, guidelines to improve the adhesion strength of NPS are suggested based on the adhesion model and on external adhesion factors such as Silane coupling agents and plasma treatment.

This research reports for the first time conductive anodic filament reliability of copper plated-through-vias with spacing of 75 – 200 µm in thin glass fiber reinforced organic packaging substrates with advanced epoxy-based and cyclo-olefin polymer resin systems. Reliability studies were conducted in halogenated and halogen-free substrates with improved test structure designs including different conductor spacing and geometry. Accelerated test condition (temperature, humidity and DC bias voltage) was used to investigate the effect of conductor spacing and substrate material influence on insulation reliability behavior. Characterization studies included gravimetric measurement of moisture sorption, extractable ion content analysis, electrical resistance measurement, impedance spectroscopy measurement, optical microscopy and scanning electron microscopy analysis and elemental characterization using energy dispersive x-ray spectroscopy. The accelerated test results and characterization studies indicated a strong dependence of insulation failures on substrate material system, conductor spacing and geometry. This study presents advancements in the understanding of failure processes and chemical nature of failures in fine-pitch copper plated-through-vias in newly developed organic substrates and demonstrates potential methods to mitigate failures for high density organic packages.

Out-of-plane displacement (warpage) is one of the major thermomechanical reliability concerns for board-level electronic packaging. Printed wiring board (PWB) and component warpage results from CTE mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly reflow processes and normal operations may cause serious reliability problems. In this research, a convective reflow and projection moire warpage measurement system was developed. The system is the first real-time, non-contact, and full-field measurement system capable of measuring PWB/PWBA/chip package warpage with the projection moire technique during different thermal reflow processes. In order to accurately simulate the reflow process and to achieve the ideal heating rate, a convective heating system was designed and integrated with the projection moire system. An advanced feedback controller was implemented to obtain the optimum heating responses. The developed system has the advantages of simulating different types of reflow processes, and reducing the temperature gradients through the PWBA thickness to ensure that the projection moire system can provide more accurate measurements. Automatic package detection and segmentation algorithms were developed for the projection moire system. The algorithms are used for automatic segmentation of the PWB and assembled packages so that the warpage of the PWB and chip packages can be determined individually. The effect of initial PWB warpage on the fatigue reliability of solder bumps on board assemblies was investigated using finite element modeling (FEM) and the projection moire system. The 3-D models of PWBAs with varying board warpage were used to estimate the solder bump fatigue life for different chip packages mounted on PWBs. The simulation results were validated and correlated with the experimental results obtained using the projection moire system and accelerated thermal cycling tests. Design of experiments and an advanced prediction model were generated to predict solder bump fatigue life based on the initial PWB warpage, package dimensions and locations, and solder bump materials. This study led to a better understanding of the correlation between PWB warpage and solder bump thermomechanical reliability on board assemblies.

Thesis (M.S.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, 2005. / Includes bibliographical references (p. 94-96).

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007. / Includes bibliographical references.

Thesis (Ph. D.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008. / Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department or Systems Science and Industrial Engineering, 2009. / Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009. / Includes bibliographical references.