Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2009. / Includes bibliographical references.

Flexible electronics has attracted significant attention in the recent past due to the booming wearables market in addition to the ever-increasing interest for faster, thinner and foldable mobile phones. Ultra-thin bare silicon ICs fabricated by thinning down standard ICs to thickness below 50 μm are flexible and therefore they can be integrated on or in polymer foils to create flexible hybrid electronic (FHE) components that could be used to replace rigid standard surface mount device (SMD) components. The fabricated FHE components referred as chip foil packages (CFPs) in this work are ideal candidates for FHE system integration owing to their ability to deliver high performance at low power consumption while being mechanically flexible. However, very limited information is available in the literature regarding the reliability of CFPs under static and dynamic bending. The lack of such vital information is a major obstacle impeding their commercialization. With the aim of addressing this issue, this thesis investigates the static and dynamic bending reliability of CFPs. In this scope, the static bending reliability of CFPs has been investigated in this thesis using flexural bending tests by measuring their fracture strength. Then, Finite Element Method (FEM) simulations have been implemented to calculate the fracture stress of ultra-thin flexible silicon chips where analytical formulas may not be applied. After calculating the fracture stress from FEM simulations, the enhancement in robustness of ultra-thin chips (UTCs) against external load has also been proved and quantified with further experimental investigations. Besides, FEM simulations have also been used to analyse the effect of Young’s Modulus of embedding materials on the robustness of the embedded UTCs. Furthermore, embedding the UTCs in polymer layers has also been experimentally proven to be an effective solution to reduce the influence of thinning and dicing induced damages on the robustness of the embedded UTCs. Traditional interconnection techniques such as wire bonding may not be implemented to interconnect ultra-thin silicon ICs owing to the high mechanical forces involved in the processes that would crack the chips. Therefore, two novel interconnection methods namely (i) flip-chip bonding with Anisotropic Conductive Adhesive (ACA) and (ii) face-up direct metal interconnection have been implemented in this thesis to interconnect ultra-thin silicon ICs to the corresponding interposer patterns on foil substrates. The CFP samples thus fabricated were then used for the dynamic bending reliability investigations. A custom-built test equipment was developed to facilitate the dynamic bending reliability investigations of CFPs. Experimental investigations revealed that the failure of CFPs under dynamic bending was caused mainly by the cracking of the redistribution layer (RDL) interconnecting the chip and the foil. Furthermore, it has also been shown that the CFPs are more vulnerable to repeated compressive bending than to repeated tensile bending. Then, the influence of dimensional factors such as the thickness of the chip as well as the RDL on the dynamic bending reliability of CFPs have also been studied. Upon identifying the plausible cause behind the cracking of the RDL leading to the failure of the CFPs, two methods to improve the dynamic bending reliability of the RDL have been suggested and demonstrated with experimental investigations. The experimental investigations presented in this thesis adds some essential information to the state-of-the-art concerning the static and the dynamic bending reliability of UTCs integrated in polymer foils that are not yet available in the literature and aids to establish in-depth knowledge of mechanical reliability of the components required for manufacturing future FHE systems. The strategies devised to enhance the robustness of UTCs and CFPs could serve as guidelines for fabricating reliable FHE components and systems.

Due to the power requirements for today's microprocessors, point of load converter packaging is becoming an important issue.   Traditional thermal management techniques involved in removing heat from a printed circuit board are being tested as today's technologies require small footprint and volume from all electrical systems.  While heat sinks are traditionally used to spread heat, ceramic substrates are gaining in popularity for their superior thermal qualities which can dissipate heat without the use of a heat sink.  3D integration techniques are needed to realize a solution that incorporates the active and components together.  The objective of this research is to explore the packaging of a high current, high power density, high frequency DC/DC converter using ceramic substrates to create a low profile converter to meet the needs of current technologies. One issue with current converters is the large volume of the passive components.  Increasing the switching frequency to the megahertz range is one way to reduce to volume of these components.  The other way is to fundamentally change the way these inductors are designed.  This work will explore the use of low temperature co-fired ceramic (LTCC) tapes in the magnetic design to allow a low profile planar inductor to be used as a substrate.  LTCC tapes have excellent properties in the 1-10 MHz range that allow for a high permeability, low loss solution.  These tapes are co-fired with a silver paste as the conductor.  This paper looks at ways to reduce dc resistance in the inductor design through packaging methods which in turn allow for higher current operation and better heavy load efficiency.  Fundamental limits for LTCC technologies are pushed past their limits during this work.  This work also explores fabrication of LTCC inductors using two theoretical ideas: vertical flux and lateral flux.  Issues are presented and methods are conceived for both types of designs.  The lateral flux inductor gives much better inductance density which results in a much thinner design. It is found that the active devices must be shielded from the magnetic substrate interference so active layer designs are discussed.  Alumina and Aluminum Nitride substrates are used to form a complete 3D integration scheme that gives excellent thermal management even in natural convection.  This work discusses the use of a stacked power technique which embeds the devices in the substrate to give double sided cooling capabilities.  This fabrication goes away from traditional photoresist and solder-masking techniques and simplifies the entire process so that it can be transferred to industry.  Time consuming sputtering and electroplating processes are removed and replaced by a direct bonded copper substrate which can have up to 8 mil thick copper layers allowing for even greater thermal capability in the substrate.  The result is small footprint and volume with a power density 3X greater than any commercial product with comparable output currents.  A two phase coupled inductor version using stacked power is also presented to achieve even higher power density. As better device technologies come to the marketplace, higher power density designs can be achieved.  This paper will introduce a 3D integration design that includes the use of Gallium Nitride devices.  Gallium Nitride is rapidly becoming the popular device for high frequency designs due to its high electron mobility properties compared to silicon.  This allows for lower switching losses and thus better thermal characteristics at high frequency.  The knowledge learned from the stacked power processes gives insight into creating a small footprint, high current ceramic substrate design.  A 3D integrated design is presented using GaN devices along with a lateral flux inductor.  Shielded and Non-Shielded power loop designs are compared to show the effect on overall converter efficiency.  Thermal designs and comparisons to PCB are made using thermal imaging.  The result is a footprint reduction of 40% from previous designs and power densities reaching close to 900W/in3. / Master of Science

<p>  </p> <p>Due to miniaturization of electronic devices new electronic packaging strategies, such as Heterogeneous Integration Packaging (HIP), are being developed. In HIP, the space in the package is strategically mapped out to maximize the placement of components including all types of materials. Thus, there is a need to develop and understand the behavior of lower-melting point metallic interconnects as they will be located next to lower melting point materials, such as polymers. </p> <p>The composition of alloying elements in Sn-rich solder plays a pivotal role in determining the microstructural properties of the solder joint. However, the complex mechanisms governing the solidification processes of Sn-In, and Sn-Bi alloys are still not fully understood. Furthermore, the experimental characterization of phase formation poses significant challenges.</p> <p>This dissertation focuses on understanding microstructural evolution in Sn-In and Sn-Bi alloys during reflow. A systematic approach to characterizing the microstructure of alloys was developed, utilizing electron microscopy, non-destructive x-ray tomography and diffraction techniques, ranging from lab-scale to synchrotron experiments. The influence of In addition on microstructure was correlated with the mechanical behavior obtained using nanoindentation. The experimental understanding was further correlated with the Density Functional Theory (DFT) calculations. To study the Sn-Bi microstructures, the effect of experimental parameters, such as the cooling rate during solidification was elucidated. A 4D study was conducted, involving the analysis of 3D microstructures along with time evolution, to gain a comprehensive understanding of the solidification dynamics using synchrotron white beam tomography. For the first time, we observed a regular pyramidal morphology of Bi forming in the solder alloy. The 4D analysis provided crucial insights into morphology formation, growth kinetics, defect formation during solidification. The crystallographic analysis unraveled unique insights into the solid-liquid interface stability for semi-metals. Furthermore, the simultaneous Energy Dispersive Diffraction (EDD) analysis yielded a deeper understanding into the phase formation and lattice strain evolution. A fundamental relationship between the diffraction intensity and phase fractions, from imaging, was obtained. The experimental methodology developed in this work has the potential to be extended to investigate a wide range of alloy solidification mechanisms, enabling a deeper understanding of these materials.</p>

This research has developed a lead-free semiconductor device interconnect technology by studying the processing-microstructure-property relationships of low-temperature sintering of nanoscale silver pastes. The nanoscale silver pastes have been formulated by adding organic components (dispersant, binder and thinner) into nano-silver particles. The selected organic components have the nano-particle polymeric stabilization, paste processing quality adjustment, and non-densifying diffusion retarding functions and thus help the pastes sinter to ~80% bulk density at temperatures no more than 300°C. It has been found that the low-temperature sintered silver has better electrical, thermal and overall thermomechanical properties compared with the existing semiconductor device interconnecting materials such as solder alloys and conductive epoxies. After solving the organic burnout problems associated with the covered sintering, a lead-free semiconductor device interconnect technology has been designed to be compatible with the existing surface-mounting techniques with potentially low-cost. It has been found that the low-temperature sintered silver joints have high electrical, thermal, and mechanical performance. The reliability of the silver joints has also been studied by the 50-250°C thermal cycling experiment. Finally, the bonging strength drop of the silver joints has been suggested to be ductile fracture in the silver joints as micro-voids nucleated at microscale grain boundaries during the temperature cycling. The low-temperature silver sintering technology has enabled some benchmark packaging concepts and substantial advantages in future applications. / Ph. D.

The work reported in this dissertation is intended to propose, analyze and demonstrate a technology for a high temperature integrated power electronics module, for high temperature (e.g those over 200oC) applications involving high density and low stress. To achieve this goal, this study has examined some existing packaging approaches, such as wire-bond interconnects and solder die-attach, flip-chip and pressure contacts. Based on the survey, a high temperature, multilayer 3-D packaging technology in the form of an Embedded Chip Module (ECM) is proposed to realize a lower stress distribution in a mechanically balanced structure with double-sided metallization layers and material CTE match in the structure. Thermal and thermo-mechanical analysis on an ECM is then used to demonstrate the benefits on the cooling system, and to study the material and structure for reducing the thermally induced mechanical stress. In the thermal analysis, the high temperature ECM shows the ability to handle a power density up to 284 W/in3 with a heat spreader only 2.1x2.1x0.2cm under forced convection. The study proves that the cooling system can be reduced by 76% by using a high temperature module in a room temperature environment. Furthermore, six proposed structures are compared using thermo-mechanical analysis, in order to obtain an optimal structure with a uniform low stress distribution. Since pure Mo cannot be electroplated, the low CTE metal Cr is proposed as the stress buffering material to be used in the flat metallization layers for a fully symmetrical ECM structure. Therefore, a chip area stress as low as 126MPa is attained. In the fabrication process, the high temperature material glass and a ceramic adhesive are applied as the insulating and sealing layers. Particularly, the Cr stress buffering layer is successfully electroplated in the high temperature ECM by means of the hard chrome plating process. The flat metallization layer is accomplished by using a combined structure with Cr and Cu metallization layers. The experimental evaluations, including the electrical and thermal characteristics of the ECM, have been part of in the study. The forward and reverse characteristics of the ECM are presented up to 250oC, indicating proper device functionality. The study on the reverse characteristics of the ECM indicates that the large leakage current at high temperature is not due to the package surrounding the chip, but chiefly caused by the Schottky junction and the chip passivation layer. Finally, steady-state and transient measurements are conducted in terms of the thermal measurements. The steady-state thermal measurement is used to demonstrate the cooling system reduction. To obtain the thermal parameters of the different layers in the high temperature ECM, the transient thermal measurement is applied to a single chip ECM based on the temperature cooling-down curve measurement. / Ph. D.

This work developed a process to provide physical, electrical, and environmental protection to the electrical lead system of an optical switch device. A literature review was conducted to find materials and processes suitable to the stress-sensitive, high voltage characteristics of many optical switch devices. An automatic dispensing dam and fill process, and three candidate materials (two epoxy and one silicone) were selected for investigation. Experimental and analytical techniques were used to evaluate the materials. Methods applied included interferometric die warpage measurements, electrochemical migration resistance tests (ECMT), thermal cycling, and finite element analysis. The silicone dam and fill system was selected based upon the results of die warpage and electrochemical migration resistance tests. A modified, selective dam and fill process was developed and preliminary reliability testing was performed. The paper provides detailed instructions for successful encapsulation of the optical switch's lead system.

Thesis (M.S.)--State University of New York at Binghamton, Department of Mechanical Engineering, 2005. / Includes bibliographical references (leaves 70-72).

The objective of this dissertation is to develop electrical modeling and co-simulation methodologies for signal and power integrity of package and board applications. The dissertation includes 1) the application of the finite element method to the optimization for decoupling capacitor selection and placement on a power delivery network (PDN), 2) the development of a PDN modeling method effective for multidimensional and multilayer geometries, 3) the analysis and modeling of return path discontinuities (RPDs), and 4) the implementation of the absorbing boundary condition for PDN modeling. The optimization technique for selection and placement of decoupling capacitors uses a genetic algorithm (GA) and the multilayer finite element method (MFEM), a PDN modeling method using FEM. The GA is customized for the decoupling problem to enhance the convergence speed of the optimization. The mathematical modifications necessary for the incorporation of the capacitor model into MFEM is also presented. The main contribution of this dissertation is the development of a new modeling method, the multilayer triangular element method (MTEM), for power/ground planes of a PDN. MTEM creates a surface mesh on each plane-pair using dual graphs; a non-uniform triangular mesh (Delaunay triangulation) and its orthogonal counterpart (Voronoi diagram), to which electromagnetic and equivalent circuit concepts are applied. The non-uniform triangulation is especially efficient for discretizing multidimensional and irregular geometries which are common in package and board PDNs. Moreover, MTEM generates a sparse, banded, and symmetric system matrix, which enables efficient computations. For a given plane-pair, MTEM extracts an equivalent circuit that is consistent with the physics-based planar-circuit model of a plane-pair. Thus, the values of the lumped elements can be simply calculated from the physical parameters, such as material properties and mesh geometries of each unit-cell. Consequently, the modeling of MTEM is flexible and easy to modify for further extensions, such as the incorporation of external circuits, e.g. decoupling capacitors and vertical interconnects. Power and ground planes provide paths for the return current of signal traces. Typically, planes have discontinuities such as via holes, plane cutouts, and split planes that disturb flow of signal return currents. At the discontinuity, return currents have to detour or switch to different layers, causing signal and power integrity problems. Therefore, a separate analysis of signal interconnects will neglect the significant coupling with a PDN, and the result will not be reliable. In this dissertation, the co-simulation of the signal and power integrity is presented focusing on the modeling of RPDs created by split planes, apertures, and vias. Plane resonance is one of the main sources of power integrity problems in package and board PDNs. A number of techniques have been developed and published in literature to reduce or prevent the resonance of a plane-pair. One of the techniques is to surround plane-pair edges with absorbing material that effectively damps the outgoing parallel-plate wave and minimizes the reflection. To model this behavior, the boundary condition of MTEM needs to be changed from its original form, the open-circuit boundary condition. In this dissertation, the application of the 1st order absorbing boundary condition to MTEM is presented.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009. / Includes bibliographical references.