Fieldbuses are defined as a family of communication media specified for industrial applications. They usually interconnect embedded systems. Embedded systems exist everywhere in the modern world, they are included in simple personal technology as well as the most advanced spaceships. They aid in producing a specific task, often with the purpose to generate a greater system functionality. These kinds of implementations put high demands on the communication media. For a medium to be applicable for use in embedded systems, it has to reach certain requirements. Systems in industry practice react on real-time events or depend on consistent timing. All kinds are time sensitive in their way. Failing to complete a task could lead to irritation in slow monitoring tasks, or catastrophic events in failing nuclear reactors. Fieldbuses are optimized for this usage. This thesis aims to research fieldbus theory and connect it to industry practice. Through interviews, requirements put on industry are explored and utilization of specific types of fieldbuses assessed. Based on the interviews, guidelines are put forward into what fieldbus techniques are relevant to study in preparation for future work in the field. A discussion is held, analysing trends in, and synergy between, state of the art and the state of practice. A strong momentum is identified. The traditional communication media Ethernet, not originally intended for time-sensitive industry appliances, are expanding throughout the field, both in research and, maybe most interestingly, in practice. It is mainly motivated through qualities of somewhat lesser technical significance. A plethora of methods have emerged trying to optimize Ethernet for real-time purposes, each one resulting in some drawbacks, which are in turn addressed. In the end of this paper, the large-scale trend of Real-Time Ethernet is questioned and discussed.

Sensors with very low power consumption are required so that they can last a long time without the need to replace the batteries very often. Low power sensors can save significant cost and time incurred in battery replacement, especially in establishments and organizations that span over several buildings, floors and rooms. In this thesis, we investigate the use of the low-power wireless protocol Z-wave for sensors solutions that can last for approximately 10 years. An algorithm was created and we concluded that 10 years on a 480 mAh battery is not possible and the expected years need to be lowered or we need to increase the battery capacity.

The aim of this thesis is to create a port of the Zephyr realtime operating systemfor the LEON processor platform. The LEON is a frequently used computing corefor spaceflight applications, with ample flight heritage. It is based upon the wellestablished SPARC v8 instruction set, and offers many extensions to ease softwaredevelopment and increase overall processor performance. An overview of the nec-essary steps towards a functional architecture port is given in this report. Specialemphasis is put upon the interrupt handling and context switching. One LEONspecific feature introduced with the GR716 LEON3-FT microcontroller, registerwindow partitioning, is used to increase the performance of the context switchingmechanism in the operating system. By using this feature, context switching timehas shown to decrease significantly, while easing verification of the overall softwaresystem by providing dedicated partitions for tasks with hard realtime requirements. / Det övergripande målet med examensarbetet är att porta Zephyr realtidsopera-tivsystem (OS) till LEON processorplattformen. LEON processorn är ursprungligendesignad för och förekommer ofta i datorsystem inom rymd p.g.a. sina feltolerantaegenskaper. LEON är kompatibel med den öppna SPARC v8 instruktionsuppsät-tningen vilken också tillåter utökning och anpassningar. Rapporten ger läsaren enöverblick av vilka steg som är nödvändiga för att skapa en fungerande arkitektur-port av ett OS. Vidare beskriver rapporten mer i detalj designen kring trådväxlingoch avbrottshantering, samt hur dessa anpassas för att utnyttja LEON specifikautökningar av SPARC till att nå högre prestanda. GR716 LEON3-FT introducerarpartitionering av SPARC registerfönster för att kunna minska tiden det tar opera-tivsystemet att växla trådar. Denna funktion har inte använts tidigare i något OS,och är därför av särskilt intresse att studera och karakterisera. Resultaten visar atttrådväxlingstiden minskat signifikant, samtidigt som determinismen blivit bättreoch därigenom är det nu enklare att designa system med hårda realtidskrav.

This master’s thesis covers the design and implementation of a monopulse directionof arrival (DOA) estimation algorithm on an FPGA. The goal is to implement a complete system that is capable of estimating the bearing of an incident signal. In order to determine the estimate quality both a theoretical and practical noise analysis of the signal chain is performed. Special focus is placed on the statistical properties of the transformation from I/Q-demodulated signals with correlated noise to a polar representation. The pros and cons for three different methods of calculating received signal phasors are also covered.The system is limited to two receiving channels which constrains this report to a 2D analysis. In addition the used hardware is limited to C-band signals. We show that an FPGA implementation of monopulse techniques is definitely viable and that an SNR higher than ten dB allows for a gaussian approximation of the polar representationof an I/Q signal.

Unmanned vehicles, both ground and aerial, have become prevalent in recent years. The research community has different needs than the industrial community when designing a finalized unmanned system since the vehicle, the sensors and the control design are dynamic and change frequently as new ideas are developed and implemented. Current autopilot hardware, which is available as on-the-market products and proposed in research, is sufficient for unmanned systems design. However, this equipment falls short of being able to accommodate the needs of those in the research community who must be able to quickly implement new ideas on a flexible platform. The contribution of this research is the realization of a hardware platform, which provides for rapid implementation of newly developed theory. Rapid implementation is gained by providing for software development from within the Simulink environment and utilizing previously unrealized flexibility in sensor selection. In addition to the development of the hardware platform, research was performed within Simulink's System Generator environment in order to complement the hardware. The software produced consists of a user template that integrates to the selected hardware. The template creates a user friendly environment, which provides the end user the capability to develop software algorithms from within the Simulink environment. This capability facilitates the final step of full hardware implementation. The major novelty of the research was the overall FPGA based autopilot design. The approach provided flexibility, functionality and generality. The approach is also suitable for and applicable to the design of multiple platforms. This research yielded a first time approach to the development of an unmanned systems autopilot platform by utilizing: -Development of programmable voltage level digital Input/Output (I/O), ports, -Utilization of Field Programmable Analog Arrays (FPAA), -Hardware capabilities to allow for integration with full computer systems, -A full Field Programmable Gate Array (FPGA), implementation, -Full integration of the hardware within Simulink's System Generator Toolbox

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This thesis presents design automation methodologies for extensible processor platforms in application specific domains. The work presents first a single processor approach for customization; a methodology that can rapidly create different processor configurations by the removal of unused instructions sets from the architecture. A profile directed approach is used to identify frequently used instructions and to eliminate unused opcodes from the available instruction pool. A coprocessor approach is next explored to create an SoC (System-on-Chip) to speedup the application while reducing energy consumption. Loops in applications are identified and accelerated by tightly coupling a coprocessor to an ASIP (Application Specific Instruction-set Processor). Latency hiding is used to exploit the parallelism provided by this architecture. A case study has been performed on a JPEG encoding algorithm; comparing two different coprocessor approaches: a high-level synthesis approach and our custom coprocessor approach. The thesis concludes by introducing a heterogenous multi-processor system using ASIPs as processing entities in a pipeline configuration. The problem of mapping each algorithmic stage in the system to an ASIP configuration is formulated. We proposed an estimation technique to calculate runtimes of the configured multiprocessor system without running cycle-accurate simulations, which could take a significant amount of time. We present two heuristics to efficiently search the design space of a pipeline-based multi ASIP system and compare the results against an exhaustive approach. In our first approach, we show that, on average, processor size can be reduced by 30%, energy consumption by 24%, while performance is improved by 24%. In the coprocessor approach, compared with the use of a main processor alone, a loop performance improvement of 2.57x is achieved using the custom coprocessor approach, as against 1.58x for the high level synthesis method, and 1.33x for the customized instruction approach. Energy savings are 57%, 28% and 19%, respectively. Our multiprocessor design provides a performance improvement of at least 4.03x for JPEG and 3.31x for MP3, for a single processor design system. The minimum cost obtained using our heuristic was within 0.43% and 0.29% of the optimum values for the JPEG and MP3 benchmarks respectively.

As embedded systems designers increasingly turn to programmable logic technologies in place of off-the-shelf microprocessors, there is a growing interest in the development of optimised custom processing cores that can be designed on a per-application basis. FPGAs blur the traditional distinction between hardware and software and offer the promise of application specific hardware acceleration. But realizing this in a general sense requires a significant departure from traditional embedded systems development flows. Whereas off-the-shelf processors have a fixed architecture, the same cannot be said of purpose-built FPGA-based processors. With this freedom comes the challenge of empirically determining the optimal boundary point between hardware and software. The fluidity of the hardware/software partition also poses an interesting challenge for compiler developers. This thesis presents a tool and methodology that addresses these codesign challenges in a new way. Described as 'compiler-directed codesign', it makes use of a suitably modified compiler to help direct the development of a custom processor core on a per-application basis. By exposing the compiler's internal representation of a compiled target program, visibility into those instructions, and hardware resources, that are most sought after by the compiler can be gained. This information is then used to inform further processor development and to determine the optimal partition between hardware and software. At each design iteration, the machine model is updated to reflect the available hardware resources, the compiler is rebuilt, and the target application is compiled once again. By including the compiler 'in-the-loop' of custom processor design, developers can accurately quantify the impact on performance caused by the addition or removal of specific hardware resources and iteratively converge on an optimal solution. Compiler Directed Codesign has advantages over existing codesign methodologies because it offers both a concrete point from which to begin the partitioning process as well as providing quantifiable and rapid feedback of the merits of different partitioning choices. When applied to an Adaptive PCM Encoder/Decoder case study, the Compiler Directed Codesign technique yielded a custom processor core that was between 36% and 73% smaller, consumed between 11% to 19% less memory, and performed up to 10X faster than comparable general-purpose FPGA-based processor cores. The conclusion of this work is that a suitably modified compiler can serve a valuable role in directing hardware/software partitioning on a per-application basis.

AADL est dédié à la conception de haut niveau et l'évaluation de systèmes embarqués. Il permet de décrire la structure d'un système et ses aspects fonctionnels par une approche à base de composants. Des processus localement synchrones sont alloués sur une architecture distribuée et communiquent de manière globalement asynchrone (système GALS). Une spécificité du modèle polychrone est qu'il permet de spécifier un système dont les composants peuvent avoir leur propre horloge d'activation : il est bien adapté à une méthodologie de conception GALS. Dans ce cadre, l'atelier Polychrony fournit des modèles et des méthodes pour la modélisation, la transformation et la validation de systèmes embarqués. Cette thèse propose une méthodologie pour la modélisation et la validation de systèmes embarqués spécifiés en AADL via le langage synchrone multi-horloge Signal. Cette méthodologie comprend la modélisation de niveau système en AADL, des transformations automatiques du modèle AADL vers le modèle polychrone, la distribution de code, la vérification formelle et la simulation du modèle polychrone. Notre transformation prend en compte l'architecture du système, décrite dans un cadre IMA, et les aspects fonctionnels, les composants logiciels pouvant être mis en œuvre en Signal. Les composants AADL sont modélisés dans le modèle polychrone en utilisant une bibliothèque de services ARINC. L'annexe comportementale d'AADL est interprétée dans ce modèle via SSA. La génération de code distribué est obtenue avec Polychrony. La vérification formelle et la simulation sont effectuées sur deux études de cas qui illustrent notre méthodologie pour la conception fiable des applications AADL.

<p>Events play an important role in many computer systems, from small reactive embedded applications to large distributed systems. Many applications react to events generated by a graphical user interface or by external sensors that monitor the system environment, and other systems use events for communication and synchronisation between independent subsystems. In some applications, however, individual event occurrences are not the main point of concern. Instead, the system should respond to certain event patterns, such as "the start button being pushed, followed by a temperature alarm within two seconds". One way to specify such event patterns is by means of an event algebra with operators for combining the simple events of a system into specifications of complex patterns.</p><p>This thesis presents an event algebra with two important characteristics. First, it complies with a number of algebraic laws, which shows that the algebra operators behave as expected. Second, any pattern represented by an expression in this algebra can be efficiently detected with bounded resources in terms of memory and time, which is particularly important when event pattern detection is used in embedded systems, where resource efficiency and predictability are crucial.</p><p>In addition to the formal algebra semantics and an efficient detection algorithm, the thesis describes how event pattern detection can be used in real-time systems without support from the underlying operating system, and presents schedulability theory for such systems. It also describes how the event algebra can be combined with a component model for embedded system, to support high level design of systems that react to event patterns.</p>