The Tunnel Field Effect Transistor (TFET) with sub-60mV/decade Sub-threshold slope and extremely high ION/IOFF ratio has attracted enough attention for low standby power (LSTP) applications where the battery life is very important. So far research in this area has been limited to numerical simulation and experimental analysis. It is however extremely necessary to develop compact models for TFET in order to use them in nano-scale integrated circuit design and simulation. In this work, for the first time, we develop analytical Sub-threshold slope model for n-channel double gate TFET (nDGTFET). Unlike conventional FETs, current in TFET is mainly controlled by the band-to-band tunneling mechanism at source/channel interface. As the total drain current is proportional to band-to-band generation rate, the main challenge in the present work is to find an explicit relationship between average electric field over the tunneling path and the applied gate voltage under nonlocal tunneling condition. Two dimensional Poisson’s equation (with Laplace approximation)is first solved in a rectangular coordinate system in order to obtain analytical expression for electron energy distribution over the channel region.Kane’s Model[J. Phy. Chem.Solids 12(181)1959]for band-to-band tunneling along with some analytical approximation techniques are then used to derive the expression for the Sub-threshold slope under nonlocal tunneling conditions. This Sub-threshold slope model is verified against professional numerical device simulator (MEDICI) for different device geometries. Being an asymmetric device, TFET fabrication suffers from source misalignment with gate. As the doping in source and drain-gate are different, conventional-FET-like self-aligned gate stack formation is not possible for TFET. Such misalignment, at source side, seriously degrades the performance of TFETs. To overcome this problem, in this work we explore the possibility of using “gate replacement” technique for TFET fabrication. We first develop process flow for single gate bulk nTFET, and then we extend it to n-channel double gate TFET (nDGTFET) using modified FinFET process. Good alignments between source and gate are observed with TCAD-simulations in both the cases.

Die vorliegende Arbeit beschreibt die Berechnung und Optimierung von Silicon-On-Insulator-Metal-Oxide-Semiconductor-Field-Effect-Transistors, einschließlich noch nicht in Massenproduktion hergestellter neuartiger Transistorarchitekturen für die nächsten Technologiegenerationen der hochleistungsfähigen Logik-MOSFETs mit Hilfe der Prozess- und Bauelementesimulation. Die neuartigen Transistorarchitekturen umfassen dabei vollständig verarmte SOI-MOSFETs, Doppel-Gate-Transistoren und FinFETs. Die statische und dynamische Leistungsfähigkeit der neuartigen Transistoren wird durch Simulation bestimmt und miteinander verglichen. Der mit weiterer Skalierung steigende Einfluss von statistischen Variationen wird anhand der Oberflächenrauheit sowie der Polykantenrauheit untersucht. Zu diesem Zweck wurden Modelle für die Generierung der Rauheit erarbeitet und in das Programmsystem SIMBA implementiert. Die mikroskopische Rauheit wird mit der makroskopischen Bauelementesimulation kombiniert und deren Auswirkungen auf die Standardtransistoren und skalierte Bauelemente aufgezeigt. Zudem erfolgt eine ausführliche Diskussion der Modellierung mechanischer Verspannung und deren Anwendung zur Steigerung der Leistungsfähigkeit von MOSFETs. Die in SIMBA implementierten Modelle zur verspannungs-abhängigen Änderung der Ladungsträgerbeweglichkeit und Lage der Bandkanten werden ausführlich dargestellt und deren Einfluss auf die elektrischen Parameter von MOSFETs untersucht. Weiterhin wird die Verspannungsverteilung für verschiedene Herstellungsvarianten mittels der Prozess-simulation berechnet und die Wirkung auf die elektrischen Parameter dargestellt. Exponential- und Gaußverteilungsfunktionen bilden die Grundlage, um die mechanische Verspannung in der Bauelementesimulation nachzubilden, ohne die Verspannungsprofile aus der Prozesssimulation zu übernehmen. Darüber hinaus werden die Grenzfrequenzen der Logiktransistoren in Bezug auf die parasitären Kapazitäten und Widerstände und zur erweiterten MOSFET-Charakterisierung dargestellt.

Dans ce projet de thèse, deux voies visant l'élaboration de transistors à effet de champ en diamant ont été explorées : le delta-doping et la structure métal oxyde semi-conducteur (MOS). Plusieurs couches nanométriques delta-dopées au bore ont été épitaxiées et caractérisées par effet Hall. Un mécanisme de conduction par saut a été détecté dans les couches isolantes. Une mobilité de 3±1 cm2/Vs a été mesurée dans toutes les couches delta-dopées présentant une conduction métallique, quelque soit leur épaisseur (de 2 nm à 40 nm). Des structures MOS ont été fabriquées en utilisant de l'oxyde d'aluminium déposé par ALD (Atomic Layer Deposition) sur une surface oxygénée de diamant. Les mesures capacité tension ont montré que les régimes d'accumulation, de déplétion et de déplétion profonde pouvaient être contrôlés par la tension de grille, ouvrant ainsi la voie pour la fabrication de MOSFET en diamant.

The aim of this study is to ascertain what misconceptions N2 students have about DC resistive circuits and how screencasts could effect on the rectification of these misconceptions. This study was conducted at the Kathu Campus of the Northern Cape Rural Further Education and Training College in the town Kathu in the arid Northern Cape. The empirical part of this study was conducted during the first six months of 2013. A design-based research (DBR) method consisting of four phases was used. DBR function is to design and develop interventions such as a procedure, new teachinglearning strategies, and in the case of this study a technology-enhanced learning (TEL) tool (screencast) with the purpose of solving a versatile didactic problem and to acquire information about the interventions of the TEL tool (screencast) on the learning of a student. In the first and second phase of DBR quantitative data for this research were gathered with the Determining and Interpreting Resistive Electric circuits Concepts Test (DIRECT) in order to determine the four most common misconceptions. The DIRECT test was conducted in the first trimester to find the misconceptions; the test was conducted in the second trimester also to confirm the misconceptions. Further quantitative data were collected from a demographic questionnaire. The qualitative data were collected by individual interviews in the fourth phase of the research project. Phase three of this study was the development of screencasts in the four most prominent misconceptions in DC resistive circuits of the students. The respondents of this study were non-randomly chosen and comprised of two groups, one in the first trimester of the year and one in the second trimester of the year, which enrolled for the N2 Electrical or Millwright courses. The respondents were predominant male and representing the three main cultural groups in the Northern Cape namely: Black, Coloured and White. The four misconceptions on DC resistive circuits that were identified were: (i) understanding of concepts, (ii) understanding of short circuit, (iii) battery as a constant current source, and (iv) rule application error. Screencasts clarifying the four misconceptions were developed and distributed to the respondents. On the foundation of the results of this research, it can be concluded that the students have several misconceptions around direct current resistive direct current circuits and that the use of TEL like screencasts can be used to solve some of these misconceptions. Screencasts could supplement education when they were incorporated into the tutoring and learning for supporting student understanding. The results of this research could lead to the further development and refinement of screencasts on DC resistive circuits and also useable guidelines in creating innovative screencasts on DC resistive circuits. / MEd (Curriculum Development), North-West University, Potchefstroom Campus, 2014

Une des principales solutions technologiques liées à la réduction d’échelle de la technologie CMOS est aujourd’hui clairement orientée vers les transistors MOSFET faiblement dopés à multiples grilles. Ceux-ci proposent une meilleure immunité contre les effets canaux courts comparés aux transistors MOSFET bulk planaires (cf. ITRS 2011). Parmi les MOSFETs à multiples grilles, le transistor FinFET SOI est un candidat intéressant de par la similarité de son processus de fabrication avec la technologie des transistors planaires. En parallèle, il existe une réelle attente de la part des concepteurs et des fonderies à disposer de modèles compacts efficaces numériquement, précis et proches de la physique, insérés dans les « design tools » permettant alors d’étudier et d’élaborer des circuits ambitieux en technologie FinFET. Cette thèse porte sur l’élaboration d’un modèle compact orienté conception du transistor FinFET valide aux dimensions nanométriques. Ce modèle prend en compte les effets canaux courts, la modulation de longueur de canal, la dégradation de la mobilité, leseffets de mécanique quantique et les transcapacités. Une validation de ce modèle est réalisée par des comparaisons avec des simulations TCAD 3D. Le modèle compact est implémenté en langage Verilog-A afin de simuler des circuits innovants à base de transistors FinFET. Une modélisation niveau-porte est développée pour la simulation de circuits numériques complexes. Cette thèse présente également un modèle compact générique de transistors MOSFET SOI canaux long faiblement dopés à multiple grilles. La dépendance à la température est prise en compte. Selon un concept de transformation géométrique, notre modèle compact du transistor MOSFET double grille planaire est étendu pour s’appliquer à tout autre type de transistor MOSFET à multiple grille (MuGFET). Une validation expérimentale du modèle MuGFET sur un transistor triple grille est proposée. Cette thèse apporte enfin des solutions pour la modélisation des transistors MOSFET double grille sans jonction. / One of the main technological solutions related to downscaling of CMOS technology is now clearly oriented to lightly doped multigate MOSFETs. They offer better immunity against short channel effects compared to planar bulk MOSFETs (see ITRS 2011). Among the multigate MOSFETs, the SOI FinFET transistor is an interesting candidate because of the similarity of its manufacturing process with the planar transistor technology. In parallel, there is a real expectation on the part of designers and foundries to have compact models numerically efficient, accurate and close to the physics, and then inserted in to the design tools in order to study and develop ambitious circuits in FinFET technology. This thesis focuses on the development of a design-oriented compact model of FinFET transistor valid to nanoscale dimensions. This model takes into account the short channel effects, the channel length modulation, the mobility degradation, the quantum mechanic effects and the transcapacitances. A validation of this model is carried out by comparisons with 3DTCAD simulations. The compact model is implemented in Verilog-A to simulate innovative FinFET-based circuits. A gate-level modeling is developed for the simulation of complex digital circuits. This thesis also presents a generic compact modeling of multigate SOI MOSFETs with lightly doped channels and temperature dependent. According to a concept of geometric transformation, our compact model of the planar double-gate MOSFET is extended to be applied to any other type of multigate MOSFETs (MuGFET). An experimental validation of the MuGFET compact model with a triple gate transistor is proposed. This thesis finally brings solutions for the modeling of junction less double-gate MOSFET.

Submitted by Geandra Rodrigues (geandrar@gmail.com) on 2018-01-11T18:27:28Z No. of bitstreams: 1 manoelcarlosdossantosjunior.pdf: 4607995 bytes, checksum: 47fe628f81ff50e0935ea700b075a416 (MD5) / Rejected by Adriana Oliveira (adriana.oliveira@ufjf.edu.br), reason: Favor corrigir: Título: Síntese e estudo raman de grafeno bicamada rodado sob influência e campo eléctrico Título: Síntese e estudo raman de grafeno bi-camada rodado sob influencia e campo eléctrico Verificar o acento em Júnior e corrigir "dos" Autor(es): Santos Junior, Manoel Carlos Dos on 2018-01-23T13:56:04Z (GMT) / Submitted by Geandra Rodrigues (geandrar@gmail.com) on 2018-01-23T14:05:52Z No. of bitstreams: 1 manoelcarlosdossantosjunior.pdf: 4607995 bytes, checksum: 47fe628f81ff50e0935ea700b075a416 (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2018-01-23T14:22:48Z (GMT) No. of bitstreams: 1 manoelcarlosdossantosjunior.pdf: 4607995 bytes, checksum: 47fe628f81ff50e0935ea700b075a416 (MD5) / Made available in DSpace on 2018-01-23T14:22:48Z (GMT). No. of bitstreams: 1 manoelcarlosdossantosjunior.pdf: 4607995 bytes, checksum: 47fe628f81ff50e0935ea700b075a416 (MD5) Previous issue date: 2016-02-26 / CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / No presente trabalho, usamos os dois principais modos de operação CVD, LPCVD (low Pressure Chemical Vapor Deposition – Deposição Química na Vapor em Baixa Pressão) e APCVD (Ambient Pressure Chemical Vapor Deposition – Deposição Química na Vapor em Pressão Ambiente), para a produção de filmes de grafeno bicamada rodado (GBR). O modo LPCVD se mostrou mais eficaz para produção de grafeno monocada de alta qualidade e cobrindo grandes áreas. Pelo modo APCVD foi possível otimizar uma rota reprodutível para sintetizar filmes de GBR com todos os ângulos possíveis e com dimensões suficientes para realização de medidas Raman com precisão espacial (≈100 ). Usamos, microscopia óptica e espectroscopia Raman para caracterizar os filmes de GBR. Posteriormente, os filmes sintetizados foram transferidos para um substrato litografado para confecção de um dispositivo de efeito de campo (FET). Fizemos um estudo sistemático das características Raman do GBR (frequência, largura máxima a meia altura e intensidades relativas das bandas G e 2D) como função da altura do nível de Fermi. Observamos uma diminuição das Anomalias de Kohn e um aumento do tempo de vida dos fônons responsáveis pela banda G tanto do grafeno quanto do GBR quando a tensão de porta é sintonizada. Observamos também que, para ângulos grandes, 20°≤≤30°, as principais características Raman do GBR se mantém constantes quando sintonizamos uma tensão de porta, em outras palavras, as curvas da frequência e da largura máxima a meia altura das bandas G e 2D assumem o mesmo comportamento. Contudo, para ângulos pequenos, menores que <7,5°, observamos alterações nas características Raman do grafeno quando uma tensão de porta é aplicada, principalmente na banda 2D. Ainda são necessários mais estudos para a compreensão correta desses fenômenos. Porém, atribuímos essas diferenças de comportamento das características Raman do GBR a uma diminuição da velocidade de Fermi dos elétrons nesse material para ângulos pequenos. Para ângulos grandes, não observamos nenhuma diferença nas características Raman do GBR. Isso pode ser explicado pelo fato de que, para ângulos grandes, as camadas do GBR estão praticamente desacopladas, fazendo com que as propriedades do GBR sejam semelhantes às de uma monocamada de grafeno. / In this work, we have employed, both, Low Pressure Chemical Vapor Deposition, (LPCVD) as well as Ambient Pressure Chemical Vapor Deposition (APCVD) to produce large areas of twisted bi-layer graphene. LPCVD allowed us to produce highly crystalline monolayer graphene. However, by using APCVD we were able to obtain twisted bi-layer graphene as large as ≈100 . All the materials synthesized were carefully analyzed by optical microscopy and Raman spectroscopy. Once we were able to produce ideals bi-layer twisted graphene films; we transferred these materials to a field effect transistor (FET) device. Then we studied the graphene Raman features as a function of the gate voltage. As expected, we observed that the Kohn anomaly was removed by doping graphene by either holes or electrons. Also, the G band phonon lifetime tends to increase as a function of the gate voltage for both monolayer and twisted bi-layer graphene. It seems that large angle twisted bi-layer graphene 20°≤≤30° has a Raman behavior, when back-gated, very similar to monolayer graphene. Which seems to be consistent with the fact that those sample behave as two uncoupled monolayer graphene. Even though, we could prove that our FET device was working properly, we could not obtain significant modification of the Raman band features for twisted bi-layer with small angles (<7,5°).

There is a compelling need to explore different material options as well as device structures to facilitate smooth transistor scaling for higher speed, higher density and lower power. The enormous potential of nanoelectronics, and nanotechnology in general, offers us the possibility of designing devices with added functionality. However, at the same time, the new materials come with their own challenges that need to be overcome. In this work, we have addressed some of these challenges in the context of quasi-2D Silicon, III-V semiconductor and graphene. Bulk Si is the most widely used semiconductor with an indirect bandgap of about 1.1 eV. However, when Si is thinned down to sub-10nm regime, the quasi-2D nature of the system changes the electronic properties of the material significantly due to the strong geometrical confinement. Using a tight-binding study, we show that in addition to the increase in bandgap due to quantization, it is possible to transform the original in direct bandgap to a direct one. The effective masses at different valleys are also shown to vary uniquely in an anisotropic way. This ultra-thin Si, when used as a channel in a double gate MOSFET structure, creates so called “volume in version” which is extensively investigated in this work. It has been found that the both the quantum confinement as well as the gating effect play a significant role in determining the spatial distribution of the charge, which in turn has an important role in the characteristics of transistor. Compound III-V semiconductors, like Inx Ga1-xAs, provide low effective mass and low density of states. This, when coupled with strong confinement in a nanowire channel transistor, leads to the “Ultimate Quantum Capacitance Limit” (UQCL) regime of operation, where only the lowest subband is occupied. In this regime, the channel capacitance is much smaller than the oxide capacitance and hence dominates in the total gate capacitance. It is found that the gate capacitance change qualitatively in the UQCL regime, allowing multi-peak, non-monotonic capacitance-voltage characteristics. It is also shown that in an ideal condition, UQCL provides improved current saturation, on-off ratio and energy-delay product, but a degraded intrinsic gate delay. UQCL shows better immunity towards series resistance effect due to increased channel resistance, but is more prone to interfacial traps. A careful design can provide a better on-off ratio at a given gate delay in UQCL compared to conventional MOSFET scenario. To achieve the full advantages of both FinFET and HEMT in III-V domain, a hybrid structure, called “HFinFET” is proposed which provides excellent on performance like HEMT with good gate control like FinFET. During on state, the carriers in the channel are provided using a delta-doped layer(like HEMT) from the top of a fin-like non-planar channel, and during off state, the gates along the side of the fin(like FinFET) help to pull-off the carriers from the channel. Using an effective mass based coupled Poisson-Schrodinger simulation, the proposed structure is found to outperform the state of the art planar and non-planar MOSFETs. By careful optimization of the gate to source-drain underlap, it is shown that the design window of the device can be increased to meet ITRS projections at similar gate length. In addition, the performance degradation of HFinFET in presence of interface traps has been found to be significantly mitigated by tuning the underlap parameter. Graphene is a popular 2D hexagonal carbon crystal with extraordinary electronic, mechani-cal and chemical properties. However, the zero band gap of grapheme has limited its application in digital electronics. One could create a bandgap in grapheme by making quasi-1D strips, called nanoribbon. However, the bandgap of these nanoribbons depends on the the type of the edge, depending on which, one can obtain either semiconducting or metallic nanoribbon. It has been shown that by the application of an external transverse field along the sides of a nanoribbon, one could not only modulate the magnitude of the bandgap, but also change it from direct to indirect. This could open up interesting possibilities for novel electronic and optoelectronic applications. The asymmetric potential distribution inside the nanoribbon is found to result in such direct to indirect bandgap transition. The corresponding carrier masses are also found to be modulated by the external field, following a transition from a“slow”electron to a“fast” electron and vice-versa. Experimentally, it is difficult to control the bandgap in nanoribbons as precise edge control at nanometer scale is nontrivial. One could also open a bandgap in a bilayer graphene, by the application of vertical electric field, which has raised a lot of interest for digital applications. Using a self-consistent tight binding theory, it is found that, inspite of this bandgap opening, the intrinsic bias dependent electronic structure and the screening effect limit the subthreshold slope of a metal source drain bilayer grapheme transistor at a relatively higher value-much above the Boltzmann limit. This in turn reduces the on-off ratio of the transistor significantly. To overcome this poor on-off ratio problem, a semiconductor source-drain structure has been proposed, where the minority carrier injection from the drain is largely switched off due to the bandgap of the drain. Using a self-consistent Non-Equilibrium Green’s Function(NEGF) approach, the proposed device is found to be extremely promising providing unipolar grapheme devices with large on-off ratio, improved subthreshold slope and better current saturation. At high drain bias, the transport properties of grapheme is extremely intriguing with a number of nontrivial effects. Optical phonons in monolayer grapheme couple with carriers in a much stronger way as compared to a bilayer due to selection rules. However, it is difficult to experimentally probe this through transport measurements in substrate supported grapheme as the surface polar phonons with typical low activation energy dominates the total scattering. However, at large drain field, the carriers obtain sufficient energy to interact with the optical phonons, and create so called ‘hot phonons’ which we have experimentally found to result in a negative differential conductance(NDC). The magnitude of this NDC is found to be much stronger in monolayer than in bilayer, which agrees with theoretical calculations. This NDC has also been shown to be compensated by extra minority carrier injection from drain at large bias resulting in an excellent current saturation through a fundamentally different mechanism as compared to velocity saturation. A transport model has been proposed based on the theory, and the experimental observations are found to be in agreement with the model.

The central theme of the research is an investigation into what motivates FET phase learners to learn. All learners are interested in learning certain things however, learners interests often do not correspond with what teachers are required to teach. Teachers are therefore constantly searching for ways to motivate learners to learn. This challenge is not easy for teachers in a culturally homogenous classroom, but becomes even greater when the classes are comprised of learners from diverse cultural backgrounds. So then how does a teacher motivate learners in general, and more specifically learners from different cultural orientations? This is a difficult question to answer but one that needs to be addressed considering the diversity of cultures found in the South African classroom. In this study an attempt is made to examine what motivates learners to learn, and the influence of culture on the motivation to learn of Further Education and Training (FET) phase learners in a multicultural classroom. Data on these two elements is collected through the use of structured questionnaires and focus group interviews and is analysed in order to answer the research question. / Psychology of Education / M. Ed. (Psychology of Education)

No description available.

The thesis deals with a concept of turning a conventional petrol powered lawn mower to a battery powered solution which is powered by lithium cells. A division to three chapters, comparison, mechanical and electrical, provides fluency of the whole design and further realization. The arrangement of chapters is performed so that the continuity of the thesis is maintained. Calculations of parameters of every motor and transmission with choosing particular devices are just a part of much interesting information which can be found in this thesis. All new components have full documentation except those which were changed during manufacturing. The electrical part explains every part of the schematics in detail. The realization contains difference between preliminary design and further production, manufacturing of the PCB and powering up the motor drives. The last part of the thesis contains temperature measurements of the device at no load.