Neste trabalho analisamos e propomos a utilização de TDM (Time Division Multiplexing) nativo canalizado/estruturado em redes PON (Passive Optical Network) com padrão GPON (Gigabit Passive Optical Network), com ênfase na estrutura de transmissão do legado das redes de telefonia. O objetivo principal é obter um aumento na eficiência de banda transmitida através da fragmentação de sinais E1 sem que seja necessário o uso de técnicas de emulação de circuito (que reduzem a eficiência de banda devido à adição de cabeçalhos). Inicialmente, é descrito o transporte TDM em redes GPON, como efetuado pelos equipamentos comerciais atuais através de duas técnicas: CES - Circuit Emulation Service e TDM nativo não estruturado. Em seguida, é introduzido o conceito de comutação digital visando sua aplicação no transporte TDM nativo estruturado em redes GPON. Nesta etapa, é proposta uma solução para este transporte, é descrito o protocolo utilizado bem como seu funcionamento. Por fim, como prova de conceito, é apresentada uma implementação em HDL (Hardware Description Language) para FPGA (Field Programmable Gate Array). / In this work we analyze and propose the use of native channeled /structured TDM (Time Division Multiplexing) in GPON (Gigabit Passive Optical Network), with emphasis on the structure for transmission of the telephone network legacy. The main target is to achieve an increase in transmitted bandwidth efficiency by fragmenting E1 signals, thus avoiding the use of circuit emulation techniques (which reduce the bandwidth efficiency due to overhead addition). Initially, it is described in TDM transport in GPON networks, as it is performed in present commercial equipment by two techniques: CES - Circuit Emulation Service and Native TDM - unstructured. Next, we introduce the concepts of digital switching aiming its application on the transport of native and structured TDM in GPON. At this stage, we propose a transport solution, describe its protocol and functionalities. Finally, for concept proof, we present an implementation in HDL (Hardware Description Language) meant to FPGA (Field Programmable Gate Array) application.

In der vorliegenden Arbeit werden eine sichere FPGA-Stellwerksplattform und ein Transformationsverfahren entwickelt, mit dem die Schaltungen bestehender Relaisstellwerke in eine FPGA-Logik überführt werden können. Die FPGA-Stellwerksplattform ersetzt die Innenanlage eines Relaisstellwerks. Ihre Schnittstellen entsprechen den bisherigen Schnittstellen am Kabelabschlussgestell und zur Bedien- und Meldeeinrichtung. Damit ist eine einfache Migration bestehender Stellwerke möglich. Das Sicherheitskonzept basiert auf einer zweikanaligen Struktur mit sicherem Vergleicher und zusätzlichen Selbsttests zur schnellen, datenflussunabhängigen Ausfalloffenbarung. Die erreichbare Gefährdungsrate liegt im Bereich von SIL 4 und entspricht damit dem Sicherheitsziel für Stellwerke der Deutschen Bahn. Die Transformation sieht eine Trennung der Stellwerkslogik in Logik- und Leistungsteil vor. Der Logikteil wird auf dem FPGA realisiert. Die im Leistungsteil verbliebenen Kontakte und Überwacherrelais werden durch sichere Stellteile ersetzt. Die logischen Ansteuerbedingungen der Relais werden in Schaltnetze überführt. Die gesteuerten Relais werden durch Instanzen generischer Zustandsmodelle ersetzt. Für jeden verwendeten Relaistyp wurde ein entsprechendes Modell entwickelt, das bei der Transformation als Baustein eingesetzt werden kann. Die generischen Zustandsmodelle berücksichtigen auch die sicherheitsrelevanten konstruktiven Eigenschaften der Relais. So wird bei der Auftrennung einer Schaltung in Logik- und Leistungsteil sichergestellt, dass die in getrennte Schaltungsteile überführten Öffner und Schließer eines Relais nie gleichzeitig geschlossen sein können (Zwangsführung der Kontakte). Dies ist eine Voraussetzung für die Beibehaltung der sicherheitsrelevanten Funktionsbedingungen der Originalschaltung. Das Transformationsverfahren und die implementierten Mechanismen zur Ausfalloffenbarung sind unabhängig von der Anwenderlogik und vom gewählten Schaltkreistyp. Damit kann der generierte VHDL-Code bei Obsoleszenz eines Schaltkreises auch auf andere FPGA-Typen portiert werden. In einer Ressourcenabschätzung wird gezeigt, dass der gewählte Lösungsansatz geeignet ist, die Schaltungen kleinerer Relaisstellwerke vollständig auf einem FPGA zu realisieren. Die Anwendung des vorgestellten Verfahrens wird am Beispiel der Weichengruppe des Stellwerkstyps GS II DR demonstriert. Das Transformationsverfahren ist aber auch für andere Stellwerksbauformen geeignet. Dabei ist es unerheblich, ob diese nach dem tabellarischen Verschlussplanprinzip oder dem Spurplanprinzip arbeiten.

Tile-based many-core architectures are extensively used in modern system-on-chip designs to achieve scalable computing performance with adequate energy efficiency. Heterogeneity is the key element to boost computing performance and keep energy consumption under certain limits for several application domains. However, the steady increase of using many custom heterogeneous tiles leads to an expansion in design and integration cost with limited tiles re-usability. The recent widespread of open-source RISC-V ISA provides the potential to develop modular compute units that can be used for many application domains with high reduction in non-recurring engineering costs. The motivation of this work is to bring design modularity and adaptability features for heterogeneous tile-based many-core architectures by increasing their flexibility to realize different many-core configurations with less design time and costs. In this work, AGILER is proposed as an adaptive tile-base many-core architecture for heterogeneous RISC-V based processors. The proposed architecture consists of modular and adaptable heterogeneous multi-/single-core compute tiles that supports 32-/64-bit RISC-V ISAs with different memory hierarchies. Inter-tile communication is developed based on a scalable network-on-chip architecture to achieve a high degree of system scalability. AGILER supports run-time adaptation through a custom internal reconfiguration manager for dynamic and partial reconfiguration over Xilinx FPGAs. Evaluation results demonstrate that the proposed architecture features a scalable computing performance up to 685 MOPS for 8 x 32-bit tiles and 316 MOPS for 8 x 64-bit tiles with a scalable memory bandwidth up to 7.4 GB/s. AGILER is evaluated on Xilinx Virtex UltrascaleC FPGA with a maximum reconfiguration time of 38.1 ms for a single compute tile.

Thesis (MScEng)--Stellenbosch University, 2011. / ENGLISH ABSTRACT: A well-known problem with FM-CW radar systems is the leakage of transmitter power into the receiver which leads to the making of close-in targets, and can severely limit the system dynamic range performance. This thesis considers two solutions to this radar system problem for a low frequency radar operating in the VHF band. The first method to suppress coupling is using separate transmit and receive antennas designed in such a way as to reduce coupling between them. The second is to design a negative feedback loop as part of the radar receiver where the feedback loop adaptively reduces the amount of transmitter leakage through to the receiver. This project details the realisation of these two solutions. A number of antenna designs are modelled in software and simulated to determine their characteristics of which the transmit-to-receive coupling is the key parameter. As no low coupling configuration could be found a simple configuration is chosen and practical measurements are taken. These antennas are then used in the radar system that is to be built. An FM-CW radar system is designed and simulated using software with a negative feedback loop being designed and implemented into the radar simulation. A practical radar system is then made inclusive of the feedback loop. Measurements are then taken to determine the efficacy of the feedback loop. / AFRIKAANSE OPSOMMING: ʼn Bekende probleem met FM-CW radar stelsels is die lekkasie van versender krag tot in die ontvanger wat lei tot die maak van nabye teikens en kan die stelsel se dinamiese sendbereik steng beperk. Hierdie tesis oorweeg twee oplossings tot hierdie probleem vir ʼn lae frekwensie radar wat in die VHF band werk. Die eerste metode wat na gekyk word om die koppeling te onderdruk is om die twee antennas van die radar stelsel so te ontwerp sodat die hoeveelheid koppeling tussen hulle verminder is. Die tweede is om ʼn negatiewe terugvoerlus as deel van die ontvanger te ontwerp. Hierdie terugvoerlus sal die versender lekkasie sein aanpassend in die ontvanger verminder. In hierdie projek word die realisering van bogenoemde oplossings uiteengeset. ʼn Paar verskillende antenna ontwerpe word gemodelleer in sagteware en word gesimuleer om hul karakteristieke te bepaal. Die belangrikste van hierdie faktore is die versender na ontvanger koppeling. Sienend dat geen ontwerp met ʼn lae genoeg koppeling gevind kon word nie, is ʼn eenvoudige ontwerp gekies en praktiese metings daarvan geneem. Hierdie antennas word dan gebruik in die radar stelsel wat gebou sal word. ʼn FM-CW radar stelsel word ontwerp en gesimuleer in sagteware. Die negatiewe terugvoerlus word ook ontwerp en geïmplementeer in die radar simulasie. ʼn Praktiese radar stelsel word dan gemaak insluitend die terugvoerlus. Metings word dan geneem om die effektiwiteit daarvan te bepaal.

L’utilisation de réseaux de neurones artificiels pour divers types de traitements d’information bio-inspirés est une technique de plus en plus répandue dans le domaine de l’intelligence artificielle. Leur fonctionnement diffère avantageusement de celui des ordinateurs conventionnels en permettant une plus grande parallélisation des calculs, ce qui explique pourquoi autant d’efforts sont déployés afin de réaliser une plate-forme matérielle dédiée à leur simulation. Pour ce projet, une architecture matérielle flexible simulant efficacement un réseau de neurones à décharges est présentée. Celle-ci se distingue des architectures existantes notamment parce qu’elle utilise une approche de simulation à événements discrets et parce qu’elle permet une détection efficace des événements simultanés. Ces caractéristiques en font une plate-forme de choix pour la simulation de réseaux de neurones à décharges de plus de 100 000 neurones où un niveau important de synchronie des décharges neuronales est atteint. Afin d’en démontrer les performances, une application en traitement d’images utilisant cette architecture a été réalisée sur FPGA. Cette application a permis de démontrer que la structure proposée pouvait simuler jusqu’à 2[indice supérieur 17] neurones et traiter des dizaines de millions d’événements par secondes lorsque cadencé à 100 MHz.

Field Programmable Gate Arrays (FPGAs) are programmable logic devices used for the implementation of a wide range of digital systems. In recent years, there has been an increasing interest in design methodologies that allow high-level design descriptions to be automatically implemented in FPGAs. This thesis describes the design and implementation of a novel compilation flow that implements circuits in FPGAs from a streaming programming language. The streaming language supported is called FPGA Brook, and is based on the existing Brook and GPU Brook languages, which target streaming multiprocessors and graphics processing units (GPUs), respectively. A streaming language is suitable for targeting FPGAs because it allows system designers to express applications in a way that exposes parallelism, which can then be exploited through parallel hardware implementation. FPGA Brook supports replication, which allows the system designer to trade-off area for performance, by specifying the parts of an application that should be implemented as multiple hardware units operating in parallel, to achieve desired application throughput. Hardware units are interconnected through FIFO buffers, which effectively utilize the small memory modules available in FPGAs. The FPGA Brook design flow uses a source-to-source compiler, and combines it with a commercial behavioural synthesis tool to generate hardware. The source-to-source compiler was developed as a part of this thesis and includes novel algorithms for implementation of complex reductions in FPGAs. The design flow is fully automated and presents a user-interface similar to traditional software compilers. A suite of benchmark applications was developed in FPGA Brook and implemented using our design flow. Experimental results show that applications implemented using our flow achieve much higher throughput than the Nios II soft processor implemented in the same FPGA device. Comparison to the commercial C2H compiler from Altera shows that while simple applications can be effectively implemented using the C2H compiler, complex applications achieve significantly better throughput when implemented by our system. Performance of many applications implemented using our design flow would scale further if a larger FPGA device were used. The thesis demonstrates that using an automated design flow to implement streaming applications in FPGAs is a promising methodology.

Estimation of depth within an imaged scene can be formulated as a stereo correspondence problem. Software solutions tend to be too slow for high frame rate (i.e. > 30 fps) performance. Hardware solutions can result in marked improvements. This thesis explores one such hardware implementation that generates dense binocular disparity estimates at frame rates of over 200 fps using a dynamic programming formulation (DPML) developed by Cox et. al. A highly parameterizable field programmable gate array implementation of this architecture demonstrates equivalent accuracy while executing at significantly higher frame rates to those of current approaches. Existing hardware implementations for dense disparity estimation often use sum of squared difference, sum of absolute difference or other similar algorithms that typically perform poorly in comparison to DPML. The presented system runs at 248 fps for a resolution of 320 x 240 pixels and disparity range of 128 pixels, a performance of 2.477 billion DPS.

Estimation of depth within an imaged scene can be formulated as a stereo correspondence problem. Software solutions tend to be too slow for high frame rate (i.e. > 30 fps) performance. Hardware solutions can result in marked improvements. This thesis explores one such hardware implementation that generates dense binocular disparity estimates at frame rates of over 200 fps using a dynamic programming formulation (DPML) developed by Cox et. al. A highly parameterizable field programmable gate array implementation of this architecture demonstrates equivalent accuracy while executing at significantly higher frame rates to those of current approaches. Existing hardware implementations for dense disparity estimation often use sum of squared difference, sum of absolute difference or other similar algorithms that typically perform poorly in comparison to DPML. The presented system runs at 248 fps for a resolution of 320 x 240 pixels and disparity range of 128 pixels, a performance of 2.477 billion DPS.

Field Programmable Gate Arrays (FPGAs) are programmable logic devices used for the implementation of a wide range of digital systems. In recent years, there has been an increasing interest in design methodologies that allow high-level design descriptions to be automatically implemented in FPGAs. This thesis describes the design and implementation of a novel compilation flow that implements circuits in FPGAs from a streaming programming language. The streaming language supported is called FPGA Brook, and is based on the existing Brook and GPU Brook languages, which target streaming multiprocessors and graphics processing units (GPUs), respectively. A streaming language is suitable for targeting FPGAs because it allows system designers to express applications in a way that exposes parallelism, which can then be exploited through parallel hardware implementation. FPGA Brook supports replication, which allows the system designer to trade-off area for performance, by specifying the parts of an application that should be implemented as multiple hardware units operating in parallel, to achieve desired application throughput. Hardware units are interconnected through FIFO buffers, which effectively utilize the small memory modules available in FPGAs. The FPGA Brook design flow uses a source-to-source compiler, and combines it with a commercial behavioural synthesis tool to generate hardware. The source-to-source compiler was developed as a part of this thesis and includes novel algorithms for implementation of complex reductions in FPGAs. The design flow is fully automated and presents a user-interface similar to traditional software compilers. A suite of benchmark applications was developed in FPGA Brook and implemented using our design flow. Experimental results show that applications implemented using our flow achieve much higher throughput than the Nios II soft processor implemented in the same FPGA device. Comparison to the commercial C2H compiler from Altera shows that while simple applications can be effectively implemented using the C2H compiler, complex applications achieve significantly better throughput when implemented by our system. Performance of many applications implemented using our design flow would scale further if a larger FPGA device were used. The thesis demonstrates that using an automated design flow to implement streaming applications in FPGAs is a promising methodology.

The goal of the QPACE project is to build a novel cost-efficient massive parallel supercomputer optimized for LQCD (Lattice Quantum Chromodynamics) applications. Unlike previous projects which use custom ASICs, this is accomplished by using the general purpose multi-core CPU PowerXCell 8i processor tightly coupled with a custom network processor implemented on a modern FPGA. The heterogeneous architecture of the PowerXCell 8i processor and its core-independent OS-bypassing access to the custom network hardware and application-oriented 3D torus topology pose interesting challenges for the implementation of the applications. This work will describe and evaluate the implementation possibilities of message passing APIs: the more general MPI, and the more QCD-oriented QMP, and their performance in PPE centric or SPE centric scenarios. These results will then be employed to optimize HPL for the QPACE architecture. Finally, the developed approaches and concepts will be briefly discussed regarding their applicability to heterogeneous node/network architectures as is the case in the "High-speed Network Interface with Collective Operation Support for Cell BE (NICOLL)" project.