Electric drives are crucial components of powertrain of modern vehicles. They need to be controlled effectively to deliver a comfortable and efficient driving experience. The control unit needs to be robust to handle extreme operating conditions and faults in a safe manner. Hardware in Loop (HIL) setups can be used to develop such control units for majority of real-life test cases, without involving physical drives. Typical HIL setup includes the controller (hardware) under test connected to a high fidelity computer model of the controlled system (plant). Thanks to the efficient, inexpensive, consistent and nondestructive nature of HIL setups, they are widely used for research and development in the automotive industry. This thesis focuses on developing such a HIL setup for latest electric drive architecture at Scania CV AB. In this thesis, the plant models are programmed onto a field programmable gate array (FPGA). The HIL setup, plant models and the controller are continuously improved throughout the thesis to achieve higher fidelity and real time replication of the internal permanent magnet synchronous machine under consideration. Software in Loop (SIL) strategy, wherein all components are represented by computer models, is also applied for rapid developments. Several aspects like flux linkage-based and inductance-based machine models, choice of arithmetic, discretization methods, noise, delays, etc. are studied and optimised during the thesis. Validation is conducted for both SIL and HIL setups and above 95% correlation with physical drive’s performance is reported. Stable operation and repeatability of the developed HIL setup ensure that the framework is scalable to be applied to other drives and control units. / Elektriska drivenheter är centrala komponenter i drivlinan hos moderna elektriska fordon. Drivenheterna måste regleras effektivt för att ge en bekväm och effektiv körupplevelse. Regulatorn måste vara robust för att säkert hantera extrema driftsförhållanden och fel. Hardware in Loop (HIL) simuleringar kan användas för att utveckla sådana regulatorer för de flesta verkliga testfall, utan att involvera de fysiska komponenterna. En typisk HIL-installation inkluderar styrenheten (hårdvaran) som testas ansluten till en datormodell av det kontrollerade systemet (anläggningen). På grund av den effektiva, billiga, konsekventa och oförstörande naturen hos HIL simuleringar används de i stor utsträckning för FoU inom fordonsindustrin. Detta examensarbete fokuserar på att utveckla en sådan HIL-modell för en elektrisk drivlina hos Scania CV AB. I detta examensarbete är anläggningsmodellerna programmerade på en programmerbar integrerad krets. HIL-inställningen, anläggningsmodellerna och styrenheten förbättras kontinuerligt under hela examensarbetet för att uppnå högre kvalitet och realtidsreplikering av den permanentmagnetiserade synkronmaskin som övervägs. En Software in Loop (SIL) strategi, där alla komponenter representeras av datormodeller, tillämpas också för snabb utveckling. Flera aspekter såsom flödesbaserade och induktansbaserade maskinmodeller, val av aritmetik, diskretiserings metoder, brus, fördröjningar etc. studeras och optimeras. Validering utförs för både SIL- och HIL-inställningar och över 95% korrelation med fysiska enhetsprestanda erhålls. Stabil drift och repeterbarhet av den utvecklade HIL-kretsen säkerställer att ramverket är skalbart för att kunna appliceras på andra enheter och regulatorer.

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The complexity of the software behind autonomous systems is rapidly growing, as are the applications of what they can do. It is not unusual for the lines of code to reach the millions, which adds to the verification challenge. The machine learning algorithms involved are often "black boxes" where the precise workings are not known by the developer applying them, and their behavior is undefined when encountering an untrained scenario. With so much code, the possibility of bugs or malicious code is considerable. An approach is developed to monitor and possibly override the behavior of autonomous systems independent of the software controlling them. Application-isolated safety monitors are implemented in configurable hardware to ensure that the behavior of an autonomous system is limited to what is intended. The sensor inputs may be shared with the software, but the output from the monitors is only engaged when the system violates its prescribed behavior. For each specific rule the system is expected to follow, a monitor is present processing the relevant sensor information. The behavior is defined in linear temporal logic (LTL) and the associated monitors are implemented in a field programmable gate array (FPGA). An off-the-shelf drone is used to demonstrate the effectiveness of the monitors without any physical modifications to the drone. Upon detection of a violation, appropriate corrective actions are persistently enforced on the autonomous system. / Master of Science / Autonomous systems are surprisingly vulnerable, not just from malicious hackers, but from design errors and oversights. The lines of code required can quickly climb into the millions, and the artificial decision algorithms can be inscrutable and fully dependent upon the information they are trained on. These factors cause the verification of the core software running our autonomous cars, drones, and everything else to be prohibitively difficult by traditional means. Independent safety monitors are implemented to provide internal oversight for these autonomous systems. A semi-automatic design process efficiently creates error-free monitors from safety rules drones need to follow. These monitors remain separate and isolated from the software typically controlling the system, but use the same sensor information. They are embedded in the circuitry and act as their own small, task-specific processors watching to make sure a particular rule is not violated; otherwise, they take control of the system and force corrective behavior. The monitors are added to a consumer off-the-shelf (COTS) drone to demonstrate their effectiveness. For every rule monitored, an override is triggered when they are violated. Their effectiveness depends on reliable sensor information as with any electronic component, and the completeness of the rules detailing these monitors.

With the emergence of Industry 4.0, there is a pronounced emphasis on the necessity for enhanced flexibility in assembly processes. In the domain of bolt-tightening, this transition is evident. Tools are now required to navigate a variety of bolts and unpredictable tightening methodologies. Each bolt, possessing distinct tightening parameters, necessitates a specific sequence to prevent issues like bolt cross-talk or unbalanced force. This thesis introduces an approach that integrates advanced computing techniques with machine learning to address these challenges in the tightening areas. The primary objective is to offer edge computation for bolt detection and tightening tools' precise localization. It is realized by leveraging visual-inertial data, all encapsulated within a System-on-Chip (SoC) Field Programmable Gate Array (FPGA). The chosen approach combines visual information and motion detection, enabling tools to quickly and precisely do the localization of the tool. All the computing is done inside the SoC FPGA. The key element for identifying different bolts is the YOLOv3-Tiny-3L model, run using the Deep-learning Processor Unit (DPU) that is implemented in the FPGA. In parallel, the thesis employs the Error-State Extended Kalman Filter (ESEKF) algorithm to fuse the visual and motion data effectively. The ESEKF is accelerated via a full implementation in Register Transfer Level (RTL) in the FPGA fabric. We examined the empirical outcomes and found that the visual-inertial localization exhibited a Root Mean Square Error (RMSE) position of 39.69 mm and a standard deviation of 9.9 mm. The precision in orientation determination yields a mean error of 4.8 degrees, offset by a standard deviation of 5.39 degrees. Notably, the entire computational process, from the initial bolt detection to its final localization, is executed in 113.1 milliseconds. This thesis articulates the feasibility of executing bolt detection and visual-inertial localization using edge computing within the SoC FPGA framework. The computation trajectory is significantly streamlined by harnessing the adaptability of programmable logic within the FPGA. This evolution signifies a step towards realizing a more adaptable and error-resistant bolt-tightening procedure in industrial areas. / Med framväxten av Industry 4.0, finns det en uttalad betoning på nödvändigheten av ökad flexibilitet i monteringsprocesser. Inom området bultåtdragning är denna övergång tydlig. Verktyg krävs nu för att navigera i en mängd olika bultar och oförutsägbara åtdragningsmetoder. Varje bult, som har distinkta åtdragningsparametrar, kräver en specifik sekvens för att förhindra problem som bultöverhörning eller obalanserad kraft. Detta examensarbete introducerar ett tillvägagångssätt som integrerar avancerade datortekniker med maskininlärning för att hantera dessa utmaningar i skärpningsområdena. Det primära målet är att erbjuda kantberäkning för bultdetektering och åtdragningsverktygs exakta lokalisering. Det realiseras genom att utnyttja visuella tröghetsdata, allt inkapslat i en System-on-Chip (SoC) Field Programmable Gate Array (FPGA). Det valda tillvägagångssättet kombinerar visuell information och rörelsedetektering, vilket gör det möjligt för verktyg att snabbt och exakt lokalisera verktyget. All beräkning sker inuti SoC FPGA. Nyckelelementet för att identifiera olika bultar är YOLOv3-Tiny-3L-modellen, som körs med hjälp av Deep-learning Processor Unit (DPU) som är implementerad i FPGA. Parallellt använder avhandlingen algoritmen Error-State Extended Kalman Filter (ESEKF) för att effektivt sammansmälta visuella data och rörelsedata. ESEKF accelereras via en fullständig implementering i Register Transfer Level (RTL) i FPGA-strukturen. Vi undersökte de empiriska resultaten och fann att den visuella tröghetslokaliseringen uppvisade en Root Mean Square Error (RMSE) position på 39,69 mm och en standardavvikelse på 9,9 mm. Precisionen i orienteringsbestämningen ger ett medelfel på 4,8 grader, kompenserat av en standardavvikelse på 5,39 grader. Noterbart är att hela beräkningsprocessen, från den första bultdetekteringen till dess slutliga lokalisering, exekveras på 113,1 millisekunder. Denna avhandling artikulerar möjligheten att utföra bultdetektering och visuell tröghetslokalisering med hjälp av kantberäkning inom SoC FPGA-ramverket. Beräkningsbanan är avsevärt effektiviserad genom att utnyttja anpassningsförmågan hos programmerbar logik inom FPGA. Denna utveckling innebär ett steg mot att förverkliga en mer anpassningsbar och felbeständig skruvdragningsprocedur i industriområden.

L’utilisation des alimentations à découpage (SMPSs : switched mode power supplies) est à présent largement répandue dans des systèmes embarqués en raison de leur rendement. Les exigences technologiques de ces systèmes nécessitent simultanément une très bonne régulation de tension et une forte compacité des composants. SEPIC (Single-Ended Primary Inductor Converter) est un convertisseur à découpage DC/DC qui possède plusieurs avantages par rapport à d’autres convertisseurs de structure classique. Du fait de son ordre élevé et de sa forte non linéarité, il reste encore peu exploité. L’objectif de ce travail est d’une part le développement des stratégies de commande performantes pour un convertisseur SEPIC et d’autre part l’implémentation efficace des algorithmes de commande développés pour des applications embarquées (FPGA, ASIC) où les contraintes de surface silicium et le facteur de réduction des pertes sont importantes. Pour ce faire, deux commandes non linéaires et deux observateurs augmentés (observateurs d’état et de charge) sont exploités : une commande et un observateur fondés sur le principe de mode de glissement, une commande prédictive et un observateur de Kalman étendu. L’implémentation des deux lois de commande et l’observateur de Kalman étendu sont implémentés sur FPGA. Une modulation de largeur d’impulsion (MLI) numérique à 11-bit de résolution a été développée en associant une technique de modulation Δ-Σ de 4-bit, un DCM (Digital Clock Management) segmenté et déphasé de 4-bit, et un compteur-comparateur de 3-bit. L’ensemble des approches proposées sont validées expérimentalement et constitue une bonne base pour l’intégration des convertisseurs à découpage dans les alimentations embarquées. / The use of SMPS (Switched mode power supply) in embedded systems is continuously increasing. The technological requirements of these systems include simultaneously a very good voltage regulation and a strong compactness of components. SEPIC ( Single-Ended Primary Inductor Converter) is a DC/DC switching converter which possesses several advantages with regard to the other classical converters. Due to the difficulty in control of its 4th-order and non linear property, it is still not well-exploited. The objective of this work is the development of successful strategies of control for a SEPIC converter on one hand and on the other hand the effective implementation of the control algorithm developed for embedded applications (FPGA, ASIC) where the constraints of Silicon surface and the loss reduction factor are important. To do it, two non linear controls and two observers of states and load have been studied: a control and an observer based on the principle of sliding mode, a deadbeat predictive control and an Extended Kalman observer. The implementation of both control laws and the Extended Kalman observer are implemented in FPGA. An 11-bit digital PWM has been developed by combining a 4-bit Δ-Σ modulation, a 4-bit segmented DCM (Digital Clock Management) phase-shift and a 3-bit counter-comparator. All the proposed approaches are experimentally validated and constitute a good base for the integration of embedded switching mode converters

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / This paper describes a 300 Mega Bit Per Second (MBPS) Front End Processor (FEP) prototype completed in early 1993. The FEP implements a patent pending parallel frame synchronizer (frame sync) design in 12 Actel 1240 Field Programmable Gate Arrays (FPGA's). The FEP also provides (255,223) Reed-Solomon (RS) decoding and a High Performance Parallel Interface (HIPPI) output interface. The recent introduction of large RAM based FPGA's allows greater high speed data processing integration and flexibility to be achieved. A proposed FEP implementation based on Altera 10K50 FPGA's is described. This design can be implemented on a single slot 6U VME module, and includes a PCI Mezzanine Card (PMC) for a commercial Fibre Channel or Asynchronous Transfer Mode (ATM) output interface module. Concepts for implementation of (255,223) RS and Landsat 7 Bose-Chaudhuri-Hocquenghem (BCH) decoding in FPGA's are also presented. The paper concludes with a summary of the advantages of high speed data processing in FPGA's over Application Specific Integrated Circuit (ASIC) based approaches. Other potential data processing applications are also discussed.

In More Electric Aircraft, different power system activities are attributed to electrical means such as the start-up of the main engine. In this context, the study of the sensorless control of the Brushless Synchronous Starter Generator (BSSG) that is used to electrically start the main engine is revealed to be a very interesting issue. For long time, the elimination of the mechanical sensor was highly recommended for reliability, cost, weight, integration issues.Hence, this work aims to transpose the results obtained in the research area to an avionic testbench. It presents an adaptive sensorless technique to use when electrically starting the main engine of the aircraft. This is achieved by elaborating three different methods selected depending on the speed of the machine and based on the :- injection of a high frequency signal- use of the back-emf of the Permanent Magnet Generator (PMG)- use of the extended Kalman Filter EKFIn this work, it is shown that the …first method gives good position estimation results from standstill up to 8% of the rated speed. Then, the back-emfs of the PMG are used to detect the position of the BSSG when the speed exceeds the 8% of the rated speed. Good results are observed with this method at medium and high speed.For redundancy reasons, the EKF was also used in this work. Thus, the estimated position can be delivered via two different estimation algorithms in medium and high speed region.The implementation of the algorithm was achieved on an FPGA board since the latter can ensure a very tiny execution time. The fastness of the treatment ensures quasi-instantaneous position estimation and does not practically introduce any phase lag in the position estimation. / Aujourd'hui, l'aviation est en train de vivre des évolutions technologiques concernant surtout l'attribution de différentes fonctionnalités aux équipements électriques et ceci au détriment d'équipements hydrauliques et mécaniques assurant les mêmes fonctionnalités.Dans le cadre de l'avion plus électrique, le démarrage électrique sans capteurs mécaniques de la turbine de l'avion préoccupe les avionneurs de nos jours. Les problèmes introduits par ce capteur ont été identifiés : problèmes de coût et de poids, problèmes de fiabilité et d'intégration.Ce travail présente alors une commande sans capteurs pour la machine synchrone à trois étages à utiliser durant le démarrage électrique de l'avion. Ceci est réalisé avec trois méthodes de détection de la position selon la vitesse de rotation, basées sur :- l'injection d'un signal à haute fréquence- l'utilisation d'un filtre de Kalman étendu FKE- les fém. du PMG (Permanent Magnet Generator) La première méthode donne de bons résultats d'estimation depuis l'arrêt jusqu'à 8% de la vitesse nominale de la machine. Au-delà de cette vitesse, es valeurs des fém. du PMG deviennent assez élevées pour être utilisées dans l'estimation de la position. De bons résultats sont obtenus à moyenne et haute vitesse.Pour des questions de redondance, le FKE est aussi utilisé. Ainsi, la position estimée peut être fournie par l'un des deux algorithmes à moyenne et haute vitesse.L'implémentation de ces algorithmes est réalisée via une carte FPGA étant donné que celui-ci garantit un temps d'exécution. La rapidité de traitement garantit une estimation de la position quasi-instantanée et donc n'introduit pratiquement pas des retards dans l'estimation.

Fixed Broadband Wireless Access (FBWA) is a technology aimed at providing high-speed wireless Internet access, over a wide area, from devices such as personal computers and laptops. FBWA channels are defined in the range of 1-20 MHz which makes the RF front end (RFE) design extremely challenging. In its pursuit to standardize the Broadband Wireless Access (BWA) technologies, IEEE working group 802.16 for Broadband Wireless Access has released the fixed BWA standard IEEE 802.16 – 2004 in 2004. This standard is further backed by a consortium, of leading wireless vendors, chip manufacturers and service providers, officially known as Wireless Interoperability for Microwave Access (WiMAX). In general, any wireless base station (BS), supporting a number of contiguous Frequency Division Multiplexed (FDM) channels has to incorporate an RF front end (RFE) for each RF channel. The precise job of the RFE is to filter the desired channel from a group of RF channels, digitize it and present it to the subsequent baseband system at the proper sampling rate. The system essentially has a bandpass filter (BPF) tuned to the channel of interest followed by a multiplier which brings the channel to a suitable intermediate frequency (IF). The IF output is digitized by an ADC and then brought to the baseband by an appropriate digital multiplier. The baseband samples, thus generated, are at the ADC sampling rate which is significantly higher than the target sampling rate, which is defined by the wireless protocol in use. As a result a sampling rate conversion (SRC) is performed on these baseband samples to bring the channel back to the target sampling rate. Since the input sampling rate need not be an integer multiple of the target sampling rate, Fractional SRC (FSRC) is required in most of the cases. Instead of using a separate ADC and IF section for each individual channels, most systems use a common IF section, followed by a wideband ADC, which operates over a wide frequency band containing a group of contiguous FDM channels. In this case a channelizer is employed to digitally extract the individual channels from the digital IF samples. We formally call this system a receiver channelizer. Such an implementation presents considerable challenge in terms of the computational requirement and of course the cost of the BS. The computational complexity further goes up for FBWA system where channel bandwidth is in the order of several MHz. Though such a system has been analyzed for narrow band wireless systems like GSM, to the best of our knowledge no analysis seems to have been carried out for a wideband system such as WiMAX. In this work, we focus on design of a receiver channelizer for WiMAX BS, which can simultaneously extract a group of contiguous FDM RF channels supported by the BS. The main goal is to obtain a simple, low cost channelizer architecture, which can be implemented in an FPGA. There are a number of techniques available in the literature, from Direct Digital Conversion to Polyphase FFT Filter Banks (PFFB), which can do the job of channelization. But each of them operates with certain constraints and, as a result, suits best to a particular application. Further all of these techniques are generic in nature, in the sense that their structure is independent of any particular standard. With regard to computational requirement of these techniques, PFFB is the best, with respect to the number of complex multiplications required for its implementation. But it needs two very stringent conditions to be satisfied, viz. the number of channels to be extracted is equal to the decimation factor and the sampling rate is a power of 2 times baseband bandwidth. Clearly these conditions may not be satisfied by different wireless communication standards, and in fact, this is not satisfied by the WiMAX standard. This gives us the motivation to analyze the receiver channelizer for WiMAX BS and to find an efficient and low cost architecture of the same. We demonstrate that even though the conditions required by PFFB are not satisfied by the WiMAX standard, we can modify the overall architecture to include the PFFB structure. This is achieved by dividing the receiver channelizer into two blocks. The first block uses the PFFB structure to separate the desired number of channels from the input samples. This process also achieves an integer SRC by a factor that is equal to the number of channels being extracted. This block generates baseband outputs whose sampling rates are related to their target sampling rate by a fractional multiplication factor. In order to bring the channels to their target sampling rate, each output from the PFFB block is fed to a FSRC block, whose job is to use an efficient FSRC algorithm to generate the samples at the target sampling rate. We show that the computational complexity, as compared to the direct implementation, is reduced by a factor, which is approximately equal to the square of the number of channels. After mathematically formulating the receiver channelizer for WiMAX BS, we perform the simulation of the system using a software tool. There are two basic motives behind the simulation of the system which has a mathematical model. Firstly, the software simulation will give an idea whether the designed system is physically realizable. Secondly, this will help in designing the logic for different blocks of the system. Once these individual blocks are simulated and tested, they can be smoothly ported onto an FPGA. For simulation purpose, we parameterize the receiver channelizer in such a way that it can be reconfigured for different ADC sampling rates and IF frequencies, by changing the input clock rate. The system is also reconfigurable in terms of the supported channel bandwidth. This is achieved by storing all the filter coefficients pertaining to each channel type, and loading the required coefficients into the computational engine. Using this methodology we simulate the system for three different IF frequencies (and the corresponding ADC sampling rates) and three different channel types, thus leading to nine different system configurations. The simulation results are in agreement with the mathematical model of the system. Further, we also discuss some important implementation issues for the reconfigurable receiver channelizer. We estimate the memory requirement for implementing the system in an FPGA. The implementation delay is estimated in terms of number of samples. The thesis is organized in five chapters. Chapter 1 gives a brief introduction about the WiMAX system and different existing channelization architecture followed by the outline of the proposed receiver channelizer. In chapter 2, we analyze the proposed receiver channelizer for WiMAX BS and evaluate its computational requirements. Chapter 3 outlines the procedure to generate the WiMAX test signal and specification of the all the filters used in the system. It also lists the simulation parameters and records the results of the simulation. Chapter 4 presents the details of a possible FPGA implementation. We present the concluding remarks and future research directions in the final chapter.

Partial dynamic reconfiguration of FPGAs has attracted high attention from both academia and industry in recent years. With this technique, the functionality of the programmable devices can be adapted at runtime to changing requirements. The approach allows designers to use FPGAs more efficiently: E. g. FPGA resources can be time-shared between different functions and the functions itself can be adapted to changing workloads at runtime. Thus partial dynamic reconfiguration enables a unique combination of software-like flexibility and hardware-like performance. Still there exists no common understanding on how to assess the overhead introduced by partial dynamic reconfiguration. This dissertation presents a new cost model for both the runtime and the memory overhead that results from partial dynamic reconfiguration. It is shown how the model can be incorporated into all stages of the design optimization for reconfigurable hardware. In particular digital circuits can be mapped onto FPGAs such that only small fractions of the hardware must be reconfigured at runtime, which saves time, memory, and energy. The design optimization is most efficient if it is applied during high level synthesis. This book describes how the cost model has been integrated into a new high level synthesis tool. The tool allows the designer to trade-off FPGA resource use versus reconfiguration overhead. It is shown that partial reconfiguration causes only small overhead if the design is optimized with regard to reconfiguration cost. A wide range of experimental results is provided that demonstrates the benefits of the applied method. / Partielle dynamische Rekonfiguration von FPGAs hat in den letzten Jahren große Aufmerksamkeit von Wissenschaft und Industrie auf sich gezogen. Die Technik erlaubt es, die Funktionalität von progammierbaren Bausteinen zur Laufzeit an veränderte Anforderungen anzupassen. Dynamische Rekonfiguration erlaubt es Entwicklern, FPGAs effizienter einzusetzen: z.B. können Ressourcen für verschiedene Funktionen wiederverwendet werden und die Funktionen selbst können zur Laufzeit an veränderte Verarbeitungsschritte angepasst werden. Insgesamt erlaubt partielle dynamische Rekonfiguration eine einzigartige Kombination von software-artiger Flexibilität und hardware-artiger Leistungsfähigkeit. Bis heute gibt es keine Übereinkunft darüber, wie der zusätzliche Aufwand, der durch partielle dynamische Rekonfiguration verursacht wird, zu bewerten ist. Diese Dissertation führt ein neues Kostenmodell für Laufzeit und Speicherbedarf ein, welche durch partielle dynamische Rekonfiguration verursacht wird. Es wird aufgezeigt, wie das Modell in alle Ebenen der Entwurfsoptimierung für rekonfigurierbare Hardware einbezogen werden kann. Insbesondere wird gezeigt, wie digitale Schaltungen derart auf FPGAs abgebildet werden können, sodass nur wenig Ressourcen der Hardware zur Laufzeit rekonfiguriert werden müssen. Dadurch kann Zeit, Speicher und Energie eingespart werden. Die Entwurfsoptimierung ist am effektivsten, wenn sie auf der Ebene der High-Level-Synthese angewendet wird. Diese Arbeit beschreibt, wie das Kostenmodell in ein neuartiges Werkzeug für die High-Level-Synthese integriert wurde. Das Werkzeug erlaubt es, beim Entwurf die Nutzung von FPGA-Ressourcen gegen den Rekonfigurationsaufwand abzuwägen. Es wird gezeigt, dass partielle Rekonfiguration nur wenig Kosten verursacht, wenn der Entwurf bezüglich Rekonfigurationskosten optimiert wird. Eine Anzahl von Beispielen und experimentellen Ergebnissen belegt die Vorteile der angewendeten Methodik.

The use of SMPS (Switched mode power supply) in embedded systems is continuously increasing. The technological requirements of these systems include simultaneously a very good voltage regulation and a strong compactness of components. SEPIC ( Single-Ended Primary Inductor Converter) is a DC/DC switching converter which possesses several advantages with regard to the other classical converters. Due to the difficulty in control of its 4th-order and non linear property, it is still not well-exploited. The objective of this work is the development of successful strategies of control for a SEPIC converter on one hand and on the other hand the effective implementation of the control algorithm developed for embedded applications (FPGA, ASIC) where the constraints of Silicon surface and the loss reduction factor are important. To do it, two non linear controls and two observers of states and load have been studied: a control and an observer based on the principle of sliding mode, a deadbeat predictive control and an Extended Kalman observer. The implementation of both control laws and the Extended Kalman observer are implemented in FPGA. An 11-bit digital PWM has been developed by combining a 4-bit Δ-Σ modulation, a 4-bit segmented DCM (Digital Clock Management) phase-shift and a 3-bit counter-comparator. All the proposed approaches are experimentally validated and constitute a good base for the integration of embedded switching mode converters