Ziel der Arbeit ist die anschauliche Demonstration der Leistungsfähigkeit von Hardware- Systemen zur Regelung instabiler Systeme am Beispiel des Inversen Pendels. Dabei handelt es sich um das Balancieren eines Stabes, einem Standard-Problem der Regelungstechnik. Es wird die Konzeption und Implementierung einer Hardware-Regelung in einem FPGA-Prototypenboard zur Realisierung dieser Aufgabe beschrieben. Die Regelung basiert mit LQR-Entwurf und Kalman-Filter auf klassischen Methoden der Regelungstechnik. Zur Demonstration der Regelung wurde ein mechanischer Aufbau vorgenommen, an dem die Funktionsfähigkeit des Inversen Pendels praktisch gezeigt wurde.

Die Dissertationsschrift stellt eine Methodik und die Infrastruktur zur Entwicklung von dynamisch verteilbaren Anwendungen für heterogene Computersysteme vor. Diese Computersysteme besitzen vielfältige Rechenwerke, die Berechnungen in den Domänen Software und Hardware realisieren. Als erster Schritt wird ein übergreifendes und integriertes Vorgehen für den Anwendungsentwurf auf Basis eines abstrakten “Single-Source” Ansatzes entwickelt. Durch die Virtualisierung der Rechenwerke wird die preemptive Verteilung der Anwendungen auch über die Domänengrenzen möglich. Die Anwendungsentwicklung für diese Computersysteme bedarf einer durchgehend automatisierten Entwurfsunterstützung. In der Arbeit wird der dazu vorgeschlagene Ansatz formalisiert und eine neuartige Unterbrechungspunktsynthese entwickelt, die ein hinsichtlich Zeit und Fläche optimiertes, präemptives Verhalten für beliebige Anwendungsbeschreibungen generiert. Das Verfahren wird beispielhaft implementiert und mittels einer FPGA- Prototypenplattform mit Linux-basierter Laufzeitumgebung anhand dreier Fallbeispiele unterschiedlicher Komplexität validiert und evaluiert. / This thesis introduces a methodology and infrastructure for the development of dynamically distributable applications on heterogeneous computing systems. Such systems execute computations using resources from both the hardware and the software domain. An integrated approach based on an abstract single-source design entry is developed that allows preemptive partitioning through virtualization of computing resources across the boundaries of differing computational domains. Application design for heterogeneous computing systems is a complex task that demands aid by electronic design automation tools. This work provides a novel synthesis approach for breakpoints that generates preemptive behaviour for arbitrary applications. The breakpoint scheme is computed for a minimal additional resource utilization and given timing constraints. The approach is implemented on an FPGA prototyping platform driven by a Linux based runtime environment. Evaluation and validation of the approach have been carried out using three different application examples.

Submitted by Gilvanedja Silva (gilvanedja@biblioteca.ufpb.br) on 2018-03-22T20:42:08Z No. of bitstreams: 1 arquivototal.pdf: 11929036 bytes, checksum: e796f3e04cbf0cf6da3fa9648d4f9270 (MD5) / Made available in DSpace on 2018-03-22T20:42:09Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 11929036 bytes, checksum: e796f3e04cbf0cf6da3fa9648d4f9270 (MD5) Previous issue date: 2017-05-25 / This work presents a technique using carrier-based pulse width modulation (PWM) applied to single-phase asymmetrical multilevel inverters with diodes clamped, aiming to increase the amount of output voltage levels to improve signal quality, reducing the total harmonic distortion rate (THD). The technique was used in inverters of three, four and five levels per arm, providing an output signal with seven, thirteen and nineteen levels respectively, presenting two, six and ten levels higher than the equivalent symmetrical multilevel inverters. The technique was described with a set of equations and procedures that can be generalized for inverters of any number of levels. To verify the operation, simulations were performed using the PSIM program and an experimental assembly of an asymmetrical multilevel inverter of three levels was performed, using a field programmable gate array device (FPGA) in the implementation of the PWM modulator. Finally, the simulation and experimental results that prove the effectiveness of the modulation strategy employed in this work are presented and compared / Este trabalho apresenta uma técnica utilizando a modulação por largura de pulso (PWM) baseada em portadora, aplicada aos inversores multiníveis monofásicos assimétricos com diodos de grampeamento, com o objetivo de elevar a quantidade de níveis na tensão de saída, para melhorar a qualidade do sinal, reduzindo a taxa de distorção harmônica total (THD). A técnica foi empregada em inversores de três, quatro e cinco níveis por braço, fornecendo um sinal de saída com sete, treze e dezenove níveis respectivamente, apresentando dois, seis e dez níveis a mais que os inversores multiníveis simétricos equivalentes. A técnica foi descrita com um conjunto de equações e procedimentos que pode ser generalizada para inversores de qualquer número de níveis. Para comprovar o funcionamento, foram realizadas simulações utilizando o programa PSIM e efetuada montagem experimental de uma inversor multinível assimétrico de três níveis, utilizando na implementação do modulador PWM um dispositivo em matriz de porta programável em campo (FPGA). Por fim, são apresentados e comparados os resultados de simulações e experimentais que comprovam a eficácia da estratégia de modulação empregada neste trabalho

The development of dedicated cryptography systems for applications requiring low cost and consumption has been the current focus of research. This work addresses the design and performance analysis of cryptographic algorithms AES-128 (NIST standard), PRESENT-80 and CLEFIA-128 (ISO/IEC standard for Lightweight Cryptography), im-plemented in FPGA (Basys 3 Artix-7 - 28 nm technology) using VHDL. Performance metrics were analyzed and compared: occupied area in the FPGA, throughput (Mbps), efficiency (Mbps/slice), energy efficiency (Ws/bit) and current consumption. The metrics were obtained through the synthesis and implementation tool in FPGA, Vivado Design Suites (Xilinx), and by means of a current measurement prototype, which uses the Ada-fruit INA219 sensor board (Sensor from Texas Instruments) and microcontroller Arduino Uno (Atmega328 - Atmel). We also analyzed the graphical representation of current con-sumption through the mathematical model based on the Welch periodogram, applied on the current consumption variables during the data encryption process. The results show current curves that facilitate the identification and comparison of the algorithms. The data of area consumption, processing speed and efficiency in the FPGA obtained satisfactory performance in comparison with other implementations existing in the literature, besides providing relevant information to choose an algorithm of encryption. / O desenvolvimento de sistemas dedicados de criptografia, para aplicações que exigem baixo custo e consumo tem sido enfoque atual de pesquisas. Este trabalho aborda o projeto e análise de desempenho dos algoritmos de criptografia AES-128 (padrão NIST), PRESENT-80 e CLEFIA-128 (padrão ISO/IEC para Criptografia Leve), implementados em FPGA (Basys 3 Artix-7 – tecnologia de 28 nm), utilizando VHDL. Foram analisadas e comparadas as métricas de desempenho: área ocupada no FPGA, velocidade de proces-samento (Mbps), eficiência (Mbps/slice), eficiência energética (Ws/bit) e consumo de corrente. As métricas foram obtidas através da ferramenta de síntese e implementação em FPGA, Vivado Design Suites (Xilinx), e por meio de um protótipo de medição de corrente, que utiliza a placa sensor Adafruit INA219 (sensor da Texas Instruments) e microcontro-lador Arduino Uno (Atmega328 - Atmel). Foram analisadas também a representação grá-fica do consumo de corrente através do modelo matemático baseado no periodograma de Welch, aplicado sobre as variáveis de consumo de corrente durante o processo de encrip-tação de dados. Os resultados mostram curvas de corrente que facilitam a identificação e comparação dos algoritmos. Os dados de consumo de área, velocidade processamento e eficiência no FPGA obtiveram desempenho satisfatório, em comparação com outras im-plementações existentes na literatura, além de fornecer informação relevante para escolha de um algoritmo de criptografia.

Submitted by Renata Lopes (renatasil82@gmail.com) on 2016-05-17T12:37:21Z No. of bitstreams: 1 diogofernandes.pdf: 2723080 bytes, checksum: 27ac16e618618f1cb4c4dc6394956f80 (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2016-06-28T14:08:15Z (GMT) No. of bitstreams: 1 diogofernandes.pdf: 2723080 bytes, checksum: 27ac16e618618f1cb4c4dc6394956f80 (MD5) / Made available in DSpace on 2016-06-28T14:08:15Z (GMT). No. of bitstreams: 1 diogofernandes.pdf: 2723080 bytes, checksum: 27ac16e618618f1cb4c4dc6394956f80 (MD5) Previous issue date: 2015-08-31 / CNPq - Conselho Nacional de Desenvolvimento Científico e Tecnológico / Este trabalho tem como objetivo apresentar técnicas com complexidade computacional reduzida para implementação em hardware do modulador de amplitude em quadratura M-ária (M-ary quadrature amplitude modulation - M-QAM) de elevada ordem, que pode ser viável para sistemas banda larga. As técnicas propostas abrangem as constelações M-QAM quadradas e cruzadas (número par e ímpar de bits), a regra de decisão abrupta (hard decison rule), derivação de constelações M-QAM de baixa ordem das de elevada ordem. A análise de desempenho em termos de taxa de bits errados (bit error rate - BER) é realizada quando os símbolos M-QAM são corrompidos por ruído Gaussiano branco aditivo (additive white Gaussian noise - AWGN) e ruído Gaussiano impulsivo aditivo (additive impulsive Gaussian noise - AIGN). Os resultados de desempenho da taxa de bits errados mostram que a perda de desempenho das técnicas propostas é, em média, inferior a 1 dB, o que é um resultado surpreendente. Além disso, a implementação das técnicas propostas em arranjo de portas programáveis em campo (field programmable gate array - FPGA) é descrita e analisada. Os resultados obtidos com as implementações em dispositivo FPGA mostram que as técnicas propostas podem reduzir consideravelmente a utilização de recursos de hardware se comparadas com as técnicas presentes na literatura. Uma melhoria notável em termos de redução da utilização de recursos de hardware é conseguida através da utilização da técnica de modulação M-QAM genérica em comparação com a técnica de regra de decisão heurística (heuristic decision rule - HDR) aprimorada e uma técnica previamente concebida, a tà c cnica HDR. Com base nas análises apresentadas, a técnica HDR aprimorada é menos complexa do que a técnica HDR. Finalmente, os resultados numéricos mostram que a técnica de modulação M-QAM genérica pode ser oito vezes mais rápida do que as outras duas técnicas apresentadas, quando um grande número de símbolos M-QAM (p. ex., > 1000) são transmitidos consecutivamente. / This work aims at introducing techniques with reduced computational complexity for hardware implementation of high order M-ary quadrature amplitude modulation (MQAM) which may be feasible for broadband communication systems. The proposed techniques cover both square and cross M-QAM constellations (even and odd number of bits), hard decision rule, derivation of low-order M-QAM constellations from high order ones. Performance analyses, in terms of bit error rate (BER) is carried out when the M-QAM symbols are corrupted by either additive white Gaussian noise (AWGN) or additive impulsive Gaussian noise (AIGN). The bit error rate performance results show that the performance loss of the proposed techniques is, on average, less than 1 dB, which is a remarkable result. Additionally, the implementation of the proposed techniques in field programmable gate array (FPGA) device is described and outlined. The results based on FPGA show that the proposed techniques can considerably reduce hardware resource utilization. A remarkable improvement in terms of hardware resource utilization reduction is achieved by using the generic M-QAM technique in comparison with the enhanced heuristic decision rule (HDR) technique and a previously designed technique, the HDR technique. Based on the analyses performed, the enhanced HDR technique is less complex than the HDR technique. Finally, the numerical results show that the generic M-QAM technique can be eight times faster than the other two techniques when a large number of M-QAM symbols (e.g., > 1000) are consecutively transmitted.

Image De-noising forms an integral part of image processing. It is used as a standalone algorithm for improving the quality of the image obtained through camera as well as a starting stage for image processing applications like face recognition, super resolution etc. Non Local Means (NL-Means) and Bilateral Filter are two computationally complex de-noising algorithms which could provide good de-noising results. Due to its computational complexity, the real time applications associated with these letters are limited. In this thesis, we propose the use of hardware accelerators such as GPU (Graphics Processing Units) and FPGA (Field Programmable Gate Arrays) to speed up the filter execution and efficiently implement using them. GPU based implementation of these letters is carried out using Open Computing Language (Open CL). The basic objective of this research is to perform high speed de-noising without compromising on the quality. Here we implement a basic NL-Means filter, a Fast NL-Means filter, and Bilateral filter using Gauss Polynomial decomposition on GPU. We also propose a modification to the existing NL-Means algorithm and Gauss Polynomial Bilateral filter. Instead of Gaussian Spatial Kernel used in standard algorithm, Box Spatial kernel is introduced to improve the speed of execution of the algorithm. This research work is a step forward towards making the real time implementation of these algorithms possible. It has been found from results that the NL-Means implementation on GPU using Open CL is about 25x faster than regular CPU based implementation for larger images (1024x1024). For Fast NL-Means, GPU based implementation is about 90x faster than CPU implementation. Even with the improved execution time, the embedded system application of the NL-Means is limited due to the power and thermal restrictions of the GPU device. In order to create a low power and faster implementation, we have implemented the algorithm on FPGA. FPGAs are reconfigurable devices and enable us to create a custom architecture for the parallel execution of the algorithm. It was found that the execution time for smaller images (256x256) is about 200x faster than CPU implementation and about 25x faster than GPU execution. Moreover the power requirements of the FPGA design of the algorithm (0.53W) is much less compared to CPU(30W) and GPU(200W).

Pour le développement des convertisseurs d’électronique de puissance, la simulation en temps réel joue un rôle essentiel dans la validation des performances des convertisseurs et de leur contrôle avant leur réalisation. Cela permet de simuler et reproduire avec précision les formes d’ondes des courants et tensions des convertisseurs de puissance modélisés avec un pas de temps de simulation correspondant exactement au temps physique. Les circuits d’électronique de puissance sont caractérisés par le comportement non linéaire des interrupteurs. Par conséquent, les représentations des dispositifs de commutation sont cruciales dans la simulation en temps réel. Le modèle au niveau système est largement utilisé dans les simulateurs temps réel du commerce et les plates-formes expérimentales, qui modélisent les comportements des interrupteurspar deux états stationnaires distincts - passant et bloqué - et négligent tous les phénomènes transitoires. Ces dernières années, la simulation temps réel au niveau du composant est devenue populaire car elle permet de simuler les formes d'onde de commutation transitoires et de fournir des informations utiles concernant les contraintes sur les interrupteurs , les pertes, les effets parasites et les comportements électrothermiques. Néanmoins, la simulation temps réel au niveau du composant est contrainte par le pas de temps transitoire réalisable en raison des quantités de calcul accrues introduites par la non-linéarité du modèle de commutation.Afin d'intégrer le modèle au niveau du composant dans la simulation en temps réel, cette thèse porte sur l'exploration approfondie des techniques de modélisation et de simulation en temps réel au niveau composantdes convertisseurs d’électronique de puissance. Les techniques de simulation en temps réel les plus récentes sont d’abord examinées de manière exhaustive, tant au niveau du système que du composant. En outre, deux approches de modélisation au niveau du composant sont proposées, à savoir le modèle haute résolution quasi-transitoire (HRQT) et le modèle transitoire linéaire par morceaux (PLT). Dans le modèle HRQT, le modèle de réseau est implémenté par une simulation au niveau système tout en générant les formes d'onde de commutation transitoires avec une résolution de 5 ns, ce qui permet de simuler le convertisseur de puissance avec des transitoires rapides jusqu'à des dizaines de nanosecondes. Compte tenu des effets des transitoires sur l’ensemble du réseau, les modèles non linéaires des IGBT et diodes sont linéarisés par morceaux dans le modèle PLT. À l'aide de techniques efficaces de découplage de circuits, le modèle du convertisseur de puissance au niveau composant peut être simulé de manière stable avec un pas de temps de simulation global de 50 ns. Les deux modèles proposés sont testés et validés via différents cas sur une plate-forme temps réel de National Instruments basée sur un FPGA, comprenant un convertisseur boost boosté entrelacé (FIBC) pour le modèle HRQT, un convertisseur DC-DC-AC pour le modèle PLT et un convertisseur modulaire à plusieurs niveaux (MMC) pour les deux. Des résultats précis sont produits par rapport aux outils de simulation hors ligne. L'efficacité et les valeurs d'application sont également vérifiées par les résultats d’essais en temps réel. / In the development cycles of the power electronics converters, the real-time simulation plays an essential role in validating the converters’ and the controllers’ performances before their implementations on real systems. It can simulate and reproduce the current and voltage waveforms of the modeled power electronics converters accurately with a simulation time-step exactly corresponding to the physical time. The power electronics circuits are characterized by nonlinear switching behaviors. Therefore, the representations of switching devices are crucial in real-time simulation. The system-level model is widely used in both commercial real-time simulators and the experimentally built real-time platforms, which models the switching behaviors by two separate steady states – turn-on and turn-off, and neglects all the switching transients. In recent years, the device-level real-time simulation has become popular since it can simulate the transient switching waveforms and provide useful information with regard to the device stresses, the power losses, the parasitic effects, and electro-thermal behaviors. Nevertheless, the device-level real-time simulation is constrained by the achievable transient time-step due to the increased computational amounts introduced by the nonlinearity of the switch model.In order to integrate the device-level model in the real-time simulation, in this thesis, the device-level real-time modeling and simulation techniques of the power electronics converters are deeply explored. The state-of-art real-time simulation techniques are firstly reviewed comprehensively with regard to both system-level and device-level. Moreover, two device-level modeling approaches are proposed, including high- resolution quasi-transient model (HRQT) and the piecewise linear transient (PLT) model. In HRQT model, the network model can be implemented by system-level simulation while generating the transient switching waveforms with a 5 ns resolution, which is good at simulating the power converter with fast switching transients down to tens of nanoseconds. Considering the effects of the transient behaviors on the entire network, the PLT model is proposed by piecewise linearizing the nonlinear IGBT and diode equivalent models. With the help of effective circuit decoupling techniques, the device-level power converter model can be simulated stably with a 50 ns global simulation time-step. The proposed two models are tested and validated via different case studies on National Instruments (NI) FPGA-based real-time platform, including floating interleaved boost converter (FIBC) for HRQT model, DC-DC-AC converter for PLT model, and modular multi-level converter (MMC) for the both. Accurate results are produced compared to offline simulation tools. The effectiveness and the application values are further verified by the results of the real-time experiments.

The aim of this work is to implement digital filters into programmable gate array. The work also includes a description of the MEMS technology, including comparisons with the technology of MEMS microphones from various manufacturers. Another part is devoted to the Sigma-delta modulation. The main section is the design and implementation of digital CIC and FIR filters for signal processing of digital microphone, including simulation and verification of properties of the proposed filter in Matlab.

Der achte Band der wissenschaftlichen Schriftenreihe EINGEBETTETE, SELBSTORGANISIERENDE SYSTEME widmet sich der Synthese von partiell dynamisch rekonfigurierbaren, eingebetteten Systemen. Mit der Möglichkeit Hardwareblöcke zur Laufzeit auf programmierbaren Bausteinen neu zu konfigurieren, lässt sich eine höhere Flexibilität im Vergleich zu einer Hardwarerealisierung in eingebettete Systeme integrieren. Gleichzeitig sind diese Systeme durch eine gesteigerte Performance gegenüber Software gekennzeichnet. Die Flexibilität kann ausgenutzt werden, um kleinere Schaltkreise bei gleichem Funktionsumfang einzusetzen. Für die Integration von Rekonfigurierung sind zusätzliche Entwurfschritte im Design Flow notwendig. Herr Meisel stellt hierfür in seiner Arbeit eine Entwurfsmethodik vor und geht im Besonderen auf die Partitionierung, Platzierung und Steuerung in dynamisch rekonfigurierbaren, eingebetteten Systemen ein. Um eine vergleichsweise effizient zu realisierende Partitionierung des Systems zu erhalten, wurde das Overlaying Verfahren aus dem Bereich der Speicherverwaltung für dynamische Rekonfigurierung adaptiert. Für das Platzierungsverfahren wurden Rekonfigurierungen als Markov Kette modelliert, um so zu einer Minimierung der durchschnittlichen Rekonfigurierungsdauer zu gelangen. Die vorgestellte Rekonfigurierungssteuerung fokussiert auf einer ressourcensparenden Hardware Implementierung. Mit einem Entwurfsbeispiel werden die Vorteile und Ergebnisse des Ansatzes anschaulich illustriert. So kann der Leser die Mächtigkeit des entwickelten Ansatzes nachvollziehen und wird motiviert, die entwickelte Methodik auf weitere Anwendungsfälle zu übertragen. / Volume 8 of scientific series EINGEBETTETE, SELBSTORGANISIERENDE SYSTEME (Embedded Self-Organized Systems) addresses the synthesis of partially dynamically reconfigurable embedded systems. With the ability to configure hardware blocks during run-time, more flexibility can be integrated in embedded systems. At the same time, these systems have better performance than functions implemented in software. Through this flexibility it is possible to use smaller circuits without limiting the functionality. For the integration of reconfiguration into embedded systems, additional design steps are required. Mr. Meisel presents a design methodology for the design flow and primarily concerns the problem of partitioning, placement, and reconfiguration control in dynamically reconfigurable embedded systems. The implemented partitioning of the system is based on the adapted memory management concept of Overlaying. For the placement method the configurations are modeled as Markov chain, in order to minimize the average reconfiguration time. The presented reconfiguration control unit focuses on a resource-saving hardware implementation. The benefits and results of the approach are clearly illustrated with a design sample. The reader can understand the power of developed approach and is motivated to transfer the developed methodology to more use cases.

Today’s embedded systems depend on the availability of hybrid platforms, that contain heterogeneous computing resources such as programmable processors units (CPU’s or DSP’s) and highly specialized hardware cores. These platforms have been scaled down to integrated embedded system-on-chip. Modern platform FPGAs enhance such systems by the flexibility of runtime configurable silicon. One of the major advantages that arises is the ability to use hardware (HW) and software (SW) resources in a time-shared manner. Though the ability to dynamically assign computing resources based on decisions taken at runtime is given.