During test flights SAAB uses the data acquisition system COMET 16. The part of the system that receives the signals from the sensors and converts them is called KSM 15. The purpose of this thesis is to develop a data acquisition module on stacked PC/104 modules with a lower production cost. Our work has been divided into one part about analog signal conditioning and a second part with digital filtering and memory management of the sampled data. The analog part, designed of regular components like instrument amplifiers, voltage references, operational amplifiers and multiplexers, adjusts the sensors signal levels for the ADC’s that converts the signals. In the digital part the sampling frequency is decimated by digital FIR filters in several stages down to 16 Hz. All the resulting data is temporarily stored in a SDRAM memory before being recovered by the HL-11 board that handles the communication with the other parts of the COMET system. We have made a design proposal that needs some additional work and testing before a prototype can be made. It’s primarily the C code in the digital part that needs further development. Our result and conclusions should be a great help in the future when developing a small,cheap data acquisition system.

FIR filters are widely used nowadays, with applications from MP3 players, Hi-Fi systems, digital TVs, etc. to communication systems like wireless communication. They are implemented in DSPs and there are several trade-offs that make important to have an exact as possible estimation of the required filter order. In order to find a better estimation of the filter order than the existing ones, genetic expression programming (GEP) is used. GEP is a Genetic Algorithm that can be used in function finding. It is implemented in a commercial application which, after the appropriate input file and settings have been provided, performs the evolution of the individuals in the input file so that a good solution is found. The thesis is the first one in this new research line. The aim has been not only reaching the desired estimation but also pave the way for further investigations.

In this thesis we discuss the design and implementation of Digital Signal Processing (DSP) applications in a standard digital CMOS technology. The aim is to fulfill a throughput requirement with lowest possible power consumption. As a case study a frequency selective filter is implemented using a half-band FIR filter and a bireciprocal Lattice Wave Digital Filter (LWDF) in a 0.35 µm CMOS process. The thesis is presented in a top-down manner, following the steps in the topdown design methodology. This design methodology, which has been used for bit-serial maximally fast implementations of IIR filters in the past, is here extended and applied for digit-serial implementations of recursive and non-recursive algorithms. Transformations such as pipelining and unfolding for increasing the throughput is applied and compared from throughput and power consumption points of view. A measure of the level of the logic pipelining is developed, i.e., the Latency Model (LM), which is used as a tuning variable between throughput and power consumption. The excess speed gained by the transformations can later be traded for low power operation by lowering the supply voltage, i.e., architecture driven voltage scaling. In the FIR filter case, it is shown that for low power operation with a given throughput requirement, that algorithm unfolding without pipelining is preferable. Decreasing the power consumption with 40, and 50 percent compared to pipelining at the logic or algorithm level, respectively. The digit-size should be tuned with the throughput requirement, i.e., using a large digit-size for low throughput requirement and decrease the digit-size with increasing throughput. In the bireciprocal LWDF case, the LM order can be used as a tuning variable for a trade-off between low energy consumption and high throughput. In this case using LM 0, i.e., non-pipelined processing elements yields minimum energy consumption and LM 1, i.e., use of pipelined processing elements, yields maximum throughput. By introducing some pipelined processing elements in the non-pipelined filter design a fractional LM order is obtained. Using three adders between every pipeline register, i.e., LM 1/3, yields a near maximum throughput and a near minimum energy consumption. In all cases should the digit-size be equal to the number of fractional bits in the coefficient. At the arithmetic level, digit-serial adders is designed and implemented in a 0.35 µm CMOS process, showing that for the digit-sizes, , the Ripple-Carry Adders (RCA) are preferable over Carry-Look-Ahead adders (CLA) from a throughput point of view. It is also shown that fixed coefficient digitserial multipliers based on unfolding of serial/parallel multipliers can obtain the same throughput as the corresponding adder in the digit-size range D = 2...4. A complex multiplier based on distributed arithmetic is used as a test case, implemented in a 0.8 µm CMOS process for evaluation of different logic styles from robustness, area, speed, and power consumption points of view. The evaluated logic styles are, non-overlapping pseudo two-phase clocked C2MOS latches with pass-transistor logic, Precharged True Single Phase Clocked logic (PTSPC), and Differential Cascade Voltage Switch logic (DCVS) with Single Transistor Clocked (STC) latches. In addition we propose a non-precharged true single phase clocked differential logic style, which is suitable for implementation of robust, high speed, and low power arithmetic processing elements, denoted Differential NMOS logic (DN-logic). The comparison shows that the two-phase clocked logic style is the best choice from a power consumption point of view, when voltage scaling can not be applied and the throughput requirement is low. However, the DN-logic style is the best choice when the throughput requirements is high or when voltage scaling is used.

Parallelized implementations of FIR-filters are often used to meet throughput and power requirements. The most common methods to optimize coefficient multiplication in FIR-filters are developed for single rate filters, thus the added redundancy of parallel implementations cannot be utilized in the optimization. In this work optimization methods utilizing the redundancy of parallel filter implementations are evaluated for a set of low-pass and interpolation filters. Results show that the proposed methods offer parallelization with less than linear increases in hardware for several evaluated filters with up to 47% reduction in adder count compared to conventional methods. Furthermore, an optimization algorithm for retiming of algorithmic delays is evaluated both with and without pipelining. Synthesis results show that the retiming algorithm can reduce the power consumption with up to 48% without added latency for high throughput applications.

Millimeter wave (mm-Wave) has become increasingly popular frequency band for next-generation high-speed wireless communications. In mm-Wave, the wireless channel path loss is severe, demanding a high output power in transmitters (Tx) to meet a required SNR in receivers (Rx). Due to the intractable speed-power tradeoff ingrained in silicon processes, however, achieving a high power at mm-Wave, particularly over W-band (> 90 GHz), is challenging in silicon power amplifiers. To relieve the output power burden, phased-arrays are widely adopted in mm-Wave wireless communication systems -- namely, by leveraging a parallel power combining in the space domain, inherent in the phased arrays, the required output power per array element can be reduced significantly with increasing array size. In large arrays ( > 100's -- 1000's number of arrays), the required output power per element could be small, typically around several 10's mW or less in silicon-based phased arrays. In such small-to-medium scale output power level, the static power dissipations by transistor knee voltage and passive components could be a significant portion of the output power, decreasing power efficiency of power amplifiers drastically. This poses a significant concern on the power efficiency of the large-scale silicon-based phased arrays in mm-Wave. Another critical problem in mm-Wave wireless systems design is the increase of passive reactive components loss caused by worsening skin depth effect and increasing dielectric loss through silicon substrate. This essentially degrades the reactive components quality factor (Q) and limits frequency selectivity of the silicon-based mm-Wave systems. This thesis tackles these two major technical challenges to provide high frequency selectivity with maintaining high power efficiency for future mm-Wave wireless systems over W-band and beyond. First, various high-efficiency techniques such as impedance tuning with a reactive component at a cascoding stage in conventional stacked power amplifiers or load-pull based inter-stage matching technique, rather than conventional conjugate matching, have been applied to W-band CMOS and SiGe BiCMOS amplifiers to improve power efficiency with 5-10 dBm output power level, suitable for a large phased array applications, as detailed in Chapter 2 and 3. Second, a 4-tap finite impulse response (FIR) filter based receiver architecture is presented in Chapter 4. The FIR filtered receiver leverages a sinc-pulse type frequency nulls built-in in the transmission-line based FIR filter's frequency response to increase frequency selectivity. The proposed FIR filtered receiver achieves > 40-dB image rejection by placing an image signal at the null frequency at D-band, one of the largest image rejection performance at the highest frequency band reported so far. / Ph. D. / Due to recent advances in Silicon based solid-state technologies, the interest towards the millimeter wave (mm-Wave) frequency band has been emerging for next-generation high-speed wireless communication applications. One of the most significant parameters in a communication system would be the output power of a transmitter. However, the output power is limited especially at mm-wave frequencies. A phased array is one of the viable solutions to overcome this burden by utilizing a parallel power combing in the space domain. The required output power per element can be relieved, typically around several tens of mill watts or less. There are two major factors limiting the output power, which are the high loss of passive and active devices. This dissertation presents solutions to overcome these challenges. In addition, a 4-tap finite impulse response (FIR) filter based receiver architecture is introduced, which rejects unwanted image signals in heterodyne systems by utilizing sinc-pulse type frequency nulls. The proposed FIR filter achieves more than 40 dB of image rejection at D-band (110-170 GHz), which is one of the highest filtering performance in the millimeter-wave frequency band.

In recent years, genetic algorithms (GAs) began to be used in many disciplines such as pattern recognition, robotics, biology, and medicine to name just a few. GAs are based on Darwin's principle of natural selection which happens to be a slow process and, as a result, these algorithms tend to require a large amount of computation. However, they offer certain advantages as well over classical gradient-based optimization algorithms such as steepest-descent and Newton-type algorithms. For example, having located local suboptimal solutions they can discard them in favor of more promising local solutions and, therefore, they are more likely to obtain better solutions in multimodal problems. By contrast, classical optimization algorithms though very efficient, they are not equipped to discard inferior local solutions in favour of more optimal ones. This dissertation is concerned with the design of several types of digital filters by using GAs as detailed bellow. In Chap. 2, two approaches for the design of fractional delay (FD) filters based on a GA are developed. The approaches exploit the advantages of a global search technique to determine the coefficients of FD FIR and allpass-IIR filters based on the so-called Farrow structure. The GA approach was compared with a least-squares approach and was found to lead to improvements in the amplitude response and/or delay characteristic. In Chap. 3, a GA-based approach is developed for the design of delay equalizers. In this approach, the equalizer coefficients are optimized using an objective function based on the passband filter-equalizer group delay. The required equalizer is built by adding new second-order sections until the desired accuracy in terms of the flatness of the group delay with respect to the passband is achieved. With this approach stable delay equalizers satisfying arbitrary prescribed specifications with the desired degree of group-delay flatness can easily be obtained. In Chap. 4, a GA-based approach for the design of multiplierless FIR filters is developed. A recently-introduced GA, called orthogonal GA (OGA) based on the so-called experimental design technique, is exploited to obtain fixed-point implementations of linear-phase FIR filters. In this approach, the effects of finite word length are minimized by considering the filter as a cascade of two sections. The OGA leads to an improved amplitude response relative to that of an equivalent direct-form cascade filter obtained using the Remez exchange algorithm. In Chap. 5, a multiobjective GA for the design of asymmetric FIR filters is proposed. This GA uses a specially tailored elitist nondominated sorting GA (ENSGA) to obtain so-called Pareto-optimal solutions for the problem at hand. Flexibility is introduced in the design by imposing phase-response linearity only in the passband instead of the entire baseband as in conventional designs. Three objective functions based on the amplitude-response error and the flatness of the group-delay characteristic are explored in the design examples considered. When compared with a WLS design method, the ENSGA was found to lead to improvements in the amplitude response and passband group-delay characteristic. In Chap. 6, a hybrid approach for the design of IIR filters using a GA along with a quasi-Newton (QN) algorithm is developed. The hybrid algorithm, referenced to as the genetic quasi-Newton (GQN) algorithm combines the flexibility and reliability inherent in the GA with the fast convergence and precision of the QN algorithm. The GA is used as a global search tool to explore different regions in the parameter space whereas the QN algorithm exploits the efficiency of a gradient-based algorithm in locating local solutions. The GQN algorithm works well with an arbitrary random initialization and filters that would satisfy prescribed amplitude-response specifications can easily be designed

This thesis deals with artificial simulation of acoustic spaces by using reverberators. Output of this document consists of four reverberation algorithms and function that evaluates objective parameters of acoustic space from impulse responses. Reverberators and script were implemented using Matlab. Graphical user interface is used to present all of the algorithms for easier usability. First chapter deals with objective parameters of acoustic spaces and the ways they are computed from impulse response. Second chapter describes various structures which are used to build reverberators. Those structures are used in third chapter in implementations of reverberators. Third chapter also compares all implemented reverberators . In last chapter experiment was made. Impulse responses of three spaces were measured and subsequently aproximated by algorithms implemented in this thesis.

<p>Nonuniform sampling occurs in many practical applications either intentionally or unintentionally. This thesis deals with the reconstruction of two-periodic nonuniform signals which is of great importance in two-channel time-interleaved analog-to-digital converters. In a two-channel time-interleaved ADC, aperture delay mismatch between the channels gives rise to a two-periodic nonuniform sampling pattern, resulting in distortion and severely affecting the linearity of the converter. The problem is solved by digitally recovering a uniformly sampled sequence from a two-periodic nonuniformly sampled set. For this purpose, a time-varying FIR filter is employed. If the sampling pattern is known and fixed, this filter can be designed in an optimal way using least-squares or minimax design. When the sampling pattern changes now and then as during the normal operation of time-interleaved ADC, these filters have to be redesigned. This has implications on the implementation cost as general on-line design is cumbersome. To overcome this problem, a novel time-varying FIR filter with polynomial impulse response is developed and characterized in this thesis. The main advantage with these filters is that on-line design is no longer needed. It now suffices to perform only one design before implementation and in the implementation it is enough to adjust only one variable parameter when the sampling pattern changes. Thus the high implementation cost is decreased substantially.</p><p>Filter design and the associated performance metrics have been validated using MATLAB. The design space has been explored to limits imposed by machine precision on matrix inversions. Studies related to finite wordlength effects in practical filter realisations have also been carried out. These formulations can also be extended to the general M - periodic nonuniform sampling case.</p>

Nonuniform sampling occurs in many practical applications either intentionally or unintentionally. This thesis deals with the reconstruction of two-periodic nonuniform signals which is of great importance in two-channel time-interleaved analog-to-digital converters. In a two-channel time-interleaved ADC, aperture delay mismatch between the channels gives rise to a two-periodic nonuniform sampling pattern, resulting in distortion and severely affecting the linearity of the converter. The problem is solved by digitally recovering a uniformly sampled sequence from a two-periodic nonuniformly sampled set. For this purpose, a time-varying FIR filter is employed. If the sampling pattern is known and fixed, this filter can be designed in an optimal way using least-squares or minimax design. When the sampling pattern changes now and then as during the normal operation of time-interleaved ADC, these filters have to be redesigned. This has implications on the implementation cost as general on-line design is cumbersome. To overcome this problem, a novel time-varying FIR filter with polynomial impulse response is developed and characterized in this thesis. The main advantage with these filters is that on-line design is no longer needed. It now suffices to perform only one design before implementation and in the implementation it is enough to adjust only one variable parameter when the sampling pattern changes. Thus the high implementation cost is decreased substantially. Filter design and the associated performance metrics have been validated using MATLAB. The design space has been explored to limits imposed by machine precision on matrix inversions. Studies related to finite wordlength effects in practical filter realisations have also been carried out. These formulations can also be extended to the general M - periodic nonuniform sampling case.

The doctoral thesis deals with development and design of novel architectures of digital filters for low-power integrated circuits. The main goal was to achieve optimum parameters of digital filters with respect to the chip area, power consumption and operating frequency. The target group of the proposed architectures are application specific integrated circuits designed for signal processing from sensors using delta-sigma modulators. Three novel architectures of digital filters optimized for low-power integrated circuits are presented in the thesis. The thesis provides analysis and comparison of parameters of the new filter architectures with the parameters of architectures generated by Matlab tool. A software tool has been designed and developed for the practical application of the proposed architectures of digital filters. The developed software tool allows generating hardware description of the filters with respect to defined parameters.