The FFT support in an Ericsson's proprietary DSP is to be improved in order to achieve high performance without disrupting the current DSP architecture too much. The FFT:s and inverse FFT:s in question should support FFT sizes ranging from 12-2048, where the size is a multiple of prime factors 2, 3 and 5. Especially memory access conflicts could cause low performance in terms of speed compared with existing hardware accelerator. The problem addressed in this thesis is how to minimise these memory access conflicts. The studied FFT is a mixed-radix DIT FFT where the butterfly results are written back to addresses of a certain order. Furthermore, different buffer structures and sizes are studied, as well as different order in which to perform the operations within each FFT butterfly stage, and different orders in which to shuffle the samples in the initial stage. The study shows that for both studied buffer structures there are buffer sizes giving good performance for the majority of the FFT sizes, without largely changing the current architecture. By using certain orders for performing the operations and shuffling within the FFT stages for remaining FFT sizes, it is possible to reach good performance also for these cases.

A numerical method for computing three-dimensional Stokes flow driven by a doubly-periodic array of regularized forces is presented. In the non-periodic direction either a free boundary or a homogeneous Dirichlet condition is enforced. The method consists of finding a regularized Green's function in Fourier space analytically. Then only an inverse fast Fourier transform (inverse FFT) has to be computed. Accuracy is verified by comparing numerical results to a solution that is independent of the method. In an Ewald splitting, the FFT method can be used to compute the smooth component of the flow, which allows for a splitting parameter as small as a few grid cells. This selection makes the sum in physical space converge extremely fast. Numerical examples demonstrate that fact. Since the forces are regularized, in some cases splitting is not even needed, depending on the relative sizes of the numerical parameters. The method is applied to model the flow created by carpets of nodal cilia based on cilium shape. / acase@tulane.edu

The main goal of this thesis will be the design and implementation of a 2048-point FFT on an FPGA through the use of VHDL code.The FFT will use a butterfly Radix-2 architecture with focus on the comparison of the parameters between the system with different Worlengths, Coefficient Wordlengths and Symbol Error rates as well as different modulation types, comparing 64QAM and 256QAM for the 5Gsystem.This implementation will replace an FFT function block in a Matlab based open source 5G NR simulator based on the 3GPP 15 standard and simulate spectrum, MSE payload,and SER performance.

De nombreuses recherches tentent d'améliorer les convertisseurs actuels en proposant de nouvelles architectures et de nouveaux procédés de fabrication. Cette évolution est longue et doit s'exécuter étape par étape. Cependant, il est possible d'utiliser des méthodes permettant de compenser les lacunes d'un composant donné avant de franchir l'étape suivante. Ces méthodes de compensation permettent de repousser les limites du composant en attendant la maturité de la génération suivante. Elles permettent également<br />de mieux comprendre les défauts actuels et d'orienter les concepteurs vers des pistes prometteuses pour leurs recherches.<br />C'est dans ce contexte que nous proposons d'étudier l'effet d'une compensation par table de correspondance uni-dimensionnelle (LUT 1D) sur un convertisseur de type à repliement et à interpolation.<br />Afin de remplir cette table de correction, nous proposons d'utiliser et d'optimiser un algorithme d'extraction des non-linéarités du composant, basé sur une analyse fréquentielle du signal converti.<br />Les paramètres sensibles de la méthode de compensation sont ensuite étudiées au travers d'expérimentations menées sur un convertisseur spécialement conçut pour cet objectif. Nous établissons qu'il est possible de calculer une table de correspondance suffisamment robuste indépendamment des variations de fréquences et de température.<br />Finalement, nous proposons une nouvelle méthode d'extraction des paramètres spectraux d'un signal à partir de ressources de calculs très faibles. Cette étude permet d'entamer le processus d'embarquement de la compensation au sein du convertisseur. Cette finalité fait partie des perspectives liées à cette thèse.

<p>AbstractDifferent approaches for implementing a complex multiplier in pipelined FFT are considered andimplemented to find an efficient one in this project. The implemented design is synthesized on Cyclone IIand Stratix III to know the performance. The design is implemented with a focus of reducing the resourcesused. Some approaches resulted in the reduced number of DSP blocks and others resulted in reducednumber of LUTs. Analysis of Synthesis results is performed for different widths (bit lengths) of complexmultiplier approaches.</p>

<p>FFT processors are today one of the most important blocks in communication equipment. They are used in everything from broadband to 3G and digital TV to Radio LANs. This master's thesis project will deal with pipelined hardware solutions for FFT processors with long FFT transforms, 1K to 8K points. These processors could be used for instance in OFDM communication systems. </p><p>The final implementation of the FFT processor uses a GALS (Globally Asynchronous Locally Synchronous) architecture, that implements the SDF (Single Delay Feedback) radix-22 algorithm. </p><p>The goal of this report is to outline the knowledge gained during the master's thesis project, to describe a design methodology and to document the different building blocks needed in these kinds of systems.</p>

<p><p>Benchmarking of DSP kernel algorithms was conducted in the thesis on a DSP processor for teaching in the course TESA26 in the department of Electrical Engineering. It includes benchmarking on cycle count and memory usage. The goal of the thesis is to evaluate the quality of a single MAC DSP instruction set and provide suggestions for further improvement in instruction set architecture accordingly. The scope of the thesis is limited to benchmark the processor only based on assembly coding. The quality check of compiler is not included. The method of the benchmarking was proposed by BDTI, Berkeley Design Technology Incorporations, which is the general methodology used in world wide DSP industry.</p><p>Proposals on assembly instruction set improvements include the enhancement of FFT and DCT. The cycle cost of the new FFT benchmark based on the proposal was XX% lower, showing that the proposal was right and qualified. Results also show that the proposal promotes the cycle cost score for matrix computing, especially matrix multiplication. The benchmark results were compared with general scores of single MAC DSP processors offered by BDTI.</p></p>

<p>A new path of DSP processor design is described in this thesis with an example, to design a FFT processor. It is an innovative concept for DSP processor design developed by the Electronic Systems Division in the department of Electrical Engineer department in Linköping University. </p><p>The project described in this thesis is to design a Sande-Tukey FFT processor step by step. It will go through all steps from the simplest MATLAB specification to the final synthesizable VHDL specification. The steps should be as small as possible in order to avoid error and MATLAB should be used as for as possible.</p>

<p>3GPP LTE (Long Term Evolution) is a project of the Third Generation Partnership Project to improve the UMTS (Universal Mobile Telecommunications System) mobile phone standard to cope with future technology evolutions. Two duplex schemes FDD and TDD are investigated in this thesis. Several computational intensive components of the baseband processing for LTE uplink such as synchronization, channel estimation, equalization, soft demapping, turbo decoding is analyzed. Cost analysis is hardware independent so that only computational complexity is considered in this thesis. Hardware dependent discussion for LTE baseband SDR platform is given according the analysis results.</p>

<p>By analyzing ISAR images, the characteristics of military platforms with respect to radar visibility can be evaluated. The method, which is based on the Discrete-Time Fourier Transform (DTFT), that is currently used to calculate the ISAR images requires large computations efforts. This thesis investigates the possibility to replace the DTFT with the Fast Fourier Transform (FFT). Such a replacement is not trivial since the DTFT is able to compute a contribution anywhere along the spatial axis while the FFT delivers output data at fixed sampling, which requires subsequent interpolation. The interpolation leads to a difference in the ISAR image compared to the ISAR image obtained by DTFT. On the other hand, the FFT is much faster. In this quality-and-time trade-off, the objective is to minimize the error while keeping high computational efficiency. </p><p>The FFT-approach is evaluated by studying execution time and image error when generating ISAR images for an aircraft model in a controlled environment. The FFT method shows good results. The execution speed is increased significantly without any visible differences in the ISAR images. The speed-up- factor depends on different parameters: image size, degree of zero-padding when calculating the FFT and the number of frequencies in the input data.</p>