AbstractDifferent approaches for implementing a complex multiplier in pipelined FFT are considered andimplemented to find an efficient one in this project. The implemented design is synthesized on Cyclone IIand Stratix III to know the performance. The design is implemented with a focus of reducing the resourcesused. Some approaches resulted in the reduced number of DSP blocks and others resulted in reducednumber of LUTs. Analysis of Synthesis results is performed for different widths (bit lengths) of complexmultiplier approaches.

The majority of all power cuts that affects individuals and communities are caused by earth faults on the power transmission lines at 10kV and 20kV level [1]. If these power cuts could be eliminated, less disturbances and interrupts would lead to large amounts of money savings. Swedish Neutral has developed such a protection system. When an earth fault occurs power is injected into the neutral point of the transformer. The RCC (Residual Current Compensation) protection calculates a compensation current exactly 180 degrees out of phase to the fault current. Doing this, the voltage at the fault location becomes very close to zero, without affecting the power transmission. The protection system can only compensate automatically for the fundamental frequency (50Hz), and manually for the 3rd, 5th, 7th and 9th harmonics. In most cases, when the harmonics are very small it is not necessary to compensate for them. There are though cases when compensation for the harmonics is necessary. This thesis focuses on finding the best method to extract the content of a sampled signal regarding both simplicity and speed. Both amplitude and phase of each harmonic must be calculated. Is the proposed method suitable for the current computer system and how can it easily be implemented. Because the fundamental frequency is known and the harmonics are all multiples of the fundamental frequency it makes the task less complex. It is not necessary to use the FFT algorithm. The DFT can be calculated using correlation. Both phase and amplitude can be calculated very precisely with few samples and not so many computer operations.

Benchmarking of DSP kernel algorithms was conducted in the thesis on a DSP processor for teaching in the course TESA26 in the department of Electrical Engineering. It includes benchmarking on cycle count and memory usage. The goal of the thesis is to evaluate the quality of a single MAC DSP instruction set and provide suggestions for further improvement in instruction set architecture accordingly. The scope of the thesis is limited to benchmark the processor only based on assembly coding. The quality check of compiler is not included. The method of the benchmarking was proposed by BDTI, Berkeley Design Technology Incorporations, which is the general methodology used in world wide DSP industry. Proposals on assembly instruction set improvements include the enhancement of FFT and DCT. The cycle cost of the new FFT benchmark based on the proposal was XX% lower, showing that the proposal was right and qualified. Results also show that the proposal promotes the cycle cost score for matrix computing, especially matrix multiplication. The benchmark results were compared with general scores of single MAC DSP processors offered by BDTI.

Choosing a right processor for an embedded application, or designing a new pro-cessor requires us to know how it stacks up against the competition, or sellinga processor requires a credible communication about its performance to the cus-tomers, which means benchmarking of a processor is very important. They arerecognized world wide by processor vendors and customers alike as the fact-basedway to evaluate and communicate embedded processor performance. In this the-sis, the benchmarking of ePUMA multiprocessor developed by the Division ofComputer Engineering, ISY, Linköping University, Sweden will be described indetails. A number of typical digital signal processing algorithms are chosen asbenchmarks. These benchmarks have been implemented in assembly code withtheir performance measured in terms of clock cycles and root mean square errorwhen compared with result computed using double precision. The ePUMA multi-processor platform which comprises of the Sleipnir DSP processor and Senior DSPprocessor was used to implement the DSP algorithms. Matlab inbuilt models wereused as reference to compare with the assembly implementation to derive the rootmean square error values of different algorithms. The execution time for differentDSP algorithms ranged from 51 to 6148 clock cycles and the root mean squareerror values varies between 0.0003 to 0.11.

By analyzing ISAR images, the characteristics of military platforms with respect to radar visibility can be evaluated. The method, which is based on the Discrete-Time Fourier Transform (DTFT), that is currently used to calculate the ISAR images requires large computations efforts. This thesis investigates the possibility to replace the DTFT with the Fast Fourier Transform (FFT). Such a replacement is not trivial since the DTFT is able to compute a contribution anywhere along the spatial axis while the FFT delivers output data at fixed sampling, which requires subsequent interpolation. The interpolation leads to a difference in the ISAR image compared to the ISAR image obtained by DTFT. On the other hand, the FFT is much faster. In this quality-and-time trade-off, the objective is to minimize the error while keeping high computational efficiency. The FFT-approach is evaluated by studying execution time and image error when generating ISAR images for an aircraft model in a controlled environment. The FFT method shows good results. The execution speed is increased significantly without any visible differences in the ISAR images. The speed-up- factor depends on different parameters: image size, degree of zero-padding when calculating the FFT and the number of frequencies in the input data.

Kraven på dagens trådlösa förbindelser kommer hela tiden att öka och med detta följer även högre krav på nya produkter som kan tillgodose de ökade kraven. För att göra processen från idé till produkt snabbare krävs enkla verktyg för att snabbt kunna gå från den formulerade standarden till en hårdvaruprototyp. Detta arbete har använt sig av ett av dessa verktyg som idag finns tillgängliga, Xilinx System Generator for DSP 1.1, för att ta fram sändare och mottagare för en del av den trådlösa standarden IEEE 802.11a. Arbetet ger en beskrivning av hur sändare och mottagare är uppbyggda samt även synpunkter på System Generator och beskrivningar av problem som uppstod under arbetet. / The demands on todays wireless communications will continue to increase and with this follows a demand for shorter and shorter development times for the products that are going to satisfy this demand. To accomplish this shorter development time simple tools for going from the formulated standard to a hardware prototype is needed. This work uses one of these tools today available, Xilinx System Generator for DSP 1.1, to develop a transmitter and a reciever for a part of the wireless standard IEEE 802.11a. The work gives a description of the building blocks of the transmitter and the reciever but also some views on System Generator and descriptions of problems that were encountered during the work.

FFT processors are today one of the most important blocks in communication equipment. They are used in everything from broadband to 3G and digital TV to Radio LANs. This master's thesis project will deal with pipelined hardware solutions for FFT processors with long FFT transforms, 1K to 8K points. These processors could be used for instance in OFDM communication systems. The final implementation of the FFT processor uses a GALS (Globally Asynchronous Locally Synchronous) architecture, that implements the SDF (Single Delay Feedback) radix-22 algorithm. The goal of this report is to outline the knowledge gained during the master's thesis project, to describe a design methodology and to document the different building blocks needed in these kinds of systems.

A new path of DSP processor design is described in this thesis with an example, to design a FFT processor. It is an innovative concept for DSP processor design developed by the Electronic Systems Division in the department of Electrical Engineer department in Linköping University. The project described in this thesis is to design a Sande-Tukey FFT processor step by step. It will go through all steps from the simplest MATLAB specification to the final synthesizable VHDL specification. The steps should be as small as possible in order to avoid error and MATLAB should be used as for as possible.

In the current study, the four most common Particle Image Velocimetry (PIV) cross-correlation algorithms were evaluated by measuring the displacement of particles in computer generated images. The synthetic images were employed to compare the methods since the particle diameter, density, and intensity could be controlled, removing some of the uncertainty found in images collected during experiments, e. g. parallax, 3-D motion, etc. The most important parameter that was controlled in the synthetic images was the particle motion. Six different displacement functions were applied to move the particles between images: uniform translation, step, sawtooth, sinusoid, line source and line vortex. The four algorithms, which all use the fast Fourier transform (FFT) to perform the cross-correlation, were evaluated with four criteria; (1) spatial resolution, (2) dynamic range, (3) accuracy and (4) robustness. The uniform translation images determined the least error possible with each method, of which the deformed FFT proved to be the most accurate. The super resolution FFT and deformed FFT methods could not properly measure the infinite displacement gradient in the step images due to the interpolation of the displacement vector field used by each method around the step. However, the predictor corrector FFT scheme, which does not require interpolation when determining the interrogation area offset, successfully measured the infinite displacement gradient in the step images. The smaller interrogation areas used by the super resolution FFT scheme proved to be the best method to capture the high frequency finite displacement gradients in the sawtooth and sinusoid images. Also shown in the sawtooth and sinusoid images is the positional bias error introduced by assuming the measured particle displacement occurs at the centre of the interrogation area. The deformed FFT method produced the most accurate results for the source and vortex images, which both contained displacement gradients in multiple directions. Experimentally obtained images were also evaluated to verify the results derived using the synthetic images. The flow in a multiple grooved channel, using both water and air as the fluid medium in separate experiments, was measured and compared to DNS simulations reported by Yang. The mean velocity, average vorticity and turbulent fluctuations determined from both experiments using the deformed FFT method compared very well to the DNS calculations.

This Master thesis deals with wave propagation and starts with wave propagation basics. It briefly presents the theory for the diffraction over terrain obstacles and describes two different path loss models, the Hata model and a FFT-based model. The significance of this paper is that it gives the simulation results for the models mentioned above and presents a comparison between the results obtained from an empirical formula and the FFT-model. The comparison shows that the approach based on Fast Fourier Transform is good enough for prediction of the path loss and that it is a time efficient method.