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The Global ETD Search service is a free service for researchers
to find electronic theses and dissertations. This service is
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Networked Digital Library of Theses and Dissertations.
Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
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Showing 21 to 24 of 24 (0.042 seconds)Spelling suggestions: "subject:"fibre achannel"" "subject:"fibre 2channel""
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200 MBPS TO 1 GBPS DATA ACQUISITION & CAPTURE USING RACEWAYO’Connell, Richard 10 1900 (has links)
International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada / For many years VME has been the platform of choice for high-performance, real-time data
acquisition systems. VME’s longevity has been made possible in part by timely
enhancements which have expanded system bandwidth and allowed systems to support
ever increasing throughput. One of the most recent ANSI-standard extensions of the VME
specification defines RACEway, a system of dynamically switched, 160 Mbyte/second
board-to-board interconnects. In typical systems RACEway increases the internal
bandwidth of a VME system by an order of magnitude. Since this bandwidth is both
scaleable and deterministic, it is particularly well suited to high-performance, real-time
systems.
The potential of RACEway for very high-performance (200 Mbps to 1 Gbps) real-time
systems has been recognized by both the VME industry and a growing number of system
integrators. This recognition has yielded many new RACEway-ready VME products from
more than a dozen vendors. In fact many significant real-time data acquisition systems that
consist entirely of commercial-off-the-shelf (COTS) RACEway products are being
developed and fielded today.
This paper provides an overview of RACEway technology, identifies the types of
RACEway equipment currently available, discusses how RACEway can be applied in
high-performance data acquisition systems, and briefly describes two systems that
acquiring and capturing real-time data streams at rates from 200 Mbps to 1 Gbps using
RACEway.
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300 MBPS CCSDS Processing Using FPGA'sGenrich, Thad J. 10 1900 (has links)
International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / This paper describes a 300 Mega Bit Per Second (MBPS) Front End Processor (FEP) prototype completed in early 1993. The FEP implements a patent pending parallel frame synchronizer (frame sync) design in 12 Actel 1240 Field Programmable Gate Arrays (FPGA's). The FEP also provides (255,223) Reed-Solomon (RS) decoding and a High Performance Parallel Interface (HIPPI) output interface. The recent introduction of large RAM based FPGA's allows greater high speed data processing integration and flexibility to be achieved. A proposed FEP implementation based on Altera 10K50 FPGA's is described. This design can be implemented on a single slot 6U VME module, and includes a PCI Mezzanine Card (PMC) for a commercial Fibre Channel or Asynchronous Transfer Mode (ATM) output interface module. Concepts for implementation of (255,223) RS and Landsat 7 Bose-Chaudhuri-Hocquenghem (BCH) decoding in FPGA's are also presented. The paper concludes with a summary of the advantages of high speed data processing in FPGA's over Application Specific Integrated Circuit (ASIC) based approaches. Other potential data processing applications are also discussed.
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WORKSHOP "MOBILITÄT"Anders, Jörg 12 June 2001 (has links)
Gemeinsamer Workshop von Universitaetsrechenzentrum und Professur "Rechnernetze und verteilte Systeme" der Fakultaet fuer Informatik der TU Chemnitz.
Workshop-Thema: Mobilitaet
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| 24 |
WORKSHOP "MOBILITÄT"Anders, Jörg 12 June 2001 (has links)
Gemeinsamer Workshop von Universitaetsrechenzentrum und Professur "Rechnernetze und verteilte Systeme" der Fakultaet fuer Informatik der TU Chemnitz.
Workshop-Thema: Mobilitaet
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