A maioria dos sistemas embarcados hoje desenvolvidos utilizam complexos sistemas eletrônicos integrados em um único chip, os Systems-on-a-Chip (SoC). A análise do comportamento de uma aplicação em execução, ou seja, o profiling nesses sistemas não é uma tarefa trivial em virtude da complexidade dos SoCs e pela restrição de ferramentas de profiling adequadas. Neste contexto, este trabalho apresenta o P2L, uma ferramenta de profiling que se baseia em métricas de nível de instrução e função para o processador LEON3. O P2L fornece estatísticas detalhadas de uso do processador, memórias e barramento de programas em execução sem uso de instrumentação. A ferramenta é composta por um componente em hardware e drivers e aplicativos em software. Os resultados mostram que o P2L fornece medidas com erro inferior a 1% e overhead desprezível quando comparado ao tempo de execução nativa do programa e ao do profiler GNU gprof. / Most embedded systems developed today use complex electronic systems integrated into a single chip, the Systems-on-a-Chip (SoC). The analysis of the behavior of a running application or profiling in these systems is not a trivial task due to the complexity of the SoC and the restriction of appropriate profiling tools. In this context, this work presents P2L - a profiling tool that is based on instruction and function level metrics for the LEON3 processor. P2L provides detailed usage statistics of the processor, memories, and bus of running programs without the use of instrumentation. The tool consists of a component in hardware, drivers and applications software. The results show that P2L provides measures with an error less than 1% and negligible overhead compared to native runtime program and the GNU profiler gprof.

O foco central desse trabalho é a utilização e aprimoramento de um framework Peripheral Component Interconnect Express (PCI Express®) para a comunicação de dados em um Espectrômetro Digital de Ressonância Magnética (Digital Magnetic Resonance Spectrometer – DMRS) utilizando o conceito de Field-Programmable Gate Array (FPGA). Esse trabalho foi desenvolvido para servir como base de comunicação para o Espectrômetro Digital de Ressonância Magnética do Centro de Imagens e Espectroscopia in vivo por Ressonância Magnética (CIERMag) devido ao requerimento de altas taxas de transferência dos dados adquiridos. A integração dessa nova comunicação, entre o software e o hardware do espectrômetro, mantém compatibilidade com as interfaces já existentes possibilitando a execução de todas as sequências desenvolvidas sem nenhuma alteração. A incorporação da comunicação PCI Express provê uma solução com um número menor de etapas por transferência em comparação com a comunicação Ethernet. Com isso é possível aumentar o desempenho do sistema e obter taxas de transferência mais elevadas. Para isso, foram feitas mudanças no hardware de forma a torná-lo mais eficiente, reduzindo o número de ciclos de clock por operação e também a quantidade de lógica sintetizada. Além disso, a latência do software durante as transferências também foi reduzida através da utilização de interrupções Message Signaled Interrupt (MSI) e do método Scatter and Gather usado para reduzir a quantidade de cópias de dados na memória principal do computador. Dessa forma, obteve-se, como resultados reais, uma taxa de transferência efetiva (throughput) de 97% do valor máximo da banda possível do barramento PCI Express. / The central focus of this work is the implementation and use of a Peripheral Component Interconnect Express (PCI Express®) framework for data communication on a Digital Magnetic Resonance Spectrometer (DMRS) using the concept of Field-Programmable Gate Array (FPGA). This work is being developed to serve as a communication basis for the magnetic resonance Digital Spectrometer of the Centro de Imagens e Espectroscopia in vivo por Ressonância Magnética (CIERMag) due to demand of high transfer rates of acquired data. The integration of this new communication, between spectrometer software and hardware, keeps compatibility with existing interfaces, making it possible to execute all developed magnetic resonance sequences without any change. The incorporation of PCI Express communication provides solution with a lower number of steps per transfer when compared to Ethernet communication. By this means it\'s possible to increase system performance and, as result, have higher transfer rates. To accomplish that, the number of clock cycles per operation was reduced, so was the synthesized logic. Furthermore, software latency for data transfer was also reduced consequence of MSI interruption implementation and the use of Scatter and Gather method to remove data movement across the computer main memory. Therefore, it was obtained, as measured real result, a throughput value of 97% the theoretical maximum value for the hardware.

Este trabalho desenvolve a simulação do controle de velocidade de motor de indução com a técnica de controle direto de torque (Direct Torque Control - DTC), sendo executada em um dispositivo lógico programável tipo FPGA (Field Programable Gate Array). A simulação é realizada usando-se dois programas: O MATLAB/Simulink e o ModelSim, sendo que estes dois programas trabalham em modo de co-simulação provida pelo toolbox Link-for-ModelSim do Simulink. Enquanto a dinâmica do motor e do inversor é executada no MATLAB, o algoritmo de controle da estratégia DTC é executada no ModelSim. O algoritmo de acionamento DTC é escrito em linguagem de descrição de hardware VHDL (Very High Speed Integrated Circuit Hardware Description Language - VHSIC HDL) e utiliza a aritmética de ponto flutuante. Os resultados das simulações são apresentados e analisados no final deste trabalho. / This work presents a simulation of induction motor speed control using the technique of direct torque control (DTC), performed in a reprogrammable device type FPGA. The simulation is performed using two programs: MATLAB/Simulink and ModelSim, where these two programs work in a co-simulation mode, provide by Link for ModelSim toolbox from Simulink. While the motor and inverter dynamics is performed in MATLAB, the control algorithm of DTC technique runs in the ModelSim program. The algorithm of DTC drive is written in hardware description language (VHDL) and use the float point arithmetic. The simulation results are presented and analyzed in the end of this work.

O aumento constante da demanda por sistemas computacionais cada vez mais eficientes tem motivado a busca por sistemas híbridos customizados compostos por GPP (General Purpose Processor), FPGAs (Field-Programmable Gate Array) e GPUs (Graphics Processing Units). Quando utilizados em conjunto possibilitam otimizar a relação entre desempenho e consumo de energia. Tais sistemas dependem de técnicas que façam o mapeamento mais adequado considerando o perfil do código fonte. Nesse sentido, este projeto propõe uma técnica para realizar o mapeamento entre GPP e FPGA. Para isso, utilizou-se como base uma abordagem de mineração de dados que avalia a similaridade entre código fonte. A técnica aqui desenvolvida obteve taxas de acertos de 65,67% para códigos sintetizados para FPGA com a ferramenta LegUP e 59,19% para Impulse C, considerando que para GPP o código foi compilado com o GCC (GNU Compiler Collection) utilizando o suporte a OpenMP. Os resultados demonstraram que esta abordagem pode ser empregada como um ponto de decisão inicial no processo de mapeamento em sistemas híbridos, somente analisando o perfil do código fonte sem que haja a necessidade de execução do mesmo para a tomada de decisão. / The steady increasing on demand for efficient computer systems has been motivated the search for customized hybrid systems composed by GPP (general purpose processors), FPGAs (Field- Programmable Gate Array) and GPUs (Graphics Processing Units). When they are used together allow to exploit their computing resources to optimize performance and power consumption. Such systems rely on techniques make the most appropriate mapping considering the profile of source code. Thus, this project proposes a technique to perform the mapping between GPP and FPGA. For this, it is applied a technique based on a data mining approach that evaluates the similarity between source code. The proposed method obtained hit rate 65.67% for codes synthesized in FPGA using LegUP tool and 59.19% for Impulse C tool, whereas for GPP, the source code was compiled on GCC (GNU Compiler Collection) using OpenMP. The results demonstrated that this approach can be used as an initial decision point on the mapping process in hybrid systems, only analyzing the profile of the source code without the need for implementing it for decision-making.

Atualmente, otimizar uma arquitetura ou um sistema de software não significa, necessariamente, aumentar o seu desempenho computacional. Devido a popularização de sistemas embutidos energizados por bateria, um item de grande importância a ser otimizado é o consumo de energia. De forma a obedecer às restrições de consumo, pesquisadores têm concentrado seus esforços na criação de ferramentas que possibilitam a modelagem, a otimização e a estimação do consumo de energia. Nos últimos anos, FPGAs têm apresentado um grande desenvolvimento nos quesitos densidade, velocidade e capacidade de armazenamento. Essas características tornaram possível a construção de sistemas complexos formados por um ou mais processadores soft-core. Esse tipo de processador permite uma personalização detalhada de suas características arquiteturais, possibilitando uma melhor adequação às restrições de tempo e espaço em um projeto. O objetivo deste trabalho é construir um estimador de potência para softwares que têm como alvo o processador soft-core Nios II da Altera, permitindo saber com antecedência quanta energia será consumida devido à execução de programas e aplicações de robótica móvel. O modelo implementado neste trabalho foi testado com vários benchmarks padronizados e os resultados obtidos provaram ser bastante adequados para estimar a energia consumida por um programa, obtendo erros de estimação máximos de 4,78% / Nowadays, optimization of hardware and software systems does not necessarily mean increasing their computational performance. Due to the popularization of battery-operated embedded systems, energy comsumption has become a very critical issue. Several tools have been created to model, optimize, and estimate energy consumption, allowing power constraints to be achieved. Lately, FPGAs have presented great advancements on density, speed and storage capacity. Such characteristics made possible the implementation of complex systems comprising one or more soft-core processors. This kind of processors allows detailed customization of its architectural features, enabling timinig, and area constraints of a design to be reached. The aim of this work is to build a power estimator to predict the energy comsumption of a software running on the Altera Nios II soft-core processor. The implemented estimation model presented on this dissertation has been tested with several standard benchmarks and the results obtained have proven to be suitable for estimating the energy consumption of a software with a maximum error of 4.78%

Este trabalho propõe um controlador PID (Proporcional, Integrador, Derivativo), implementado em hardware reconfigurável, para controle de ganho de uma câmera com sensor CMOS. O conceito utilizado é o de sistemas SoC (System-on-a-Chip). As principais funções realizadas pelo sistema são: Aquisição da imagem, montagem do histograma, análise do histograma, controle de ganho baseado na análise do histograma. O sistema proposto tem como objetivo conter algumas funções básicas de controle de ganho que possam servir de base para construção de sistemas de visão computacional que possibilitem a otimização do tempo gasto na construção de novos sistemas, deixando o projetista concentrado na parte mais específica do sistema. O algoritmo de controle de ganho através da análise de histograma demonstrou ser além de funcional, altamente flexível, pois pode ser aplicado a qualquer câmera, independente do tipo do sensor. Este algoritmo pode ser aplicado a tipos diferentes de sensores, com diferentes taxas de aquisição e transmissão de imagens. Este ambiente baseado em computação reconfigurável proporciona alta performance e flexibilidade no modo de implementação, possibilitando que o hardware seja configurado para satisfazer situações que exigem alto desempenho, que pode ser obtido através do paralelismo de operações. Esta arquitetura ainda possibilita a configuração de processadores que executam operações em software em conjunto com operações executadas em hardware. O sistema final controla a câmera CMOS de maneira adequada às aplicações robóticas de tempo real / This paper proposes a PID controller (Proportional, Integrator, Derivative), implemented in reconfigurable hardware to control a CMOS sensor camera gain. The concept used is the system SoC (System-on-a-Chip). The main functions performed by the system are: image acquisition, assembly of the histogram, histogram analysis, gain control based analysis of the histogram. The proposed system aims to contain some basic gain control functions. These functions may serve as a basis for future construction of computer vision systems. This work will optimize the time spent in building new systems, leaving the designer free to concentrate on more specific development. The gain control algorithm through the analysis of histogram proved be functional, highly exible, and it can be applied to any camera, regardless of the type of sensor. This algorithm can be applied to different types of image sensors with different acquisition and transmission rates. This environment-based reconfigurable computing provides high performance and exibility in implementation, enabling the hardware to be confiogured to meet situations that require high performance, which can be obtained through parallelism of operations. This architecture also enables the configuration of processors that perform software operations in conjunction with hardware operations. The final system controls the CMOS camera accordingly to real-time robotic applications

Parmi les cibles architecturales susceptibles d'être utilisées pour réaliser un système de traitement sur puce (SoC), les architectures reconfigurables dynamiquement (ARD) offrent un potentiel de flexibilité et de dynamicité intéressant. Cependant ce potentiel est encore difficile à exploiter pour réaliser des applications massivement parallèles sur puce. Dans nos travaux nous avons recensé et analysé les solutions actuellement proposées pour utiliser les ARD et nous avons constaté leurs limites parmi lesquelles : l'utilisation d'une technologie particulière ou d'architecture propriétaire, l'absence de prise en compte des applications parallèles, le passage à l'échelle difficile, l'absence de langage adopté par la communauté pour l'utilisation de la flexibilité des ARD, ...Pour déployer une application sur une ARD il est nécessaire de considérer l'hétérogénéité et la dynamicité de l'architecture matérielle d'une part et la parallélisation des traitements d'autre part. L'hétérogénéité permet d'avoir une architecture de traitement adaptée aux besoins fonctionnels de l'application. La dynamicité permet de prendre en compte la dépendance des applications au contexte et de la nature des données. Finalement, une application est naturellement parallèle.Dans nos travaux nous proposons une solution pour le déploiement sur une ARD d'une application parallèle en utilisant les flots de conception standard des SoC. Cette solution est appelée MATIP (MPI Application Task Integreation Platform) et utilise des primitives du standard MPI version 2 pour effectuer les communications et reconfigurer l'architecture de traitement. MATIP est une solution de déploiement au niveau de la conception basée plate-forme (PBD).La plateforme MATIP est modélisée en trois couches : interconnexion, communication et application. Nous avons conçu chaque couche pour que l'ensemble satisfasse les besoins en hétérogénéité et dynamicité des applications parallèles . Pour cela MATIP utilise une architecture à mémoire distribuée et exploite le paradigme de programmation parallèle par passage de message qui favorise le passage à l'échelle de la plateforme.MATIP facilite le déploiement d'une application parallèle sur puce à travers un template en langage Vhdl d'intégration de tâches. L'utilisation des primitives de communication se fait en invoquant des procédures Vhdl.MATIP libère le concepteur de tous les détails liés à l'interconnexion, la communication entre les tâches et à la gestion de la reconfiguration dynamique de la cible matérielle. Un démonstrateur de MATIP a été réalisée sur des FPGA Xilinx à travers la mise en oe{}uvre d'une application constituée de deux tâches statiques et deux tâches dynamiques. MATIP offre une bande passante de 2,4 Gb/s et une la latence pour le transfert d'un octet de 3,43 µs ce qui comparée à d'autres plateformes MPI (TMD-MPI, SOC-MPI, MPI HAL) met MATIP à l'état de l'art. / Among the architectural targets that could be buid a system on chip (SoC), dynamically reconfigurable architectures (DRA) offer interesting potential for flexibility and dynamicity . However this potential is still difficult to use in massively parallel on chip applications. In our work we identified and analyzed the solutions currently proposed to use DRA and found their limitations including: the use of a particular technology or proprietary architecture, the lack of parallel applications consideration, the difficult scalability, the lack of a common language adopted by the community to use the flexibility of DRA ...In our work we propose a solution for deployment on an DRA of a parallel application using standard SoC design flows. This solution is called MATIP ( textit {MPI Application Platform Task Integreation}) and uses primitives of MPI standard Version 2 to make communications and to reconfigure the MP-RSoC architecture . MATIP is a Platform-Based Design (PBD) level solution.The MATIP platform is modeled in three layers: interconnection, communication and application. Each layer is designed to satisfies the requirements of heterogeneity and dynamicity of parallel applications. For this, MATIP uses a distributed memory architecture and utilizes the message passing parallel programming paradigm to enhance scalability of the platform.MATIP frees the designer of all the details related to interconnection, communication between tasks and management of dynamic reconfiguration of the hardware target. A demonstrator of MATIP was performed on Xilinx FPGA through the implementation of an application consisting of two static and two dynamic hardware tasks. MATIP offers a bandwidth of 2.4 Gb / s and latency of 3.43 microseconds for the transfer of a byte. Compared to other MPI platforms (TMD-MPI, SOC-MPI MPI HAL), MATIP is in the state of the art.

Durant la dernière décennie, la miniaturisation des technologies de semi-conducteurs et de l’intégration à grande échelle a donné lieu à la conception de systèmes complexes, notamment l’intégration de plusieurs milliards de transistors sur un même die. Cette tendance pose de nombreux défis de fabrication et de fiabilité tels que la dissipation de puissance, la variabilité technologique et la polyvalence des applications. Les problèmes de fiabilité, représentées par la présence de points chauds thermiques peuvent accélérer la dégradation des transistors, et par conséquent réduire la durée de vie des puces, également appelée "vieillissement". Afin de relever ces défis, de nouvelles solutions sont nécessaires, basées notamment sur des systèmes auto-adaptatifs. Ces systèmes sont principalement composées d’une boucle de contrôle avec trois processus : (i) la surveillance, qui est chargée d’observer l’état du système, (ii) la prise de décision, qui analyse les informations collectées et prend des décisions pour optimiser le comportement du système et (iii) l’action qui ajuste les paramètres du système en conséquence. Cependant, une adaptation dépendre de façon critique sur le processus de suivi qui devrait fournir une estimation précise sur l’état du système de façon rentable. Dans cette thèse, nous étudions d’abord le suivi de la consommation d’énergie. Nous développons une méthode basée sur plusieurs algorithmes de fouille de données "data mining", pour surveiller l’activité de commutation sur quelques signaux pertinents sélectionnés au niveau RTL. La méthode proposée se compose d’un flot générique qui peut être utilisé pour modéliser la consommation d’énergie pour n’importe quel circuit RTL sur n’importe quelle technologie. Deuxièmement, nous améliorons le flot proposé pour estimer le comportement thermique globale de puce et de développer une nouvelle technique de placement des capteurs thermique sur puce. Les algorithmes proposés choisissent systématiquement le meilleur compromis entre la précision de l’observation et le coût représenté par le nombre de capteurs intégrés sur puce. La surface de la puce est décomposée en plusieurs zones thermiquement homogènes.Outre la partie conception, les systèmes embarqués modernes intègrent des capteurs matériels (analogiques ou numériques) qui peuvent être utilisés pour surveiller l’état du système. Ces méthodes industrielles sont généralement très coûteuses et nécessitent un grand nombre d’unités pour produire des informations précises avec une résolution à grain fin. Une solution alternative pour fournir une estimation précise de l’état du système est réalisée avec un ensemble de compteurs de performance qui peut être configuré pour effectuer le suivi des événements logiques à différents niveaux. Dans ce cas, nous proposons un nouvel algorithme pour la sélection des événements performance pertinents à partir des ressources locales, partagées et système. Nous proposons ensuite une implémentation d'un algorithme d'estimation basé sur un réseau neuronal. La méthode proposée est robuste contre les variations de température extérieure. En outre, estimation thermique est aussi peut être réalisé en utilisant les événements logiques actuelles et historiques, et la précision est évaluée sur la base de la profondeur dans le passé.Enfin, une fois la méthode de suivi et la cible définies et le système est configuré, la méthode de surveillance doit être utilisée au moment de "Run-time". Nous avons mis en place une boucle d’adaptation complète, avec un suivi dynamique de l’état du système afin atteindre une meilleure efficacité énergétique. / Over the last decade, the miniaturization of semiconductor technologies and the large-scale integration has given rise to complex system design, including the integration of several billions of transistors on a single die. This trend poses many manufacturing and reliability challenges such as power dissipation, technological variability and application versatility. The reliability issues represented by the presence of thermal hotspots can accelerate the degradation of the transistors, and consequently reduce the chip lifetime, also referred to as “aging”. In order to address these challenges, new solutions are required, based in particular on self-adaptive systems. Such systems are mainly composed of a control loop with three processes: (i) the monitoring, which is responsible for observing the state of the system, (ii) the diagnosis, which analyzes the information collected and makes decisions to optimize the behavior of the system, and (iii) the action that adjusts the system parameters accordingly. However, effective adaptations depend critically on the monitoring process that should provide an accurate estimation about the system state in a cost-effective manner. In this thesis, we firstly investigate the monitoring of the power consumption. We develop a method, based on several data mining algorithm, to monitor the toggling activity on a few relevant signals selected at the RTL level. The proposed method consists of a generic flow that can be used to model the power consumption for any RTL circuit on any technology. Secondly, we improve the proposed flow by estimating the overall chip thermal behavior and developing a new technique of on-die thermal sensor placement. The proposed algorithms systematically choose the best trade-off between accuracy and overhead. The surface of the chip is decomposed into several thermally homogeneous regions.Besides the design part, modern embedded systems integrates hardware sensors (analog or digital) that can be used to monitor the system’s state. These industrial methods are usually very expensive, and require a large number of units to produce precise information at a fine-grained resolution. An alternative solution to provide an accurate estimation of system’s state is achieved with a set of performance counters that can be configured to track logical events at different levels. To this end, we propose a novel algorithm for the selection of the relevant performance events from the local, shared and system resources. We propose then an implementation of a neural network based estimation algorithm. The proposed method is robust against the external temperature variations. Furthermore, thermal estimation is also can be achieved using the current and historic logical events, and the accuracy is evaluated on the basis of the depth in the past.Finally, once the tracking method and target are defined and the system is configured, the monitoring method should be used at “Run-time”. We implemented a complete adaptation loop, with a dynamic monitoring of the system’s state in order to achieve better energy efficiency.

Les circuits modernes sont de plus en plus sensibles aux variations technologiques et environnementales qui n'ont plus seulement un effet global sur les circuits mais aussi un effet local sur ceux-ci.Dans ce contexte, les composants reprogrammables que sont les FPGA représentent un support technologique intéressant. En effet, ces composants permettent d'adapter l'implantation physique du système grâce à une simple reconfiguration du circuit.C'est pourquoi, dans ce manuscrit, nous présentons un flot d'adaptation complet visant à compenser les variations des circuits. Pour cela, une étude de toutes les phases de conception des capteurs numériques est réalisée. Nous proposons ensuite une approche originale et unique de caractérisation basée sur l'analyse électromagnétique. Il est notamment montré que cette approche permet de se défaire des biais de mesure engendrés par les méthodes de mesure directe. L'utilisation conjointe des capteurs et de cette méthode d'analyse permet une caractérisation fine et précise des variations technologiques de n'importe quel type de circuit FPGA.Enfin, la cartographie issue de la phase de caractérisation permet ensuite de calibrer les capteurs pour une utilisation en ligne. Nous utilisons donc ensuite ces capteurs pour le monitoring dynamique d'un système MPSOC. / Modern circuits are more and more sensitive to environmental and technology changes.In this context, reprogrammable components like FPGAs represent an interesting technological support. Indeed, these components can adapt the physical layout of the system through a simple reconfiguration of the circuit.In this manuscript, we present a comprehensive adaptative flow to compensate the variations in circuits.For this, a study of all phases of digital sensor design is realized. We then propose a novel and unique characterization approach based on the electromagnetic analysis. It is particularly shown that this approach allows to get rid of measurement bias caused by direct measurement. The joint use of sensors and the method of analysis allows a detailed and accurate characterization of technological variations of any type of FPGA.Finally, the cartography issued from the characterization phase is then used to calibrate the sensors for online use. Then, we employ these sensors for monitoring the dynamics of a system MPSOC.

Avec la réduction continue des dimensions des transistors CMOS, le développement des mémoires statiques du type SRAM énergétiquement efficientes et de hautes densités devient de plus en plus difficile. Les dernières années ont vu l'apparition de nouvelles technologies de mémoire, qui ont attiré l'intérêt de la communauté académique, ainsi que de nombreux acteurs industriels. Parmi ces technologies, la STT-MRAM se distingue pour ses caractéristiques très avantageuses, comme sa faible consommation, ses performances et sa facilité d'intégration dans une technologie de fabrication CMOS. En plus, les MRAMs sont des technologies non-volatiles, avec une endurance élevée, nous allons utiliser cette caractéristique pour proposer de nouvelles fonctionnalités aux systèmes intégrés, notamment sur les architectures de processeur et les dispositifs reconfigurables.Une comparaison entre plusieurs amplificateurs de lecture, utilisables pour concevoir des matrices de mémoire et des cellules séquentielles a été aussi menée. Afin de démontrer la faisabilité de la conception hybride CMOS/MRAM plusieurs prototypes ont été conçus sur une technologie 28nm CMOS FDSOI et une technologie magnétique capable de produire des MTJ perpendiculaires STT de 200nm. Nous avons appliqué ces briques de base au monde du processeur notamment en proposant un processeur capable de conserver un état sain lors d'une erreur d'exécution. Les résultats obtenus confirment que le surcout de ces techniques est tout à fait compatible avec la démarche de conception d'un circuit intégré actuel. / With the downscaling of the CMOS technology, it is becoming increasingly difficult to design power-efficient and dense static random-access memories (SRAM). In the last two decades, alternative memory technologies have been actively researched both by academia and industry. Among them, STT-MRAM is one of the most promising, having near-zero static power consumption, competitive performance with respect to SRAM and easy integration with CMOS fabrication processes. Furthermore, MRAM is a non-volatile memory technology, providing for new features and capabilities when embedded in reconfigurable devices or processors. In this thesis, applications of MRAM to embedded processors and field-programmable gate-arrays (FPGAs) were investigated. A comparison of several self-referenced read circuits, with application for both memory arrays and sequential cells is provided, based on MTJ compact models provided by our project partners. To demonstrate the feasibility of the proposed circuits, we laid-out and fabricated independent, self-contained sequential cells and a hybrid, multi-context CMOS/MTJ memory array, using state-of-the-art 28nm FDSOI CMOS technology, combined with a 200nm perpendicular STT-MTJ process. Finally, we used these building blocks to implement instant on/off and backward-error recovery capabilities in an embedded processor. Results obtained by simulation allowed us to verify that these features have minimal impact on performance. An initial layout implementation allowed us to estimate the impact on silicon footprint, which could be further reduced by improvements in the MTJ integration process.