TO achieve high level of integration in order to reduce cost, heterodyne architecture has made way for low-IF and zero-IF (direct conversion) receiver architectures. However, a very serious issue in implementing both zero and low-IF receiver is of local oscillator (LO) pulling. Another challenge is on-chip generation of high-precision quadrature LO signals for image-rejection. We have addressed both these issues in this thesis. Regarding the first problem, we have developed a lowpower frequency multiplication technique which uses a low frequency ring oscillator and multiplies its frequency in power e cient way to generate the desired frequency. We then use this differential LO signal to generate high-precision quadrature phases by using polyphase filter and an injection-locked quadrature oscillator. Design examples are presented for 2.4 GHz band of IEEE 802.15.4 standard which is a low-data rate WPAN standard. The standard o ers relaxed performance specifications in order to help achieve low power of operation. Contributions in the thesis • The problem of local oscillator (LO) pulling can be addressed by running LO at a much reduced frequency and use a frequency multiplier (FM) to generate the desired frequency. Also, use of low-frequency LO saves power in VCO and helps eliminate first few dividers leading to significant power savings. In addition, the entire frequency synthesizer can be run at a lower supply voltage saving additional power. The frequency multiplier involves combining edges from the lower frequency ring oscillator. It improves upon the prior work by proposing a new lower-power edge-combiner. The overall power is reduced by exploiting the relaxed phase noise specification of IEEE 802.15.4 standard. Simulations using SpectreRF show that the circuit consumes only 550 ｵW of power in 0.13 ｵm RF-CMOS technology with 1.2 V supply voltage, and provides 950 VP-P sinusoidal output with phase noise of -85.5 dBc/Hz at 1 MHz offset. • An injection-locking based quadrature desensitization circuit is designed for precision quadrature generation. The differential (two phase) output of the frequency multiplier is fed to a polyphase filter to generate nearly quadrature signals. Output of polyphase filter is in turn fed to the desensitizer circuit to obtain high-precision quadrature signals. Designed for 2.4 GHz band in 0.13 µm RF-CMOS technology, it achieves a phase error of 0.5 for 1% mismatch in LC tanks. It achieves a phase noise of -84.3 dBc/Hz at 1 MHz o set and provides quadrature sinusoids of 475 mV amplitude while consuming 1.56 mW of power. • We have analyzed the popular cross-coupled LC-VCOs to generate quadrature sinusoids. In practical LC-oscillators built using low/moderate quality factor on-chip inductors, the actual frequency of oscillation is a little less than 1/2pvLC . This is known as Groszkowski effect. On the other hand, in quadrature oscillator topologies, consisting of two, cross-coupled, negative resistance LC-VCOs using parallel coupling transistors, an upward shift in frequency of oscillation from the free-running frequency of each LC-VCO is observed. This is because in order to satisfy the Barkhausen’s criteria, the LC-tanks have to operate at a frequency away from the frequency of resonance. This e ect called as quadrature detuning effect results in higher phase noise and reduced amplitude. We have shown that the old treatment given in literature is quite inaccurate for practical LC oscillators that are built using low/mo derate Q on-chip inductors. Also the prior work ignores Groszkowski effect which could be significant for low Q LC tanks. We have provided simple, accurate and closed-form expressions of associated frequency-shifts and amplitude of oscillation including both the effects. Our results show excellent match with results obtained from SpectreRF and Matlab simulations.

Les applications microélectroniques telles que les communications sans fil ou les radars nécessitent des traitements d’information avec des débits ou des résolutions de plus en plus élevés. Cela implique de travailler à des fréquences millimétriques voir sub-millimétriques. Grâce aux progrès des technologies silicium, des circuits intégrés travaillant dans les gammes de fréquences millimétriques émergent mais souffrent d'un manque de solution de caractérisation complète. Par exemple, il n’existe à ce jour aucun analyseur vectoriel de réseaux commercial qui soit capable de mesurer les paramètres S dans la bande G (140-220 GHz) en 4 ports. La caractérisation classique des circuits millimétriques en n ports (avec n>2) consiste alors à utiliser un analyseur vectoriel de réseaux 2 ports et à adapter les autres ports non utilisés à 50Ω. Par permutation circulaire, on arrive ainsi à extraire la matrice S d’un dispositif à n ports (avec n>2). Ce protocole de mesure est très long et délicat à mettre en place car il nécessite d’une part un investissement en appareil de mesure très couteux aux fréquences millimétriques et d’autre part de mettre en œuvre des méthodes de calibrage et de de-embedding précises et dédiées.Le travail développé dans le cadre de cette thèse a visé à intégrer dans la puce, des systèmes de caractérisation petits signaux (paramètres S) au plus près du Dispositif Sous Test (DST). Le fait d’être au plus près du DST permet de réduire les pertes d’insertion, de réduire l’amplitude des vecteurs d’erreurs et donc les erreurs résiduelles après calibrage. Par ailleurs, il est possible de mieux contrôler la puissance du signal envoyé et de considérer des méthodes de calibrage utilisant des charges intégrées, ce qui permet de réduire le temps de traitement et le cout. La technologie utilisée est la technologie SiGe BiCMOS 55 nm développée par la société STMicroelectronics, technologie particulièrement adaptée aux circuits en bande millimétrique. La solution développée dans cette thèse consiste à connecter le wafer avec des pointes de mesure qui amènent un signal hyperfréquence balayant le spectre 35-55 GHz. Une fois dans la puce, ce signal hyperfréquence est quadruplé en fréquence et amplifié afin d’atteindre des niveaux de puissance suffisant (bon rapport Signal/bruit) dans la bande G aux bornes du DST. Les paramètres de réflexion (S11 et S22) sont ensuite extraits grâce à deux coupleurs très directifs, placés sur l’entrée et la sortie du DST respectivement. Les sorties du coupleur sont ensuite ramenées en basse fréquence (0.5GHz < IF < 2.4 GHz) par l’intermédiaire de mélangeurs de fréquence.L’approche choisie est argumentée en se basant sur une étude des systèmes de mesures existant présentée dans la première partie de ce manuscrit. Puis la conception et la caractérisation de chacun des blocs composant le système sont détaillées : le quadrupleur de fréquence en bande G (constitué d’un doubleur de fréquence en bande W cascadé avec un doubleur de fréquence en bande G), le transfert switch en bande G permettant de commuter entre l’entrée et la sortie du DST, le coupleur directif à ondes lentes, les mélangeurs permettant de ramener les mesures en basse fréquence, etc…. Une fois tous les différents blocs présentés, le manuscrit aborde les deux systèmes de mesure conçus. Un premier système un port a été développé pour valider cette approche. Le second système conçu permet de mesurer un DST à deux ports (HBT). Ce second système conserve l’architecture hétérodyne du premier, intégrant en plus un transfert switch en bande G qui dirige le signal incident vers l’un des deux ports du DST. / Microelectronic applications such as wireless communications, radar or space detections require higher data rate resolutions, implying the use of millimeter wave and submillimeter frequencies. Thanks to the silicon technologies improvement, some microelectronic circuits are emerging working in the frequency range of 140-220 GHz (G-band) but they suffer from a lack of complete characterization tools involving costly investment. For example, there is currently no commercial vectorial network analyser (VNA) that can measure S parameters in the 4-ports G-band. The classical characterization of millimeter wave circuits in n ports (with n> 2) consists in using a vectorial analyzer of 2-ports networks and matching the other unused ports to 50Ω. By circular permutation, one thus manages to extract the S matrix from a device with n ports (with n> 2). This set up induces very long and difficult measurements and it requires on the one hand some very expensive measuring equipment at millimeter frequencies and on the other hand to implement accurate and dedicated calibration and de-embedding methods.Therefore, the work developed into this PhD study aimed to integrate in the die the measurement systems that would measure small signals "S-parameters" of the device under test (DUT). Being closer to the DST makes it possible to reduce the insertion losses, to reduce the amplitude of the error vectors and thus the residual errors after calibration. Moreover, it is possible to better control the power of the signal sent and to consider calibration methods using integrated loads, which reduces the time and cost processing. The technology used is the SiGe BiCMOS 55 nm technology developed by STMicroelectronics, a technology dedicated to RF and millimeter wave’s circuits.The system developed is a 1-port system. The solution developed consists on connecting the wafer with some probes and driving it with an external signal that spans the 35-55 GHz band. Once into the die, this signal is then quadrupled in frequency and amplified to reach good power level in G band at the DUT inputs. Some S-parameters (S11 and S22) are extracted from the DUT thanks to some very directive couplers designed respectively at the input and at the output of the DUT. The outputs of the couplers are then converted to low frequencies (IF =0.5-2.4 GHz) through passive frequency mixers.In a first part of the thesis manuscript, the way to work is argued, supported by a study of the state of the art concerning the measurement systems. Then, design and characterization of each blocks of the system are detailed: the frequency quadrupler in G band (composed of a W band frequency doubler, followed with a G band frequency doubler), the fully integrated transfer switch in G-band allowing driving the millimeter waves signal to the DUT input or to the DUT output, the directive couplers based on the slow wave lines, the frequency mixers used to bring back the results in base band frequency, etc… All the different blocks detailed, the measurement systems can be introduced. A first system, a one-port measurement system, has been designed as a proof of concept. Once the approach validated, a second system, two-ports measurement system, has been developed presenting an heterodyne architecture and a transfer switch in G band driving the input signal toward the DUT input or output.

This thesis deals with problematics of direct frequency digital synthesis. Principle and basic characteristics of this method of signal generating are explained in the introduction. It considers impact on purity of spectrum of output signal. Next chapter considers conception of the generator, namely choice of DDFS circuit and other basic blocks. Design of frequency multiplier, reconstruction filter and power amplifier are included. It also deals with choice of control circuit. The device is controlled by computer through USB. There was created user programme for this purpose. Measured characteristics are stated at the end of the work. This work includes schemes of connetions of designed parts including simulations and measured parameters.

The Asymmetric Spacer layer Tunnel (ASPAT) diode is a new diode invented in the early 90s as an alternative to the Schottky barrier diode (SBD) technology for microwave detector applications due to its highly stable temperature characteristics. The ASPAT features a strong non-linear I-V characteristic as a result of tunnelling through a thin barrier, which enables RF detection at zero bias from microwaves up to submillimetre wave frequencies. In this work, two heavily doped GaAs contact layer on top and bottom layers adjacent to lightly doped GaAs intermediate layers, enclose undoped GaAs spacers with different lengths sandwiching an undoped AlAs layer that acts as a tunnel barrier. The ultimate ambition of this work was to develop a MMIC detector as well as a frequency source based on optimized ASPAT diodes for millimetre wave (100GHz) applications. The effect of material parameter and dimensions on the ASPAT source performances was described using an empirical model for the first time. Since this is a new device, keys challenges in this work were to improve DC and RF characteristic as well as to develop a repeatable, reproducible, and ultimately manufacturable fabrication process flow. This was investigated using two approaches namely air-bridge and dielectric-bridge fabrication process flows. Through this work, it was found that the GaAs/AlAs heterostructures ASPAT diode are more amenable to the dielectric-bridge technique as large-scale fabrication of mesa area up to 4×4Âμm2 with device yields exceeding 80% routinely produced. The fabrication of the ASPAT using i-line optical lithography which has the capability to reduce emitter area to 4×4Âμm2 to lower down the device capacitance for millimetre wave application has been made feasible in this work. The former challenge was extensively studied through materials and structural characterisations by a SILVACO physical modelling and confirmed by comparison with experimental data. The I-V characteristic of the fabricated ASPAT demonstrated outstanding scalability, demonstrating robust processing. A fair comparison has been made between ASPAT and SBD fabricated in-house; indicating ASPAT is extremely stable to the temperature. The RF characterisations were carried out with the aid of Keysight ADS software. The DC characteristic from fabricated GaAs/AlAs ASPAT diodes were absorbed into an ADS simulation tool and utilized to demonstrate the performance of MMIC 100GHz detector as well as 20GHz/40GHz signal generators. Zero bias ASPAT with mesa area of 4×4Âμm2 with video resistance of 90KΩ, junction capacitance of 23fF and curvature coefficient of 23V-1 has demonstrated detector voltage sensitivity above 2000V/W, while the signal source conversion loss and conversion efficiency are 28dB and 0.3% respectively. An estimate noise equivalent power (NEP) for this particular device is 18.8pW/Hz1/2.

Cette thèse porte sur l’analyse et la conception de générateurs de fréquence millimétrique à faible bruit de phase destinés à des applications de communication sans fil de très haut débit sur une technologie BiCMOS 0.25m. Spécifiquement, des applications backhauling sont visées sur le protocole de communication P2P (point-to-point), pour un système de radio hétérodyne (à faible fréquence intermédiaire) approprié pour les bandes entre 30–38GHz et de faible profondeur de modulation (2-3 bits /symbole). Une étude rigoureuse du comportement du bruit de phase en 1/f2 d’un oscillateur contrôlé en tension (du type paire différentielle croisée) en fonction de la fréquence d’oscillation est développée. Des facteurs essentiels pour la conception de ces oscillateurs tels que la plage de fréquence et la charge de la paire croisée sur le résonateur sont pris en compte dans l’analyse. L’étude révèle que lorsque la fréquence augmente, l’oscillateur passe à travers deux régimes d’opération différents, ici appelés région QL-limited et région QC- limited, qui résultent de la dépendance du facteur de qualité du résonateur à sa partie inductive (pour les basses fréquences d’oscillation) et sa partie capacitive (pour les hautes fréquences d’oscillation). De plus, l’impact de la plage de fréquence sur l’évolution du bruit de phase en 1/f2 a été considéré en utilisant un circuit classique à base d’un varactor et d’un condensateur du type MiM. Des équations simples et précises ont été calculées pour les paramètres du circuit afin d’obtenir une fréquence centrale souhaitée avec la variation de la capacité requise. Pour ce circuit, il a été démontré (et vérifié à travers des simulations du circuit) que le pire scénario du facteur de qualité peut être associé à la constante de temps d’un condensateur. Ce dernier a permis d’estimer aisément le facteur de qualité minimal de la partie capacitive du résonateur LC de l’oscillateur, pour une plage de fréquence donnée, en fonction de la fréquence d’oscillation. D’une manière similaire, et basée sur une analyse à petit signal, la constante de temps de la capacité de sortie de la paire croisé a été déterminée. Notamment cette constante de temps présente un comportement constant sur une large gamme de fréquences, ce qui permet d’évaluer facilement son facteur de qualité. Cette étude fournit les bases théoriques qui permettent l’évaluation du bruit de phase en 1/f2 d’une source de signal basée sur un oscillateur en mode fondamental, super-harmonique ou sous-harmonique. En effet, la supériorité des oscillateurs sous-harmoniques est démontrée et des équations simples sont proposées pour déterminer la performance maximale et les conditions dans lesquelles elles peuvent être atteintes. Enfin, un système de génération de signal est ainsi conçu et vérifié par des mesures sur un prototype. Le système est composé d’un VCO sous-harmonique suivi d’un tripleur de fréquence (ILFT) –verrouillé par injection. Le circuit est implémenté sur une technologie SiGe:C BiCMOS 0.25 m. Le tripleur implémente une configuration à émetteur commun, polarisé en courant, qui exploite la seconde harmonique du VCO afin d’améliorer l’efficacité de la génération du signal responsable de verrouiller le ILFT. A 30.8 GHz, le système atteint un bruit de phase de -112 dBc/Hz à 1MHz d’offset. La consommation totale de courant est de 38mA pour une tension d’alimentation de 2.5V. Un deuxième prototype a été réalisé pour un système de génération multibande, offrant ainsi trois sorties RF à 18 GHz, 34GHz et 68 GHz. Avec une plage de fréquence de 10% (mesurée par rapport à la fréquence centrale) pour chaque sortie RF. Le bruit de phase mesuré à 1MHz d’offset est respectivement de -113dBc/Hz, -107dBc/Hz et -100dBc/Hz.. / This thesis deals with the analysis and design of Low phase Noise Local-Oscillator(LO) sources suitable for backhauling applications on the frequencies 30-38GHz. The LO is intended to be used in a low-IF architecture for low order modulations (2-3 bits/symbol). This work was developed in collaboration with NXP Semiconductorsat CAEN, France, within the project RF2THz of the European program CATRENE.The original contributions in this work include a rigorous study of the 1/f2 phasenoise characteristics of the VCO (bipolar cross-coupled pair Voltage-Controlled-Oscillator) with the oscillating frequency. Key factors in the design of VCOs such as tuning range and the tank load given by the cross-coupled pair are considered in the analysis. The study reveals that as the frequency scales, the VCO passes through two different zones, named the QL-limited and the QC-limited region, that results from the dependence of the resonator quality factor on its inductive part (for low oscillating frequencies) and its capacitive part (for high oscillating frequencies). Moreover, the impact of the tuning range on the 1/f2 phase noise evolution was captured by using a classical circuit based on an AC-coupled varactor and a MiM capacitor. Simple and accurate equations were derived for the circuit parameters in order to achieve a desired central frequency with the required capacitance variation. For this circuit, it is demonstrated (and verified through circuit simulations) that the lowest quality factor scenario can be associated to the time-constant of a lossy capacitor. The latter allows to estimate easily the minimum quality factor of the capacitive part of the VCO LC tank, for a given tuning range, as a function of the oscillating frequency. In a similar way, and based on a small signal analysis, the time-constant of the output capacitance of the bipolar cross-coupled pair was derived. Interesting, this time constant shows a constant behavior over a wide frequency range, thereby allowing to estimate easily its quality factor. This study set the bases for an analytical framework that enables the evaluation of the 1/f2 phase noise performances of local oscillator sources working either on fundamental,super-harmonic or sub-harmonic mode. The superiority in terms of 1/f2 phase noise of local oscillators based on sub-harmonic oscillators is thus demonstrated and simple equations are derived to determine the maximum performance and the conditions on which this can be achieved. Finally, a signal generation system intended for a low-IF point-to-point fixed radio system in the Ka-Band band is thus designed and verified through prototype measurements.The system is composed by a sub-harmonic VCO followed by an injectionlocked frequency tripler (ILFT) and it is designed in a 0.25m BiCMOS SiGe:C technology. The ILFT implements a cascode current-biased common emitter configuration that exploits the second harmonic of the VCO to enhance the efficiency in the generation of the injecting signal responsible for the ILFT locking. At 30.8GHz, the system achieves a phase noise of -112dBc/Hz at 1MHz offset. The total current consumption is 38mA for a supply voltage of 2.5V. A second prototype is designed for a multiband LO generation, providing thus three RF outputs at 18GHz, 34GHz and 68GHz. With a measured tuning range of 10% for each RF output, the measured phase noise at 1MHz is -113dBc/Hz, -107dBc/Hz and -100dBc/Hz respectively.

This work deals with the analog multipliers, mainly of the voltage multipliers. Also the modifications of current output will appear here. The first part is devoted to a choice several multipliers and a description of their functions, the possible involvement and introduction of the most important catalog values. The next section deals with the simple application that contains at least one of the multipliers. Next was the implementation of selected applications and measure their actual performance parameters. Results are then compared with computer simulations. As final step is done of tolerance and sensitivity analysis of simulated configurations of circuits.

This thesis presents the analysis, design and characterization of an integrated high-frequency phase-locked loop (PLL) frequency multiplier. The frequency multiplier is novel in its use of a low multiplication factor of 4 and a fully differential topology for rejection of common mode interference signals. The PLL is composed of a voltage controlled oscillator (VCO), injection-locked frequency divider (ILFD) for the first divide-by-two stage, a static master-slave flip-flop (MSFF) divider for the second divide-by-two stage and a Gilbert cell mixer phase detector (PD). The circuit has been fabricated using a standard CMOS 0.18-um process based on its relatively low cost and ready availability. The PLL frequency multiplier generates an output signal at 26 GHz and is the highest operational frequency PLL in the technology node reported to date. Time domain phase plane analysis is used for prediction of PLL locking range based on initial conditions of phase and frequency offsets. Tracking range of the PLL is limited by the inherent narrow locking range of the ILFD, and is confirmed via experimental results. The performance benefits of the fully differential PLL are experimentally confirmed by the injection of differential- and common-mode interfering signals at the VCO control lines. A comparison of the common- and differential-mode modulation indices reveals that a common mode rejection ratio (CMRR) of greater than 20 dB is possible for carrier offset frequencies of less than 1 MHz. Closed-loop frequency domain transfer functions are used for prediction of the PLL phase noise response, with the PLL being dominated by the reference and VCO phase noise contributions. Regions of dominant phase noise contributions are presented and correlated to the overall PLL phase noise performance. Experimental verifications display good agreement and confirm the usefulness of the techniques for PLL performance prediction. The PLL clock multiplier has an operational output frequency of 26.204 to 26.796 GHz and a maximum output frequency step of 16 MHz. Measured phase noise at 1 MHz offset from the carrier is -103.9 dBc/Hz. The PLL clock multiplier core circuit (VCO/ILFD/MSFF Divider/PD) consumes 186 mW of combined power from 2.8 and 4.3 V DC rails. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2009-04-24 11:31:35.384

The main aim of the thesis is to develop a solution of a frequency synthesizer for a microwave communication systems. Specifically, it suggests a design for frequency synthesizer with phase-locked loop. At beginning of the thesis the principle and basic properties of this method of signal generation are explained. Then it is followed by a brief discussion of the parameters of synthesizers and their influence on design. Another part of the work is the analysis of circuit the frequency synthesizer with the phase-locked loop MAX2871, which is followed by a proposal for the design of the frequency synthesizer module hardware. The last part of the work deals with practical implementation, verification of function and measurement of achieved parameters and their evaluation.