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BACKGROUND: Chronic ankle instability (CAI) patients have varying levels of mechanical and sensorimotor impairments that may lead to disparate functional movement patterns. Current literature on landing biomechanics in a CAI population, however, considers all patients as a homogeneous group. In our prior work, we identified 6 subgroups of movement patterns using lower extremity kinematics during a landing/cutting task and that showed promise in furthering understanding of movement patterns in a laboratory-based environment. To increase the utility of this methodology in clinical settings, there is a need to find easily administered clinical tests that can help identify multiple subgroups of movement patterns in a CAI population. The purpose of the present study was to identify clinical tests that would help identify frontal and sagittal kinematic movement pattern subgroups during a landing/cutting task. We hypothesized that clinical tests would help predict group assignment; which CAI patient is assigned to frontal and sagittal kinematic movement pattern subgroups, respectively. METHODS: We recruited 100 CAI patients from a university population. We used three-dimensional instrumented motion analysis to capture ankle, knee and hip kinematics as subjects performed a single-leg maximal jump landing/cutting task. We used sagittal and frontal joint angle waveforms to group CAI patients. We then used 12 demographic and clinical measures to predict these subgroups of CAI. These consisted of gender, Star Excursion Balance Test-Anterior (SEBT-ANT), Biodex static balance, figure 8 hop, triple crossover hop, dorsiflexion range of motion (DFROM), number of failed trials, body mass index, a score of Foot and Ankle Ability Measure-Activities of Daily Living (FAAM-ADL), a score of FAAM-Sports, number of "yes" responses on Modified Ankle Instability Index, and number of previous ankle sprains. First, we used functional principal component analysis to create representative curves for each CAI patient and plane from the 3 lower extremity joint angles. We then used these curves as inputs to a predictor-dependent product partition model to cluster each CAI patient to unique subgroups. Finally, we used a multinomial prediction model to examine the accuracy of predicting group membership from demographic and clinical metrics. RESULTS: The predictor-dependent product partition model identified 4 frontal and 5 sagittal movement pattern subgroups. Six predictors (e.g., gender, SEBT-ANT, figure 8 hop, triple crossover hop, DFROM, and FAAM-ADL) predicted group membership with 55.7% accuracy for frontal subgroups. Ten predictors (minus Biodex static balance and number of previous ankle sprains) predicted group membership with 59% accuracy for sagittal subgroups. CONCLUSION: Novel statistical analyses allowed us to predict group membership for multiple frontal and sagittal kinematic movement patterns during landing/cutting using a series of clinical predictors. However, due to relatively lower accuracy (56–59% accuracy), the clinical utility of the current prediction model may be limited. Future work should consider including other clinical predictors to maximize prediction accuracy for identifying multiple kinematic movement patterns during a landing/cutting task.

Integrated circuits, from general purpose microprocessors to application specific designs (ASICs), have become ubiquitous in modern technology. As our applications have become more complex, so too have the circuits used to drive them. Moore's law predicts that the number of transistors on a chip doubles every 18-24 months. This explosion in circuit size has also lead to significant growth in testing effort required to verify the design. In order to cope with the required effort, the testing problem must be approached from several different design levels. In particular, exploiting the Register Transfer Level for test generation allows for the use of relational information unavailable at the structural level. This dissertation demonstrates several novel methods for generating tests applicable for both structural and functional tests. These testing methods allow for significantly faster test generation for functional tests as well as providing high levels of fault coverage during structural test, typically outperforming previous state of the art methods. First, a semi-formal method for functional verification is presented. The approach utilizes a SMT-based bounded model checker in combination with an ant colony optimization based search engine to generate tests with high branch coverage. Additionally, the method is utilized to identify unreachable code paths within the RTL. Compared to previous methods, the experimental results show increased levels of coverage and improved performance. Then, an ant colony optimization algorithm is used to generate high quality tests for fault coverage. By utilizing co-simulation at the RTL and gate level, tests are generated for both levels simultaneously. This method is shown to reach previously unseen levels of fault coverage with significantly lower computational effort. Additionally, the engine was also shown to be effective for behavioral level test generation. Next, an abstraction method for functional test generation is presented utilizing program slicing and data mining. The abstraction allows us to generate high quality test vectors that navigate extremely narrow paths in the state space. The method reaches previously unseen levels of coverage and is able to justify very difficult to reach control states within the circuit. Then, a new method of fault grading test vectors is introduced based on the concept of operator coverage. Operator coverage measures the behavioral coverage in each synthesizable statement in the RTL by creating a set of coverage points for each arithmetic and logical operator. The metric shows a strong relationship with fault coverage for coverage forecasting and vector comparison. Additionally, it provides significant reductions in computation time compared to other vector grading methods. Finally, the prior metric is utilized for creating a framework of automatic test pattern generation for defect coverage at the RTL. This framework provides the unique ability to automatically generate high quality test vectors for functional and defect level testing at the RTL without the need for synthesis. In summary, We present a set of tools for the analysis and test of circuits at the RTL. By leveraging information available at HDL, we can generate tests to exercise particular properties that are extremely difficult to extract at the gate level. / Ph. D. / Digital circuits and modern microprocessors are pervasive in modern life. The complexity and scope of these devices has dramatically increased to meet new demands and applications, from entertainment devices to advanced automotive applications. Rising complexity causes design errors and manufacturing defects are more difficult to detect and increases testing costs. To cope with rising test costs, significant effort has been directed towards automating test generation early in development when defects are less expensive to correct. Modern digital circuits are designed using Hardware Description Languages (HDL) to describe their behavior at a high logical level. Then, the behavioral description is translated to a chip level implementation. Most automated test tools use the implementation description since it is a more direct representation of the manufactured circuit. This dissertation demonstrates several methods to utilize available logical information in behavioral descriptions for generating tests early in development that maintain applicability throughout the design process. The proposed algorithms utilize a biologically-inspired search, the ant colony optimization, abstracting test generation as an ant colony hunting for food. In the abstraction, a sequence of inputs to a circuit is represented by the walked path of an individual ant and untested portions of the circuit description are modelled as food sources. The final test is a collection of paths that efficiently reach the most food sources. Each algorithm also explores different software analysis techniques, which have been adapted to handle unique constraints of HDLs, to learn about the target circuits. The ant colony optimization uses the analysis to help guide and direct the search, yielding more efficient execution than prior techniques and reducing the time required for test generation. Additionally, the described methods can automatically generate tests in cases previously requiring manual generation, improving overall test quality.

This essay discusses actual situation and method for high pressure pump part testing. Here are possibilities for moving of high pressure leakage test on test benches used for pump functional test. Savings and costs plus return on investment are calculated for testing process change.

With the increasing complexity of modern day processors and system-on-a-chip (SOCs), designers invest a lot of time and resources into testing and validating these designs. To reduce the time-to-market and cost, the techniques used to validate these designs have to constantly improve. Since most of the design activity has moved to the register transfer level (RTL), test methodologies at the RTL have been gaining momentum. We present a novel functional test generation framework for functional test generation at RTL. A popular software-based metric for measuring the effectiveness of an RTL test suite is branch coverage. But exercising hard-to-reach branches is still a challenge and requires good understanding of the design semantics. The proposed framework uses static analysis to extract certain semantics of the circuit and uses several data structures to model these semantics. Using these data structures, we assist the branch-guided search to exercise these hard-to-reach branches. Since the correlation between high branch coverage and detecting defects and bugs is not clear, we present a new metric at the RTL which augments the RTL branch coverage with state values. Vectors which have higher scores on the new metric achieve higher branch and state coverages, and therefore can be applied at different levels of abstraction such as post-silicon validation. Experimental results show that use of the new metric in our test generation framework can achieve a high level of branch and fault coverage for several benchmark circuits, while reducing the length of the vector sequence. This work was supported in part by the NSF grant 1016675. / Master of Science

This thesis presents a novel concolic testing methodology and CORT, a test generation framework that uses it for high-level functional test generation. The test generation effort is visualized as the systematic unraveling of the control-flow response of the design over multiple (factored) explorations. We begin by transforming the Register Transfer Level (RTL) source for the design into a high-performance C++ compiled functional simulator which is instrumented for branch coverage. An exploration begins by simulating the design with concrete stimuli. Then, we perform an interleaved cycle-by-cycle symbolic evaluation over the concrete execution trace extracted from the Control Flow Graph (CFG) of the design. The purpose of this task is to dynamically discover means to divert the control flow of the system, by mutating primary-input stimulated control statements in this trace. We record the control-flow response as a Test Decision Tree (TDT), a new representation for the test generation effort. Successive explorations begin at system states heuristically selected from a global TDT, onto which each new decision tree resultant from an exploration is stitched. CORT succeeds at constructing functional tests for ITC99 and IWLS-2005 benchmarks that achieve high branch coverage using the fewest number of input vectors, faster than existing methods. Furthermore, we achieve orders of magnitude speedup compared to previous hybrid concrete and symbolic simulation based techniques. / Master of Science / In recent years, the cost of verifying digital designs has outpaced the cost of development, in terms of both resources and time. The scale and complexity of modern designs have made it increasingly impractical to manually verify the design. In the process of circuit design, designers use Hardware Descriptive Languages (HDL) to abstract the design in a manner similar to software programming languages. This thesis presents a novel methodology for the automation of testing functional level hardware description with the aim of maximizing branch coverage. Branches indicate decision points in the design, and tests with high branch coverage are able to thoroughly exercise the design in a manner that randomly generated tests cannot. In our work, the design is simulated concretely with a random test (a sequence of input or stimulus). During simulation, we analyze the flow of behavioral statements and decisions executed to construct a formulaic interpretation of the design execution in terms of syntactical elements, to uncover differentiating input that could have diverted the flow of execution to unstimulated parts of the design. This process is formally known as Concolic Execution. The techniques described in this thesis tightly interleaves concrete and symbolic simulation (concolic execution) of hardware designs to generate tests with high branch coverage, orders of magnitude faster than previous similar work.

A presente dissertação deseja mostrar a utilização do estudo de confiabilidade como uma ferramenta de melhoria de projeto de um produto. Para atingir o objetivo estudou-se a melhoria de um retentor automotivo através do estudo de sua confiabilidade e utilizando técnicas de engenharia do valor. Com esse estudo pretende-se mostrar a relação dos dados de campo e ensaios funcionais utilizados. Através da análise dos dados de campo, foi selecionada uma característica funcional a ser melhorada no produto. A técnica de engenharia do valor aplicada ao produto resultou na variável que deveria ser melhorada no produto, e a análise de confiabilidade antes e após a alteração no produto, juntamente com os ensaios funcionais acelerados mostram a eficácia da melhoria realizada no produto. / This research aims to show a way to use the reliability study as a tool to guarantee the improvements in a product design. To reach the goal, a improvement in a oil seal was executed through the study of its reliability and using the value engineer technique. This study aims to show the relationship between the field information and functional tests. Through the analysis of field information, the functional characteristic that must be improved in the product was selected, and the value engineering technique application result in an element that must be improved in a product. The reliability study after and before the change in product, together with functional tests showed the efficiency of the change in the product aimingat improving its operational life.

Testing integrated circuits to verify their operating frequency, known as delay testing, is essential to achieve acceptable product quality. The high cost of functional testing has driven the industry to automatically-generated structural tests, applied by low-cost testers taking advantage of design-for-test (DFT) circuitry on the chip. Traditional at-speed functional testing of digital circuits is increasingly challenged by new defect types and the high cost of functional test development. This research addressed the problems of accurate delay testing in DSM circuits by targeting resistive open and short circuits, while taking into account manufacturing process variation, power dissipation and power supply noise. In this work, we developed a class of structural delay tests in which we extended traditional launch-on-capture delay testing to additional launch and capture cycles. We call these Pseudofunctional Tests (PFT). A test pattern is scanned into the circuit, and then multiple functional clock cycles are applied to it with at-speed launch and capture for the last two cycles. The circuit switching activity over an extended period allows the off-chip power supply noise transient to die down prior to the at-speed launch and capture, achieving better timing correlation with the functional mode of operation. In addition, we also proposed advanced compaction methodologies to compact the generated test patterns into a smaller test set in order to reduce the test application time. We modified our CodGen K longest paths per gate automatic test pattern generator to implement PFT pattern generation. Experimental results show that PFT test generation is practical in terms of test generation time.

Procedimentos de teste para dispositivos eletrônicos tem sido construídos de forma a lidar com problemas, tais como geração de padrões de teste, cobertura de falhas e outros parâmetros tais como custo e tempo. Com o surgimento dos circuitos VLSI (Very Large Scale Integration), tais como os processadores, os problemas do teste tem aumentado. Com relação aos processadores, sua complexidade é um convite para o uso de procedimentos de teste funcionais, ignorando a estrutura física dos circuitos. Adicionalmente, informações sobre a estrutura do processador são geralmente desconhecidas por parte do usuário. No nível funcional, um processador é tratado como um sistema composto por blocos funcionais, cuja descrição pode ser obtida no manual do usuário. Cada bloco e caracterizado pela sua função, como por exemplo, a unidade lógica e aritmética, registradores, memória, etc... Testar o processador consiste em exercitar cada bloco com padrões de teste determinados. A utilização do processador transputer em situações onde se faz necessário um certo nível de confiabilidade depende da utilização de técnicas para detecção on-line. No presente trabalho é proposto um procedimento para o teste funcional do transputer. O teste funcional aqui proposto permite detecção de falhas on-line, em um contexto de aplicação periódica (pela suspensão temporária mas sem alteração do contexto da aplicação do usuário), com baixa degradação no desempenho global do sistema. Hipóteses e procedimentos relacionados a fabricação de circuitos não são considerados. Para possibilitar o uso de técnicas de teste convencionais, o transputer IMS T800 é particionado em blocos funcionais e um modelo para o teste, baseado na organização desse componente, e proposto. Este modelo é apoiado pela similaridade desse processador com um sistema microprocessado. Após o particionamento cada bloco funcional pode ser testado em separado; para os blocos que possuem organização como a de microprocessadores convencionais (tais como parte da CPU e a FPU), utiliza-se como base o método proposto por Robach and Saucier [ROB80]. De acordo com este método de teste funcional, as instruções do processador são modeladas por intermédio de grafos, que formam a base para definição de um conjunto mínimo de instruções. A execução desse conjunto exercita todos os elementos pertencentes ao respectivo bloco funcional do transputer. Entretanto, o procedimento proposto não é uma aplicação direta da metodologia citada, devido a características particulares do transputer, especialmente no que diz respeito ao paralelismo de operações, e sua estrutura de blocos internos. Com relação aos testes on-line, a utilização de um conjunto de instruções reduzido possibilita a realização de um teste rápido, reduzindo perdas de desempenho. Para os blocos restantes, de acordo com suas características, são construídos procedimentos de teste específicos. A freqüência de execução é ajustável para cada bloco. Dependendo das exigências da aplicação, alguns procedimentos podem ser omitidos, reduzindo a carga provocada pelo procedimento de teste no desempenho do sistema. A validação do procedimento de teste é realizada de duas maneiras: injeção de falhas, para verificar a capacidade de detecção: e avaliação de desempenho, para identificar o nível de degradação causado pela utilização do procedimento de teste em um sistema genérico. Apesar desse trabalho ter sido desenvolvido com base na estrutura da maquina TNODE [TEL91] e na abordagem de teste global descrita em [NUN93b], o procedimento de teste proposto pode ser utilizado em qualquer sistema composto por transputers, cujos parâmetros de aplicação se enquadrem nos requisitos usados neste trabalho. / Test procedures for electronic devices have been planned in order to deal with problems as test pattern generation, fault coverage and other parameters as cost and time. With the advent of very large scale integration (VLSI) circuits, such as the microprocessors, the test problems have arised. Concerning processors, their complexity is an invitation to the use of functional test procedures, ignoring the physical structure of the circuit. Further, structural information about the processor is, in general, unknown by users. In a functional level, a processor is seen as a system made up of functional blocks, whose description can be obtained from the user's manual. Each block is characterized by its function, as arithmetic and logic unit, registers, memory, etc... Testing the processor consists of exercising every block with specified test patterns. The use of the transputer processor in situations where reliability is needed depends on the use of on-line detection techniques. In this work, a functional test procedure for the transputer is proposed. The functional test here proposed intends to allow on-line fault detection, in a context of periodical application, with low degradation in global system performance. Hypotheses and procedures related to the fabrication process are not concerned. In order to make possible the use of conventional test techniques, the IMS T800 transputer is partitioned in functional blocks and a test model, based on the architecture of this component, is proposed. This model is supported by the similarity of this processor with a microprocessor system. Then each functional block may be tested in separate; for the blocks that have conventional microprocessor architecture (as part of the CPU and the FPU), the method proposed by Robach and Saucier [ROB80] is used. According to this functional test method, processor instructions are modeled by means of graphs which are the basis to find a minimal instruction set. The execution of this set exercises all elements that belong to the respective functional block of the transputer. Therefore, it is not a straight application of that methodology due to particular characteristics of the transputer, specially concerning the parallelism of operation and its internal blocks structure. Concerning on-line tests, the use of a reduced instruction set allows a fast test realization, reducing the overhead over system performance. For the remainder blocks, specific test procedures are built according to their features. The frequency of execution is adjustable to each block. Depending on the application constraints, some procedures may be omitted, reducing the overhead produced by the test procedure over the system performance. The validation of the test procedure may be done by means of: fault injection, to verify the faults coverage parameters; and performance evaluation, to identify degradation level caused by the inclusion of test procedure in a generic system. Although this work has been developed with basis in the structure of the T-NODE machine [TEL91] and the global test approach described in [NUN93b], it can be used in other transputer systems whose application parameters are similar to those here used.

Procedimentos de teste para dispositivos eletrônicos tem sido construídos de forma a lidar com problemas, tais como geração de padrões de teste, cobertura de falhas e outros parâmetros tais como custo e tempo. Com o surgimento dos circuitos VLSI (Very Large Scale Integration), tais como os processadores, os problemas do teste tem aumentado. Com relação aos processadores, sua complexidade é um convite para o uso de procedimentos de teste funcionais, ignorando a estrutura física dos circuitos. Adicionalmente, informações sobre a estrutura do processador são geralmente desconhecidas por parte do usuário. No nível funcional, um processador é tratado como um sistema composto por blocos funcionais, cuja descrição pode ser obtida no manual do usuário. Cada bloco e caracterizado pela sua função, como por exemplo, a unidade lógica e aritmética, registradores, memória, etc... Testar o processador consiste em exercitar cada bloco com padrões de teste determinados. A utilização do processador transputer em situações onde se faz necessário um certo nível de confiabilidade depende da utilização de técnicas para detecção on-line. No presente trabalho é proposto um procedimento para o teste funcional do transputer. O teste funcional aqui proposto permite detecção de falhas on-line, em um contexto de aplicação periódica (pela suspensão temporária mas sem alteração do contexto da aplicação do usuário), com baixa degradação no desempenho global do sistema. Hipóteses e procedimentos relacionados a fabricação de circuitos não são considerados. Para possibilitar o uso de técnicas de teste convencionais, o transputer IMS T800 é particionado em blocos funcionais e um modelo para o teste, baseado na organização desse componente, e proposto. Este modelo é apoiado pela similaridade desse processador com um sistema microprocessado. Após o particionamento cada bloco funcional pode ser testado em separado; para os blocos que possuem organização como a de microprocessadores convencionais (tais como parte da CPU e a FPU), utiliza-se como base o método proposto por Robach and Saucier [ROB80]. De acordo com este método de teste funcional, as instruções do processador são modeladas por intermédio de grafos, que formam a base para definição de um conjunto mínimo de instruções. A execução desse conjunto exercita todos os elementos pertencentes ao respectivo bloco funcional do transputer. Entretanto, o procedimento proposto não é uma aplicação direta da metodologia citada, devido a características particulares do transputer, especialmente no que diz respeito ao paralelismo de operações, e sua estrutura de blocos internos. Com relação aos testes on-line, a utilização de um conjunto de instruções reduzido possibilita a realização de um teste rápido, reduzindo perdas de desempenho. Para os blocos restantes, de acordo com suas características, são construídos procedimentos de teste específicos. A freqüência de execução é ajustável para cada bloco. Dependendo das exigências da aplicação, alguns procedimentos podem ser omitidos, reduzindo a carga provocada pelo procedimento de teste no desempenho do sistema. A validação do procedimento de teste é realizada de duas maneiras: injeção de falhas, para verificar a capacidade de detecção: e avaliação de desempenho, para identificar o nível de degradação causado pela utilização do procedimento de teste em um sistema genérico. Apesar desse trabalho ter sido desenvolvido com base na estrutura da maquina TNODE [TEL91] e na abordagem de teste global descrita em [NUN93b], o procedimento de teste proposto pode ser utilizado em qualquer sistema composto por transputers, cujos parâmetros de aplicação se enquadrem nos requisitos usados neste trabalho. / Test procedures for electronic devices have been planned in order to deal with problems as test pattern generation, fault coverage and other parameters as cost and time. With the advent of very large scale integration (VLSI) circuits, such as the microprocessors, the test problems have arised. Concerning processors, their complexity is an invitation to the use of functional test procedures, ignoring the physical structure of the circuit. Further, structural information about the processor is, in general, unknown by users. In a functional level, a processor is seen as a system made up of functional blocks, whose description can be obtained from the user's manual. Each block is characterized by its function, as arithmetic and logic unit, registers, memory, etc... Testing the processor consists of exercising every block with specified test patterns. The use of the transputer processor in situations where reliability is needed depends on the use of on-line detection techniques. In this work, a functional test procedure for the transputer is proposed. The functional test here proposed intends to allow on-line fault detection, in a context of periodical application, with low degradation in global system performance. Hypotheses and procedures related to the fabrication process are not concerned. In order to make possible the use of conventional test techniques, the IMS T800 transputer is partitioned in functional blocks and a test model, based on the architecture of this component, is proposed. This model is supported by the similarity of this processor with a microprocessor system. Then each functional block may be tested in separate; for the blocks that have conventional microprocessor architecture (as part of the CPU and the FPU), the method proposed by Robach and Saucier [ROB80] is used. According to this functional test method, processor instructions are modeled by means of graphs which are the basis to find a minimal instruction set. The execution of this set exercises all elements that belong to the respective functional block of the transputer. Therefore, it is not a straight application of that methodology due to particular characteristics of the transputer, specially concerning the parallelism of operation and its internal blocks structure. Concerning on-line tests, the use of a reduced instruction set allows a fast test realization, reducing the overhead over system performance. For the remainder blocks, specific test procedures are built according to their features. The frequency of execution is adjustable to each block. Depending on the application constraints, some procedures may be omitted, reducing the overhead produced by the test procedure over the system performance. The validation of the test procedure may be done by means of: fault injection, to verify the faults coverage parameters; and performance evaluation, to identify degradation level caused by the inclusion of test procedure in a generic system. Although this work has been developed with basis in the structure of the T-NODE machine [TEL91] and the global test approach described in [NUN93b], it can be used in other transputer systems whose application parameters are similar to those here used.