The photoreflectance(PR) and Electroreflectance(ER) of surface-intrinsic-n+ type doped GaAs exhibit many Franz-Keldysh oscillations (FKOs), which enable the electric field (F) to be determined from the technique of the fast Fourier transform (FFT). It is known that F's determined from PR are subjected to photovoltaic effect, but it is difficult to estimate the strength of modulating field (dF) of the pump beam in the PR measurements . Alperovich et. al. have used imaginary part of FFT to determine the strengths of dF's in the ER measurements [V. L. Alperovich, et. al. Appl. Phys . Lett. 71, 2788 (1997)]. Here, we will apply this method to the PR measurements. The dF's thus obtained will be compared with those deduced from photo-voltage measurements. The result shows that the method of Alperovich's can be used to determine the strength of dF in the PR measurements.

This thesis researchs the design of quadrature modulator consists of 120MHz quadrature modulator that is fabricated using hybrid elements and print circuit board (PCB) technology for digital signal generator and quadrature modulator monolithic-microwave integrated-circuit (MMIC) that is fabricated using GaAs heterojunction bipolar transistor (HBT) technology for Personal Communication Service (PCS) applications. The 120MHz quadrature modulator incorporates power divider/combiner, phase shifter and doubly balanced mixer; the design architecture, principle and measurement results of division are presented in this thesis. A quadrature modulator is implemented by combining every division and measures specifications accurately, comparing with that of Agilent ESG-D series digital signal generator with the same carrier frequency and digital modulation. The quadrature modulator MMIC for PCS applications incorporates phase shifter, Gilbert cell mixer, differential to single-ended converter and RF amplifier at output; the design architecture, principle and simulation results of division are presented in this thesis. A quadrature modulator is integrated by combining every division and simulates parameters strictly.For troublesome specification measurement of quadrature modulator, this thesis also presents measurement method and instrument setup detailedly.

It is known that electroreflectance (ER) of surface-intrinsic-n+ type doped GaAs has exhibited many Franz-Keldysh oscillations to enable the application of fast Fourier transform to separate the heavy and light-hole transitions. However each peak still contains two components, which belong to F+ F/2 and F- F/2 respectively, where F is the built-in field and F is the modulating field of applied voltage (Vac). In this work, we have used a larger Vac to modulate the field, and hence the peaks can be further separated. The peak belonging to heavy hole-transition and F- F/2 can be singled out to compare with Airy function-theory.

Inhalt der Arbeit waren die Überprüfung der Leistungsfähigkeit der beiden Verfahren Mikrowellendetektierte Photoleitung (MD-PL) und Mikrowellendetektierte Photo Induced Current Transient Spectroscopy (MD-PICTS) sowie ihre praktische Anwendung auf den Halbleiter GaAs. Zerstörungsfreie Photoleitungs-Wafertopogramme geben Auskunft über die Verteilung des Defekts EL20 bzw. über Widerstand und Ladungsträgerlebensdauer im Volumen eines Wafers bzw. seiner Oberfläche. MD-PICTS-Topographie weiterer Defekte ist möglich. Die Verfahren brachten ein neues Verständnis der bei PICTS ablaufenden Prozesse - die Peakhöhe ist nicht für alle Defekte unmittelbar proportional zur Defektkonzentration. Für die Erklärung positiver und negativer EL2- und EL3-PICTS- Peaks wurde ein Modell entwickelt, nach dem es sich bei diesen Defekten um Rekombinationszentren handelt. Das Modell wurde durch Simulationsrechnungen bestätigt. Ferner entstanden Ergebnisse zum Defekt EL6, an getemperten Wafern und an Epitaxieschichten.

<p>A 5-bit MMIC serial to parallel converter has been designed in Gallium Arsenide. It is intended to be used together with a 5-bit True Time Delay (TTD) circuit, but it can easily be expanded into an arbitrary number of bits. The circuit has been designed with a logic style called DCFL and a 0.20 mm process (ED02AH) from OMMIC has been used to fabricate the circuit. The chip size of this 5-bit MMIC serial to parallel converter is 2.0x0.8 mm (including pads) and close to two hundred transistors are used. Due to the complexity of the transistor models the complete serial to parallel converter has not been fully simulated. However, the smaller building blocks like inverter, latch, etc. have been simulated successfully. These blocks were assembled into the complete circuit.</p>

Title from PDF of title page. / Document formatted into pages; contains 155 pages. / Thesis (M.S.E.E.)--University of South Florida, 2003. / Includes bibliographical references. / Text (Electronic thesis) in PDF format. / ABSTRACT This research effort advances millimeter-wave transistor modeling in a current RF/Microwave circuit simulator (Agilent's Advanced Design System-ADS) for small-signal noise and large signal simulations. The device modeled is a metamorphic High Electron Mobility Transistor (mHEMT) supplied by Raytheon RF components. Because of their structure, these new low noise devices are used in this work to test the abilities to accurately model in the sub 0.5dB noise figure territory and to study model prediction into W-band (75-110 GHz). New modeling issues discussed in this thesis involve the effects of noise modeling in relation to the small-signal model parameters. The noise modeling identifies two methods of extraction and how to determine good noise data. / ABSTRACT: Other modeling topics addressed are the use of an advanced nonlinear model, and the ability to optimize for gain compression in the nonlinear model. Several measurement systems were used in the extraction and validation of this modeling effort. They consist of the ATN NP5 noise system, Maury Automated Tuner System, Agilent's IC-CAP, and Gateway's Special. The concept behind using these systems was to construct a complete modeling reference for a transistor and validate it against noise parameter and nonlinear measured data. Since the modeling work for this thesis is built on previous work, one goal has been to bring past USF field-effect transistor (FET) modeling efforts up to date and refine them for future use. The noise measurements were compared to results from Raytheon to validate the USF ATN noise parameter measurement system. Also the IC-CAP modeling system has been validated in measuring the test devices using the Maury load-pull system. / ABSTRACT: Small-signal and noise modeling were accomplished using techniques standardized from several technical papers and prior USF Ph.D. work relative to the model extraction. The IC-CAP modeling software also provided a straightforward platform for large-signal model extraction that is documented in this thesis. Using optimization in ADS, a final nonlinear was created. Measured DC, S-parameter, noise parameters, harmonic power, TOI, load-pull, and efficiency measurements were shown to compare well with model data simulated in ADS. Temperature scaling was also executed using a linear approximation of model values over measured temperatures in the noise model. The results presented show that the models developed illustrate good fitting of the behavior of the mHEMT device. / System requirements: World Wide Web browser and PDF reader. / Mode of access: World Wide Web.

The integer and fractional quantum Hall effects arise in two-dimensional electron systems subject to low temperature and high perpendicular magnetic field. The phenomenology of these two effects is rich and provides interesting insight into quantum physics. We present two experimental studies of phenomena in the fractional quantum Hall regime. The first examines the tunneling conductance of quasiparticles at filling factor 5/2. This state is of significant interest because it lies outside the traditional Jain hierarchy of fractional quantum Hall states and because it may be the first physical system found to exhibit non-abelian particle statistics. A quantum point contact is used to bring edge states on opposite sides of the system in proximity to each other, allowing quasiparticles to tunnel between the edge states. By annealing the gates forming the quantum point contact at different voltages we control the tunneling strength for fixed temperature and bias. We demonstrate a transition from strong to weak tunneling controlled in this manner. In the weak tunneling regime, the DC bias and temperature dependence of the tunneling conductance is fit to a theoretical form, resulting in values for the quasiparticle charge \(e*\) and the interaction parameter \(g\). The values of these parameters are used to help distinguish between proposed candidate states for the 5/2 wave function. Quantitative and qualitative results are most consistent with the abelian 331 state. Our second main focus is the breakdown of the fractional quantum Hall states at filling factors 4/3 and 5/3. Breakdown of integer and fractional quantum Hall states is known to occur when the Hall and longitudinal resistances deviate from their ideal values at nonzero critical currents. Although multiple studies of breakdown in the integer quantum Hall regime have been reported, corresponding results for the fractional regime are scarce. We observe breakdown over a range of integer states that is consistent with previous results. However, breakdown in the fractional regime is found to exhibit markedly different behavior. In particular, the magnitude of the critical current decreases with increased sample width. This behavior is opposite that observed for integer filling factors and does not seem to be explicable based on current theories of breakdown. / Physics

L'intégration monolithique de matériaux III-V ou Ge sur Si est un enjeu majeur de l'hétéroépitaxie qui a donné lieu à de nombreuses recherches depuis plus de vingt ans. Car premièrement, il permet de combiner des fonctionnalités optoélectroniques au standard industriel CMOS, cela peut remplacer des interconnexions métalliques par des interconnexions optiques dans lescircuits intégrés. De plus, le procédé d'intégration de semiconducteurs III-V ou de Ge sur Si permettrait de réduire sensiblement le coût de fabrication des cellules solaire pour le marché de niche du spatial.L'hétéroépitaxie directe de tels matériaux sur Si n'est pas aisée du fait du fort désaccord de maille et du différent coefficient de dilatation thermique entre ces matériaux. Plusieurs méthodes on tété proposées au cours des 20 derniers, notamment les solutions reposant sur des technologies de report telle que 'Smart Cut TM', 'GEOI condensation' donnent d'excellents résultats, mais n'offre pas autant de souplesse qu'une technologie d'hétéroépitaxie, et induit des coûts nettement supérieurs.L'objectif de cette thèse est de proposer une solution qui consiste à intégrer de façon monolithique des semiconducteurs III-V sur Si en utilisant des couches tampons des oxydes. Nous avons tout d'abord montré de manière théoriquement et expéritalement que pour les systèmes semiconducteur/oxyde, le semiconducteur croît avec son paramètre de maille massif dès le début decroissance et ne contient pas de défaut entendus associé à la relaxation plastique, la différence deparamètre de maille est entièrement accommodée par un réseau de dislocation interfacial. Il est donc apriori possible d'obtenir une couche 2D plane de semiconducteur/oxyde par la coalescence des îlots sans défauts étendus, présentant le paramètre de maille massif du semiconducteur dès le début de lacroissance, a condition qu'aucun défaut ne soit formé lors de la coalescence des îlots.La deuxième partie est dédiée à la coalescence des îlots pour le système InP/SrTiO3/Si, une stratégie de 3-étape a été utilisé pour favoriser la coalescence des îlots InP sur SrTiO3, la couche InPcoalescée présente une très bonne qualité structurale et surfacique. Cependant, nous avons observé la présence de défauts, notamment des micromacles et des parois d'inversion. Malgré ses défauts dans la couche, nous avons réalisé le puits quantique InP/InAsP épitaxié sur SrTiO3/Si, il présente une meilleure qualité cristalline et optique comparé avec un puits quantique référence InP/InAsP qui est épitaxié directement sur Si.

The work presented here report findings in (1) infrared detectors based on p-GaAs/AlGaAs heterojunctions, (2) J and H aggregate sensitized heterojunctions for solar cell and photon detection applications, (3) heterojunctions sensitized with quantum dots as low cost solar energy conversion devices and near infrared photodetectors. (1)A GaAs/AlGaAs based structure with a graded AlGaAs barrier is found to demonstrate a photovoltaic responsivity of ~ 30mA/W (~ 450mV/W) at the wavelength of 1.8 mm at 300K. Additionally the graded barrier has enhanced the photoconductive response at 78 K, showing a responsivity of ~ 80mA/W with a D*=1.4×108 Jones under 1V bias at 2.7 mm wavelength. This is an approximately 25 times improvement compared to the flat barrier detector structure, probably due to the improved carrier transport, and low recapture rate in the graded barrier structure. However, these graded barrier devices did not indicate a photoresponse with photoconductive mode at 300K due to high shot noise. Additionally, two generation-recombination noise components and a 1/f noise component were identified. A series of GaAs/AlGaAs multilayer hetero-junction structures were tested as thermal detectors. A superlattice structure containing 57% Al fraction in the barrier and 3 × 1018 cm-3 p-doped GaAs emitter showed the highest responsivity as a thermal detector with a TCR of ~ 4% K-1, at 300K. (2)The photovoltaic properties of heterojunctions with J-/ H- aggregated dye films sandwiched between n– and p-type semiconductors were investigated for potential application as solar cells and IR detectors. Films of cationic dye Rhodamine-B-thiocyanate adsorbed on Cu2O substrate are found to form organized dye layers by self-assembled J- aggregation, resulting in large red-shifts in the photo -response. Additionally, cells sensitized with a pentamethine cyanine dye exhibited a broad spectral response originating from J- and H-aggregates. The photocurrent is produced by exciton transport over relatively long distances with significant hole-mobility as well as direct sensitized injection at the first interface. (3) A ZnO/PbS-QD/Dye heterostructure had enhanced efficiency compared to ZnO/Dye heterostructure as a solar cell. Furthermore, a ZnO/PbS-QD structure has demonstrated UV and NIR responses with 4×105V/W (390 nm) and 5.5×105 V/W (750 nm) under 1V bias at 300K.

In this thesis we use three main approaches to enhance the performance of terahertz photoconductive switches (THz PC switches). We first propose two novel materials (GaBiAs and carbon nanotubes) for the substrate. The resulting enhancement in THz emission and reception are significant for GaBiAs. As thoroughly analyzed and addressed in Chapter 2, both the emission bandwidth and the emission amplitude of the device are improved by these materials. A systematic study of CNTs predicts 2 orders of magnitude enhancement in THz emission and one order of magnitude enhancement in THz reception. Experimental results for GaBiAs indicate 0.5 THz increase in bandwidth and 68% increase in the emitted THz wave amplitude. The bandwidth enhancement is in comparison to premium commercial devices. The optical excitation of the PC switch is studied and optimized next as the second enhancement approach (Chapter 3). The study presented in Chapter 3 provides an insight on the subwavelength dynamics of the optical excitation E-field at the edge of the electrodes. The study reveals that majority of the fast photocarriers are collected at the edge of the electrode in a subwavelength scale area. This insight leads to optimization of illumination profile and also the third enhancement approach, namely, the enhancement of electrode structure (Chapter 4). In Chapter 4 we have engineered the electrodes down to nanometer scale. This significantly enhances the optical excitation of the substrate and also overcomes the undesired properties of some substrate materials such as long carrier lifetime. Fabricated devices and fabrication processes are assessed in Chapter 5. Results (Chapter 6) highlight more than two orders of magnitude enhancement for nanostructures on GaAs. / Graduate / 0544