Nowadays almost all products used in our daily life are made in pursuit of streamline and good look, including mobiles, motorcycles, aerospace and 3C industry; therefore, how to shorten process time and enhance the smoothness of the product¡¦s surface has become one of the important issues. However, the process method of traditional CNC machines only can support line and circular interpolations but cannot accept motion along curve and circular paths. Therefore, the traditional CNC machines have to rely on CAM, a method to generate the NC code called G-code and M-code by approximating many tiny linear or circular segments, to plan the cutter paths. But this approximating method requires higher transmission speed; it also occupies huge memory capacity and makes the velocity of machine tool discontinuous, in order to difficultly meet the requirement of high speed and better precision. In order to solve the above problems, this thesis adopts the NC code created by CAD/CAM¡¦s NURBS curve which called NURBS-code, making CNC machines have the function of processing NURBS curve interpolations to improve the defect of the traditional processing and thus reach the goal of high speed and better precision. Furthermore, due to NURBS interpolators are always implemented by the controller. This always makes CNC machine become very expensive; meanwhile, adjusting parameters is very troublesome. Therefore this thesis also provides the intergrated method of NURBS and DDA real-time interpolator to make the application in the easy way without the consideration of controller design for AC driver.

This thesis includes two topics. The first topic is a low power design of 8-bit ANT-based pipelining CLA. The second one is a small digital to analog converter (DAC) used in an implantable neural stimulator. An ANT-based low-power 8-bit pipelining carry-lookahead adder (CLA) using two-phase all-N-transistor (ANT) blocks which are arranged in a PLA design style with power-aware pipelining is presented. The pull-up charging and pull-down discharging of the transistor arrays of the PLA are accelerated by two feedback MOS transistors between the evaluation NMOS blocks and the outputs. Both the added power-aware clock control circuit and clock generation circuit detecting data transition take advantage of shutting down the processing stages given identical inputs in two consecutive operations by keeping high clock level. The design keeps the advantage of high speed while having the effect of low power dissipation. The implantable neural stimulator assists patients to reconstruct transmission paths of neural signals by current stimulation. The proposed small DAC not only decreases the chip area and power dissipation by reducing transistor count, but also improves the linearity with higher current output performance. All of measured performances of the proposed DAC make the chip worthy of being implemented in a field application.

In response to the global climate change and environmental protection needs, more and more nations take renewable energies as one of the major future energy policies for its characteristics of clean, low greenhouse gas emission and self-productivity. Among Taiwan¡¦s many renewable energy development, wind energy is always on the list. Wind energy will not only avoid the problems of carbon dioxide which cause greenhouse effect, but also refrain pollution caused by fossil fuel or nuclear energy. The induction generator is a fundamental component of a wind machine. It¡¦s electric port and control can be classified into single fed control and double fed control. Through various comparisons of control and operation, double fed control seems to be more stable at present. Double fed induction generator may continuously produce power at island state without the supply of reactive power from parallel capacitor or the synchronous generator. which is the biggest advantage than single fed induction. , In other words, double fed induction generator may supply power independently. The induction generator is a time-varying and non-linear component. So the traditional rule of scalar control is not adopted in the thesis. The induction generator can be linearized by using vector control, and the power flow can also be directed with the control of its composition of rotor current vector and the controller is designed under the above methodology. The thesis aims to simulate, analyze and compare the steady and transient states of single fed and double fed wind generators with the purposes a more through understanding of the controller and its operation.

The first topic of this thesis is a voltage boost level clamping circuit for a flash memory which utilizes an implicit feedback loop as well as MOS transistors with different threshold voltages. The proposed design can be added to charge pumps to stabilize the output voltage. The unwanted output voltage spikes introduced by the linear pumping ratio are prevented. Not only are possible damages to memory cores avoided, the power disspation is reduced in contrast with prior regulator methods. The second topic is a switch-current 3-bit CMOS wideband random signal generator, which utilizes a digital normalizer to flatten the distribution of the probability in the entire range of B parameter. The ¡§colored¡¨ random numbers problem in prior designs is resolved. In addition, the coefficients of the proposed design are dynamically adjustable.

Significant quantities of hydrocarbons are found in complex salt environments. One of the modern challenges of exploration and production activities is to image below salt. This challenge arises from the complexities of salt structures, weak primaries from the subsalt, and the interference of free-surface multiples with the weak primaries of the subsalt. To effectively process subsalt data, we need to develop a method of attenuating free-surface multiples that preserves the amplitude and phase of primaries and does not introduce artifacts at either near and far offsets. In this thesis, we will demonstrate that the weak primaries of the subsalt can be preserved while attenuating free-surface multiples. The method used for the demonstration is the bottom-multiple generator (BMG) reflector approximation. This technique requires that a portion of the data containing only primaries be defined. A multidimensional convolution of the data containing only primaries with the actual data will predict free-surface multiples and hence is used to attenuate free-surface multiples from the actual data. This method is one of the most effective methods for attenuating free-surface multiples; however, the method requires muting data at the BMG location. One of the issues investigated in this thesis, is to establish the sensitivity of the BMG demultiple technique when the mute at the BMG location end up cutting some seismic reflections, which can be the case in complex environments such as the Gulf of Mexico and Gulf of Guinea, where freesurface multiples interfere with primaries. For this investigation, we generated synthetic data through the 2D elastic finite-difference modeling technique. The synthetic seismic data contain primaries; free-surface multiples, and internal multiples, and direct waves acquired over a 2D geological model that depicts a shallow-water geology. In this thesis, we also investigate if the first step of the BMG demultiple technique can sufficiently attenuate free-surface multiples. For this investigation, we designed a 2D geological model, which depicts the deep offshore environment, and we generated synthetic data through the 2D elastic finite-difference modeling technique. After performing the various investigations mentioned above, the following conclusions were made, that the demultiple result is not affected when the mute at the BMG location end up cutting some primaries, that the first step of the BMG demultiple technique is not sufficient for the demultiple, and that the weak subsalt primaries are preserved during demultiple processes. We compared shot gathers and zero offset data before and after the demultiple.

This thesis presents a delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-controlled delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-controlled delay line. By using multi-band technology the proposed DLL can provide wider range and lower jitter compared to those of other methods. Frequency can be ranged from 250MHz to 900MHz is using TSMC 0.18um process with 1.8V supply voltage. The other implement is using UMC 90nm 1P9M CMOS process with 1V supply voltage. The frequency can be ranged from 33MHz to 300MHz.

<p>Vid sifferseriell aritmetik används ett antal parallella bitar för varje siffra. För att jämföra prestanda och effektförbrukning i förhållande till antalet bitar behövde Institutionen för systemteknik (ISY) en layout-generator för att enkelt kunna generera layout för en sifferseriell tvåportsadaptor. Layouten skulle göras i 0.18 mikrometer process. Antalet inkommande databitar och antalet koefficientbitar skulle vara variabelt. Stor vikt lades vid planeringen av layouten för att genereringen av adaptorn skulle fungera smidigt oberoende av de variabla parametrarna. Kod skrevs för att koppla samman layout-instanserna och för att förenkla adaptorn. </p> / <p>Digit serial arithmetics uses a number of parallel bits in each digit. To compare performance and power consumption relative the number of bits, the Department of Electric Engineering (ISY) needed a layout generator to generate layout for a digit serial two-port adaptor. The layout should be done in 0.18 micrometer process. The number of bits of the incoming data and the number of bits of the coefficient should be variable. Great concern was put in the planning of the layout to make the generation of the adaptor work well independent of the parameters. Code was written to connect the layout instances and to simplify the adaptor.</p>

<p>In this thesis we investigate, implement and evaluate a solution for introducing the TransmissionControl Protocol (TCP) into the software of a load generator. The load generator is a simulator usedfor simulating end-user generated activities in the Universal Mobile Telecommunication System(UMTS) network. The purpose of simulating traffic on the network is in this case to verify thefunctionality and robustness of the Radio Network Controller (RNC) node within the UMTSnetwork.TCP is a protocol that provides reliable data transfer over unreliable underlying networkprotocols. It is used as the main transport protocol of the Internet, thus it is also used in the UMTSnetwork in order to provide connectivity for user equipment, such as 3G mobile phones, to servicesover the Internet. For the load generator to be able to produce more realistic traffic scenarios is itdesirable to give it the ability to use TCP.This thesis presents a solution of the problem where an open-source implementation of the TCPfunctionality was chosen, ported to the running platform of the load generator and then tested in asimulated test environment. The choice of the open source implementation of TCP was made byperforming an investigation of available options. In the investigation an open source TCP/IP stackcalled lwIP was chosen. lwIP was then ported to the running platform of the load generator bywrapping and modify the source code. The tests of the ported TCP implementation were made in asimulated test environment with focus on testing basic TCP functionality. The tests showed that theTCP implementation produced provided the basic functionality that was asked for.</p>

Zugl.: Berlin, Techn. Univ., Diss., 2009

The movement to smart mobile connected devices which consolidate functions of traditionally separate devices is driving innovation in System-on-chips (SoCs). One of the innovations helping to meet the current needs of SoCs is the integration of larger memory with the processor, and with this, comes the challenge of testing all the memory cells. The programmable memory BIST offers a flexible approach to designers and testers because it allows the memory test algorithms to be updated when new memory fault models are discovered. But this flexibility comes as a trade-off to area as the BIST circuitry needs to be integrated next to the memory array. This report proposes enhancements to an existing design that will improve flexibility by enhancing the address generation schemes while simultaneously eliminating the need for an auxiliary memory in cases where a Type-1 NPSF background will be used. A comparison of the base design to the proposed design shows the address and data generation improvements can be achieved with only 1.8% increase in area with an 8KB memory. / text