Des travaux récents indiquent qu'il existe des différences fondamentales entre les systèmes visuel et auditif: tandis que le premier semble échantillonner le flux d'information en provenance de l'environnement, en passant d'un "instantané" à un autre (créant ainsi des cycles perceptifs), la plupart des expériences destinées à examiner ce phénomène de discrétisation dans le système auditif ont mené à des résultats mitigés. Dans cette thèse, au travers de deux expériences de psychophysique, nous montrons que le sous-échantillonnage de l'information à l'entrée des systèmes perceptifs est en effet plus destructif pour l'audition que pour la vision. Cependant, nous révélons que des cycles perceptifs dans le système auditif pourraient exister à un niveau élevé du traitement de l'information. En outre, nos résultats suggèrent que du fait des fluctuations rapides du flot des sons en provenance de l'environnement, le système auditif tend à avoir son activité alignée sur la structure rythmique de ce flux. En synchronisant la phase des oscillations neuronales, elles-mêmes correspondant à différents états d'excitabilité, le système auditif pourrait optimiser activement le moment d'arrivée de ses "instantanés" et ainsi favoriser le traitement des informations pertinentes par rapport aux événements de moindre importance. Non seulement nos résultats montrent que cet entrainement de la phase des oscillations neuronales a des conséquences importantes sur la façon dont sont perçus deux flux auditifs présentés simultanément ; mais de plus, ils démontrent que l'entraînement de phase par un flux langagier inclut des mécanismes de haut niveau. Dans ce but, nous avons créé des stimuli parole/bruit dans lesquels les fluctuations de l'amplitude et du contenu spectral de la parole ont été enlevés, tout en conservant l'information phonétique et l'intelligibilité. Leur utilisation nous a permis de démontrer, au travers de plusieurs expériences, que le système auditif se synchronise à ces stimuli. Plus précisément, la perception, estimée par la détection d'un clic intégré dans les stimuli parole/bruit, et les oscillations neuronales, mesurées par Electroencéphalographie chez l'humain et à l'aide d'enregistrements intracrâniens dans le cortex auditif chez le singe, suivent la rythmique "de haut niveau" liée à la parole. En résumé, les résultats présentés ici suggèrent que les oscillations neuronales sont un mécanisme important pour la discrétisation des informations en provenance de l'environnement en vue de leur traitement par le cerveau, non seulement dans la vision, mais aussi dans l'audition. Pourtant, il semble exister des différences fondamentales entre les deux systèmes: contrairement au système visuel, il est essentiel pour le système auditif de se synchroniser (par entraînement de phase) à son environnement, avec un échantillonnage du flux des informations vraisemblablement réalisé à un niveau hiérarchique élevé. / Recent research indicates fundamental differences between the auditory and visual systems: Whereas the visual system seems to sample its environment, cycling between "snapshots" at discrete moments in time (creating perceptual cycles), most attempts at discovering discrete perception in the auditory system failed. Here, we show in two psychophysical experiments that subsampling the very input to the visual and auditory systems is indeed more disruptive for audition; however, the existence of perceptual cycles in the auditory system is possible if they operate on a relatively high level of auditory processing. Moreover, we suggest that the auditory system, due to the rapidly fluctuating nature of its input, might rely to a particularly strong degree on phase entrainment, the alignment between neural activity and the rhythmic structure of its input: By using the low and high excitability phases of neural oscillations, the auditory system might actively control the timing of its "snapshots" and thereby amplify relevant information whereas irrelevant events are suppressed. Not only do our results suggest that the oscillatory phase has important consequences on how simultaneous auditory inputs are perceived; additionally, we can show that phase entrainment to speech sound does entail an active high-level mechanism. We do so by using specifically constructed speech/noise sounds in which fluctuations in low-level features (amplitude and spectral content) of speech have been removed, but intelligibility and high-level features (including, but not restricted to phonetic information) have been conserved. We demonstrate, in several experiments, that the auditory system can entrain to these stimuli, as both perception (the detection of a click embedded in the speech/noise stimuli) and neural oscillations (measured with electroencephalography, EEG, and in intracranial recordings in primary auditory cortex of the monkey) follow the conserved "high-level" rhythm of speech. Taken together, the results presented here suggest that, not only in vision, but also in audition, neural oscillations are an important tool for the discretization and processing of the brain's input. However, there seem to be fundamental differences between the two systems: In contrast to the visual system, it is critical for the auditory system to adapt (via phase entrainment) to its environment, and input subsampling is done most likely on a hierarchically high level of stimulus processing.

‘Gender ideology’ is a term used by radical conservative congregations to contemn issues around gender, such as reproductive rights and gender studies, for it is seen as a conspiracy against traditional family values. Congregations that use the term also embrace other forms of anti-gender rhetoric as they aspire to influence decision-makers to adopt policies against gender matters, for instance same-sex marriages and transgender rights. As the discussion of ‘gender ideology’ is spread, campaigns against gender matters evolves. The campaigns are often focusing on whether gender should be discussed within, and be a part of, the education. It is a threat for the achievements of the Sustainable Development Goals 2030, which indeed focus on gender equality and quality education. The campaigns are seen all over the world but have become especially successful within South America. In Brazil, the campaign Escola sem Partido, has created a movement against gender and political indoctrination, where the term gender has become a central dispute for what is considered legitimate knowledge.     This thesis aims to investigate, through a critical discourse analysis of ‘testimonies’ from Escola sem Partido’s website and through collecting interviews with professors and students at a university in Brazil, the conflict about gender equality. Since the term gender has become a central term of dispute within the discussion of ‘political indoctrination’ at a high level of education.   The result of this thesis shows that the perception of gender reflects the perception of one’s education. The view on what is experienced legitimate knowledge determines whether professors are experienced as political or not. It is found within the ‘testimonies’ that professors personal agenda steers the education to involve gender matters when it should not, as gender matters are viewed as political. Moreover, that professors use their classes to systematically instill ideas and attitudes into their students minds. In opposition to this perception, it was found within the interviews that gender matters should be addressed in school. Universities role of promoting tolerance, and the value of engaged professors who allows critical thinking of societal issues, are two important factors for fighting prejudices against minorities, gender and varieties of sexualities and development for gender equality.

Field Programmable Gate Arrays (FPGAs) are programmable logic devices used for the implementation of a wide range of digital systems. In recent years, there has been an increasing interest in design methodologies that allow high-level design descriptions to be automatically implemented in FPGAs. This thesis describes the design and implementation of a novel compilation flow that implements circuits in FPGAs from a streaming programming language. The streaming language supported is called FPGA Brook, and is based on the existing Brook and GPU Brook languages, which target streaming multiprocessors and graphics processing units (GPUs), respectively. A streaming language is suitable for targeting FPGAs because it allows system designers to express applications in a way that exposes parallelism, which can then be exploited through parallel hardware implementation. FPGA Brook supports replication, which allows the system designer to trade-off area for performance, by specifying the parts of an application that should be implemented as multiple hardware units operating in parallel, to achieve desired application throughput. Hardware units are interconnected through FIFO buffers, which effectively utilize the small memory modules available in FPGAs. The FPGA Brook design flow uses a source-to-source compiler, and combines it with a commercial behavioural synthesis tool to generate hardware. The source-to-source compiler was developed as a part of this thesis and includes novel algorithms for implementation of complex reductions in FPGAs. The design flow is fully automated and presents a user-interface similar to traditional software compilers. A suite of benchmark applications was developed in FPGA Brook and implemented using our design flow. Experimental results show that applications implemented using our flow achieve much higher throughput than the Nios II soft processor implemented in the same FPGA device. Comparison to the commercial C2H compiler from Altera shows that while simple applications can be effectively implemented using the C2H compiler, complex applications achieve significantly better throughput when implemented by our system. Performance of many applications implemented using our design flow would scale further if a larger FPGA device were used. The thesis demonstrates that using an automated design flow to implement streaming applications in FPGAs is a promising methodology.

Field Programmable Gate Arrays (FPGAs) are programmable logic devices used for the implementation of a wide range of digital systems. In recent years, there has been an increasing interest in design methodologies that allow high-level design descriptions to be automatically implemented in FPGAs. This thesis describes the design and implementation of a novel compilation flow that implements circuits in FPGAs from a streaming programming language. The streaming language supported is called FPGA Brook, and is based on the existing Brook and GPU Brook languages, which target streaming multiprocessors and graphics processing units (GPUs), respectively. A streaming language is suitable for targeting FPGAs because it allows system designers to express applications in a way that exposes parallelism, which can then be exploited through parallel hardware implementation. FPGA Brook supports replication, which allows the system designer to trade-off area for performance, by specifying the parts of an application that should be implemented as multiple hardware units operating in parallel, to achieve desired application throughput. Hardware units are interconnected through FIFO buffers, which effectively utilize the small memory modules available in FPGAs. The FPGA Brook design flow uses a source-to-source compiler, and combines it with a commercial behavioural synthesis tool to generate hardware. The source-to-source compiler was developed as a part of this thesis and includes novel algorithms for implementation of complex reductions in FPGAs. The design flow is fully automated and presents a user-interface similar to traditional software compilers. A suite of benchmark applications was developed in FPGA Brook and implemented using our design flow. Experimental results show that applications implemented using our flow achieve much higher throughput than the Nios II soft processor implemented in the same FPGA device. Comparison to the commercial C2H compiler from Altera shows that while simple applications can be effectively implemented using the C2H compiler, complex applications achieve significantly better throughput when implemented by our system. Performance of many applications implemented using our design flow would scale further if a larger FPGA device were used. The thesis demonstrates that using an automated design flow to implement streaming applications in FPGAs is a promising methodology.

Pattern matching approaches in reverse engineering aim to incorporate domain knowledge and system documentation in the software architecture extraction process, hence provide a user/tool collaborative environment for architectural design recovery. This thesis presents a model and an environment for recovering the high level design of legacy software systems based on user defined architectural patterns and graph matching techniques. In the proposed model, a high-level view of a software system in terms of the system components and their interactions is represented as a query, using a description language. A query is mapped onto a pattern-graph, where a module and its interactions with other modules are represented as a group of graph-nodes and a group of graph-edges, respectively. Interaction constraints can be modeled by the description language as a part of the query. Such a pattern-graph is applied against an entity-relation graph that represents the information extracted from the source code of the software system. An approximate graph matching process performs a series of graph edit operations (i. e. , node/edge insertion/deletion) on the pattern-graph and uses a ranking mechanism based on data mining association to obtain a sub-optimal solution. The obtained solution corresponds to an extracted architecture that complies with the given query. An interactive prototype toolkit implemented as part of this thesis provides an environment for architecture recovery in two levels. First the system is decomposed into a number of subsystems of files. Second each subsystem can be decomposed into a number of modules of functions, datatypes, and variables.

Pattern matching approaches in reverse engineering aim to incorporate domain knowledge and system documentation in the software architecture extraction process, hence provide a user/tool collaborative environment for architectural design recovery. This thesis presents a model and an environment for recovering the high level design of legacy software systems based on user defined architectural patterns and graph matching techniques. In the proposed model, a high-level view of a software system in terms of the system components and their interactions is represented as a query, using a description language. A query is mapped onto a pattern-graph, where a module and its interactions with other modules are represented as a group of graph-nodes and a group of graph-edges, respectively. Interaction constraints can be modeled by the description language as a part of the query. Such a pattern-graph is applied against an entity-relation graph that represents the information extracted from the source code of the software system. An approximate graph matching process performs a series of graph edit operations (i. e. , node/edge insertion/deletion) on the pattern-graph and uses a ranking mechanism based on data mining association to obtain a sub-optimal solution. The obtained solution corresponds to an extracted architecture that complies with the given query. An interactive prototype toolkit implemented as part of this thesis provides an environment for architecture recovery in two levels. First the system is decomposed into a number of subsystems of files. Second each subsystem can be decomposed into a number of modules of functions, datatypes, and variables.

本研究期望能設計以環境保護為主題的華語課程，使中高級華語學習者在學習語言的同時，亦能了解相關環保知識，並透過共同討論現實世界所面臨的問題提升其環保意識。 研究目的為：一、了解中高級華語學習者之學習需求。二、提供環保議題融入華語教學課程設計參考模式。三、評估具體教學成效。在課程設計前，透過文獻分析釐清本課程適合的教學方法、教學目標訂定方式以及教學材料的選取、編寫準則，主要以主題式教學法（Theme-Based Language Instruction）、溝通式教學法（Communicative Language Teaching）、美國外語教學學會（ACTFL）之5C準則（5C Standards）及貝爾格勒憲章（The Belgrade Charter）中的六項環境教育目標為本研究之教學理念，並參考英語教學之經驗，思考環境議題融入語言課程可行方式。亦透過需求分析，向中高級學習者與教師發放問卷，了解「教」與「學」兩方對於環保主題課程的態度及看法。綜合文獻與需求分析結果為本研究課程設計總體方向，依此進行課程發展設計，並實際進行兩次課程實施以評估學習成就及整體課程設計，提出改進之道及後續研究建議。 本文主要研究方法為發展研究法、問卷及訪談調查法。發展研究法提供本研究可參照之設計流程，包含分析、設計發展、課程實施、成效評估、修正等階段。問卷調查用於課程設計前之學習需求分析、課程實施後之課程滿意度調查；訪談則用於課程實施後，了解學習者對本課程的想法、心得與建議，進一步回饋至修正建議。 透過教學實施，學習者對於本課程皆給予正面評價，認為本課程有意思且實用，不僅能使語言技能進步，亦能關心、討論環境議題，也讓平常少有機會接觸時事的學生更了解台灣社會與文化。本研究根據教學成效提出幾點教學建議：一、在教學內容選取上，現實議題探討能加強學習者之社會語言能力，且符合學習興趣，使學習者能更了解所處的社會環境。議題以真實材料或非真實材料呈現皆有其須注意之處。二、在環境教育目標於華語課程之實踐上，教師須於課堂提供察覺、認識之契機，透過引導，學習者能自行運用其技能與評估能力，最後發展出個人觀點與態度。三、在課堂活動規劃上，輸入、輸出型活動須搭配且循序運用。筆者並於篇末提出後續研究建議。 / This study examines the design of a Chinese language curriculum focused on environmental protection, and aims to enhance students’ language skills while increasing awareness about environmental issues. There are three purposes of this study; the first is to analyze the learning needs of intermediate-high CSL students, the second is to provide a design model for an environmentally themed CSL curriculum, and the third is to evaluate the effectiveness of its implementation. Also included is a review of previous studies that highlights appropriate methods of developing objectives, editing materials, and teaching. The instructional philosophy of this study is based on theme-based language instruction, communicative language teaching, the 5 C’s language teaching standards (ACTFL) , and the six objectives of environmental education in the Belgrade Charter. A learning needs questionnaire is also given to both teachers and students in order to survey their opinions on teaching and learning. The results of this needs analysis and extensive review of existing literature provide the main guiding principles behind the curriculum’s development. The results of two terms of implementations are presented, as well as potential further improvements. The main research method of this study is developmental research; surveys and interviews are used to as supplemental methods. The developmental research method provides a model for curriculum design, and calls for various phases of analysis, design (development), implementation, and evaluation. Survey research is then used to forecast learning needs before the design phase, and also to gather students’ feedback after the completion of the class. Interviews are used after each complete implementation to gather more information and impressions from students. After two complete implementations of the curriculum, the interview results show that students find the course practical and interesting, as they can not only enhance their language skills, but also raise their awareness of environmental issues through class discussion. In addition, they felt the class increased their understanding of Taiwan society and culture via discussion of current events. The main findings are as follows: 1) Content relating to social issues can simultaneously improve students’ sociolinguistic competence and also meet their learning needs. The contents can be provided in authentic or inauthentic contexts, but should follow certain design principles. 2) To fulfill the six objectives of environmental education in a CSL curriculum, the instructor needs to help students understand environmental issues first, and then guide students to use their analysis skills to evaluate current events. Afterwards, students will develop their own perspective and attitude. 3) To develop an effective course, the input and output activities should be arranged in sequence.

Die Dissertationsschrift stellt eine Methodik und die Infrastruktur zur Entwicklung von dynamisch verteilbaren Anwendungen für heterogene Computersysteme vor. Diese Computersysteme besitzen vielfältige Rechenwerke, die Berechnungen in den Domänen Software und Hardware realisieren. Als erster Schritt wird ein übergreifendes und integriertes Vorgehen für den Anwendungsentwurf auf Basis eines abstrakten “Single-Source” Ansatzes entwickelt. Durch die Virtualisierung der Rechenwerke wird die preemptive Verteilung der Anwendungen auch über die Domänengrenzen möglich. Die Anwendungsentwicklung für diese Computersysteme bedarf einer durchgehend automatisierten Entwurfsunterstützung. In der Arbeit wird der dazu vorgeschlagene Ansatz formalisiert und eine neuartige Unterbrechungspunktsynthese entwickelt, die ein hinsichtlich Zeit und Fläche optimiertes, präemptives Verhalten für beliebige Anwendungsbeschreibungen generiert. Das Verfahren wird beispielhaft implementiert und mittels einer FPGA- Prototypenplattform mit Linux-basierter Laufzeitumgebung anhand dreier Fallbeispiele unterschiedlicher Komplexität validiert und evaluiert. / This thesis introduces a methodology and infrastructure for the development of dynamically distributable applications on heterogeneous computing systems. Such systems execute computations using resources from both the hardware and the software domain. An integrated approach based on an abstract single-source design entry is developed that allows preemptive partitioning through virtualization of computing resources across the boundaries of differing computational domains. Application design for heterogeneous computing systems is a complex task that demands aid by electronic design automation tools. This work provides a novel synthesis approach for breakpoints that generates preemptive behaviour for arbitrary applications. The breakpoint scheme is computed for a minimal additional resource utilization and given timing constraints. The approach is implemented on an FPGA prototyping platform driven by a Linux based runtime environment. Evaluation and validation of the approach have been carried out using three different application examples.

Power dissipation in CMOS circuits is of growing concern as the computational requirements of portable, battery operated devices increases. The ability to easily develop application specific circuits, rather than program general-purpose architectures can provide tremendous power savings. To this end, we present a design platform for rapidly developing power efficient hardware architectures starting at a system level. This high level VLSI design platform, called CoDeL, allows hardware description at the algorithm level, and thus dramatically reduces design time and power dissipation. We compare the CoDeL platform to a modern DSP and find that the CoDeL platform produces designs with somewhat slower run times but dramatically lower power dissipation. The CoDeL compiler produces an FSMD (Finite State Machine with Datapath) implementation of the circuit. This regular structure can be exploited to further reduce power through various techniques. To reduce dynamic power dissipation in the resulting architecture, the CoDeL compiler automatically inserts clock gating for registers. Power analysis shows that CoDeL's automated, high-level clock gating provides considerably more power savings than existing automated clock gating tools. To reduce static power, we use the CoDeL platform to analyze the potential and performance impact of power gating individual registers. We propose a static gating method, with very low area overhead, which uses the information available to the CoDeL compiler to predict, at compile time, when the registers can be powered off and powered on. Static branch prediction is used to more intelligently traverse the finite state machine description of the circuit to discover gating opportunities. Using simulation and estimation, we find that CoDeL with backward branch prediction gives the best overall combination of gating potential and performance. Compared to a dynamic time-based technique, this method gives dramatically more power savings, without any additional performance loss. Finally, we propose techniques to efficiently partition a FSMD using Integer Linear Programming and a simulated annealing approach. The FSMD is split into two or more simpler communicating processors. These separate processors can then be clock gated or power gated to achieve considerable power savings since only one processor is active at any given time. Implementation and estimation shows that significant power savings can be expected, when the original machine is partitioned into two or more submachines.

Les systèmes intégrés sont souvent des systèmes hétérogènes avec des contraintes fortes de consommation électrique. Ils embarquent aujourd'hui des actionneurs, des capteurs et des unités pour le traitement du signal. Afin de limiter l'énergie consommée, ils peuvent tirer profit des techniques évènementielles que sont l'échantillonnage non uniforme et l'électronique asynchrone. En effet, elles permettent de réduire drastiquement la quantité de données échantillonnées pour de nombreuses classes de signaux et de diminuer l'activité. Pour aider les concepteurs à développer rapidement des plateformes exploitant ces deux techniques évènementielles, nous avons élaboré un flot de conception nommé ALPS. Il propose un environnement permettant de déterminer et de simuler au niveau algorithmique le schéma d'échantillonnage et les traitements associés afin de sélectionner les plus efficients en fonction de l'application ciblée. ALPS génère directement le convertisseur analogique/numérique à partir des paramètres d'échantillonnage choisis. L'élaboration de la partie de traitement s'appuie quant à elle sur un outil de synthèse de haut niveau synchrone et une méthode de désynchronisation exploitant des protocoles asynchrones spécifiques, capables d'optimiser la surface et la consommation du circuit. Enfin, des simulations au niveau porteslogiques permettent d'analyser et de valider l'énergie consommée avant de poursuivre par un flot classique de placement et routage. Les évaluations conduites montrent une réduction d'un facteur 3 à 8 de la consommation des circuits automatiquement générés. Le flot ALPS permet à un concepteur non-spécialiste de se concentrer sur l'optimisation de l'échantillonnage et de l'algorithme en fonction de l'application et de potentiellement réduire d'un ou plusieurs ordres de grandeur la consommation du circuit. / Integrated systems are mainly heterogeneous systems with strong powerconsumption constraints. They embed actuators, sensors and signalprocessing units. To limit the energy consumption, they can exploitevent-based techniques, namely non-uniform sampling and asynchronouscircuits. Indeed, they allow cutting drastically the amount of sampleddata for many types of signals and reducing the system activity. To helpdesigners in quickly developing platforms that exploit those event-basedtechniques, we elaborated a design framework called ALPS. It proposes anenvironment to determine and simulate at algorithmic level the samplingscheme and the associated processing in order to select the mostefficient ones depending on the targetted application. ALPS generatesdirectly the analog-to-digital converter based on the chosen samplingparameters. The elaboration of the processing unit uses a synchronoushigh-level synthesis tool and a desynchronization method that exploitsspecific asynchronous protocols to optimize the circuit area and powerconsumption. Finally, gate-level simulations allow analyzing andvalidating the energy consumption before continuing with a standardplacement and routing flow. The conducted evaluations show a reductionfactor of 3 to 8 of the consumption of the automatically generatedcirctuis. The flow ALPS allow non-specialists to concentrate on theoptimization of the sampling and the processing in function of theirapplication and to reduice the circuit power consumptions by one toseveral orders of magnitude.