A scheduling algorithm has the primary role in implementing the quality of service guaranteed to each flow by managing buffer space and selecting which packet to send next with a fair share of network. In this thesis, some scheduling algorithms for packet switching networks are studied. For evaluating their delay, jitter and throughput performances, a discrete event simulator has been developed. It has been seen that fair scheduling provides, fair allocation of bandwidth, lower delay for sources using less than their full share of bandwidth and protection from ill-behaved resources.

Electrical stimulation of the retina affected by photoreceptor loss (e.g., cases of retinitis pigmentosa) elicits the perception of luminous spots (so-called phosphenes) in the visual field. This phenomenon, attributed to the relatively high survival rates of neurons comprising the retina's inner layer, serves as the cornerstone of efforts to provide a microelectronic retinal prosthesis -- a device analogous to the cochlear implant. This thesis concerns phosphenes -- their elicitation and modulation, and, in turn, image analysis for use in a prosthesis. This thesis begins with a comparative review of visual modelling of electrical epiretinal stimulation and analogous acoustic modelling of electrical cochlear stimulation. The latter models involve coloured noise played to normal listeners so as to investigate speech processing and electrode design for use in cochlear implants. Subsequently, four experiments (three psychophysical and one numerical), and two statistical analyses, are presented. Intrinsic signal optical imaging in cerebral cortex is canvassed appendically. The first experiment describes a visual tracking task administered to 20 normal observers afforded simulated prosthetic vision. Fixation, saccade, and smooth pursuit, and the effect of practice, were assessed. Further, an image analysis scheme is demonstrated that, compared to existing approaches, assisted fixation and pursuit (but not saccade) accuracy (35.8% and 6.8%, respectively), and required less phosphene array scanning. Subsequently, (numerical) information-theoretic reasoning is provided for the scheme's superiority. This reasoning was then employed to further optimise the scheme (resulting in a filter comprising overlapping Gaussian kernels), and may be readily extended to arbitrary arrangements of many phosphenes. A face recognition study, wherein stimuli comprised either size- or intensity-modulated phosphenes, is then presented. The study involved unpracticed observers (n=85), and showed no 'size' --versus--'intensity' effect. Overall, a 400-phosphene (100-phosphene) image afforded subjects 89.0% (64.0%) correct recognition (two-interval forced-choice paradigm) when five seconds' scanning was allowed. Performance fell (64.5%) when the 400-phosphene image was stabilised on the retina and presented briefly. Scanning was similar in 400- and 100-phosphene tasks. The final chapter presents the statistical effects of sampling and rendering jitter on the phosphene image. These results may generalise to low-resolution imaging systems involving loosely packed pixels.

Timing jitter and phase noise are important design considerations in most electronic systems, particularly communication systems. The desire for faster transmission speeds and higher levels of integration, combined with lower signal levels and denser circuit boards has placed greater emphasis on managing problems related to phase noise, timing jitter, and timing distribution. This thesis reports original work on phase noise modelling in electronic systems. A new model is proposed which predicts the up-conversion of baseband noise to the carrier frequency in RF amplifiers. The new model is validated by comparing the predicted phase noise performance to experimental measurements as it applies to a common emitter (CE), bipolar junction transistor (BJT) amplifier. The results show that the proposed model correctly predicts the measured phase noise, including the shaping of the noise about the carrier frequency, and the dependence of phase noise on the amplifier parameters. In addition, new work relating to timing transfer in digital communication systems is presented. A new clock recovery algorithm is proposed for decoding timing information encoded using the synchronous residual time-stamp (SRTS) method. Again, theoretical analysis is verified by comparison with an experimental implementation. The results show that the new algorithm correctly recovers the source clock at the destination, and satisfies the jitter specification set out by the ITU-T for G.702 signals.

The study concerns the analysis of vocal cycle length perturbations in normophonic and dysphonic speakers.A method for tracking cycle lengths in voiced speech is proposed. The speech cycles are detected via the saliences of the speech signal samples, defined as the length of the temporal interval over which a sample is a maximum. The tracking of the cycle lengths is based on a dynamic programming algorithm that does not request that the signal is locally periodic and the average period length known a priori.The method is validated on a corpus of synthetic stimuli. The results show a good agreement between the extracted and the synthetic reference length time series. The method is able to track accurately low-frequency modulations and ast cycle-to-cycle perturbations of up to 10% and 4% respectively over the whole range of vocal frequencies. Robustness with regard to the background noise has lso been tested. The results indicate that the tracking is reliable for signal-to-noise ratios higher than 15dB.A method for analyzing the size of the cycle length perturbations as well as their frequency is proposed. The cycle length time series is decomposed into a sum of oscillating components by empirical mode decomposition the instantaneous envelopes and frequencies of which are obtained via AM-FM decomposition. Based on their average instantaneous frequencies, the empirical modes are then assigned to four categories (declination, physiological tremor, neurological tremor as well as cycle length jitter) and added within each. The within-category size of the cycle length perturbations is estimated via the standard deviation of the empirical mode sum divided by the average cycle length. The neurological tremor modulation frequency and bandwidth are obtained via the instantaneous frequencies and amplitudes of empirical modes in the neurological tremor category and summarized via a weighted instantaneous frequency probability density, compensating for the effects of mode mixing.The method is applied to two corpora of vowels comprising 123 and 74 control and 456 and 205 Parkinson speaker recordings respectively. The results indicate that the neurological tremor modulation depth is statistically significantly higher for female Parkinson speakers than for female control speakers. Neurological tremor frequency differs statistically significantly between male and female speakers and increases statistically significantly for the pooled Parkinson speakers compared to the pooled control speakers. Finally, the average vocal frequency increases for male Parkinson speakers and decreases for female Parkinson speakers, compared to the control speakers. / Doctorat en Sciences de l'ingénieur et technologie / info:eu-repo/semantics/nonPublished

Abstract The aim of this work was to develop time-to-digital converters(TDC) with a wide measurement range of several hundred microseconds and with a measurement precision of a few picoseconds. Because of these requirements, the focus of this work was mainly on TDC architectures based on the Nutt interpolation method, which has several advantages when a long measurement range is a requirement. Compared to conventional data converters the characteristics of a Nutt TDC differ significantly when, for example, quantization errors and linearity errors are considered. In this thesis, the operating principle of a Nutt TDC is analysed and, in particular, the effects of reference clock instabilities are studied giving new insight how the different phase noise processes can be reliably translated into time interval jitter, and how these affect the measurement precision when very long time intervals are measured. Furthermore, these analytical results are confirmed by measurements conducted with a long-range TDC designed as part of this work. Two long-range TDCs have been designed, each based on different interpolator architectures. The first TDC utilises discrete component time-to-voltage converters(TVC) as interpolators. Other key functionality is implemented on an FPGA. The interpolators use Miller integrators to improve the linearity and the single-shot precision of the converter. The TDC has a nominal measurement range of 84ms and it achieves a single-shot precision of 2ps for time intervals shorter than 2ms, after which the precision starts to deteriorate due to the phase noise of the reference clock. In addition to the discrete TDC, an integrated long-range CMOS TDC has been designed with 0.35μm technology. Instead of TVCs, this TDC features cyclic/algorithmic interpolators, which are based on switched-frequency ring oscillators(SRO). The frequency switching is used as a mechanism to amplify quantization error, a key functionality required by any cyclic or a pipeline converter. The interpolators are combined with a 16-bit main counter giving a total range of 327μs. The RMS single-shot precision of the TDC is 4.2ps without any nonlinearity compensation. Furthermore, a calibration functionality implemented partially on-chip ensures that the accuracy of the TDC varies only ±2.5ps in a temperature range of -30C to 70C. Although implemented with fairly old technology, the interpolators’ effective linear range and precision represent state-of-the-art performance. / Tiivistelmä Tämän työn tavoitteena oli kehittää aika-digitaalimuuntia (TDC), joilla on laaja satojen mikrosekuntien mittausalue ja muutaman pikosekunnin kertamittaustarkkuus. Näistä vaatimuksista johtuen tässä työssä keskitytään pääasiassa Nuttin interpolointimenetelmään perustuviin TDC-arkkitehtuureihin. Verrattuna tavanomaisiin datamuuntimiin, Nutt TDC:n toiminta poikkeaa merkittävästi, kun tarkastellaan kvantisointi- ja lineaarisuusvirhettä. Tässä väitöskirjatyössä Nuttin menetelmään perustavan TDC:n toiminta analysoidaan, jonka yhteydessä tutkitaan erityisesti referenssioskillaattorin epästabiilisuuksien vaikutusta mittausepävarmuuteen. Tämän pohjalta vaihekohinan eri kohinaprosessit voidaan luotettavasti muuntaa taajuustason kohinatiheysmittauksista aika-tasossa kuvattavaksi aikavälijitteriksi. Nämä teoreettiset tulokset ovat varmistettu yhdellä osana tätä työtä suunnitellulla pitkän kantaman TDC:llä. Teoreettisen tarkastelun lisäksi kaksi pitkän kantaman TDC:tä on suunniteltu, toteutettu ja testattu. Ensimmäinen näistä perustuu erilliskomponenteilla toteutettuun aika-jännitemuunnokseen (TVC) pohjautuvaan interpolointimenetelmään. Analogisten interpolaattoreiden ohella muu olennainen toiminnallisuus toteutettiin FPGA:lle. Interpolaattorit käyttävät Miller-integraattoreita lineaarisuuden ja kertamittaustarkkuuden parantamiseksi. TDC:n nimellinen mittausalue on 84ms ja sillä saavutetaan 2ps:n kertamittaustarkkuus, kun mitattava aikaväli on lyhyempi kuin 2ms, minkä jälkeen mittaustarkkuus heikkenee referenssioskillaattorin vaihekohinan vaikutuksesta. Toinen pitkän kantaman TDC perustuu 0.35μm:n CMOS teknologialla totetutettuun integroituun piiriin. Aika-jännitemuunnoksen sijasta tämä TDC perustuu sykliseen/algoritmiseen interpolointitekniikkaan, jossa taajuusmoduloitua rengasoskillaattoria(SRO) käytetään kvantisointivirheen vahvistamiseksi. Interpolaattorit ovat yhdistetty 16-bittiseen referenssioskillaattorin laskuriin, jolloin TDC:n mittausalue on noin 327μs. Tämän TDC:n RMS kertamittaustarkkuus on 4.2ps, joka saavutetaan ilman epälineaarisuuden kompensointia. Samalle piirille on lisäksi toteutettu kalibrointitoiminnallisuus, jolla varmistetaan TDC:n hyvä mittaustarkkuus kaikissa olosuhteissa. Mittaustarkkuus poikkeaa maksimissaan vain ±2.5ps, kun lämpötila on välillä -30C-70C. Vaikka TDC on toteutettu kohtalaisen vanhalla CMOS teknologialla, interpolaattoreiden efektiivinen lineaarinen alue ja mittaustarkkuus edustavat alansa huippua.

Today’s microprocessors with millions of transistors perform high-complexitycomputing at multi-gigahertz clock frequencies. Clock generation and clockdistribution are crucial tasks which determine the overall performance of amicroprocessor. The ever-increasing power density and speed call for newmethodologies in clocking circuitry, as the conventional techniques exhibit manydrawbacks in the advanced VLSI chips. A significant percentage of the total dynamicpower consumption in a microprocessor is dissipated in the clock distributionnetwork. Also since the chip dimensions increase, clock jitter and skew managementbecome very challenging in the framework of conventional methodologies. In such asituation, new alternative techniques to overcome these limitations are demanded. The main focus in this thesis is on new circuit techniques, which treat thedrawbacks of the conventional clocking methodologies. The presented research in thisthesis can be divided into two main parts. In the first part, challenges in design ofclock generators have been investigated. Research on oscillators as central elements inclock generation is the starting point to enter into this part. A thorough analysis andmodeling of the injection-locking phenomenon for on-chip applications show greatpotential of this phenomenon in noise reduction and jitter suppression. In thepresented analysis, phase noise of an injection-locked oscillator has been formulated.The first part also includes a discussion on DLL-based clock generators. DLLs haverecently become popular in design of clock generators due to ensured stability,superior jitter performance, multiphase clock generation capability and simple designprocedure. In the presented discussion, an open-loop DLL structure has beenproposed to overcome the limitations introduced by DLL dithering around the averagelock point. Experimental results reveals that significant jitter reduction can beachieved by eliminating the DLL dithering. Furthermore, the proposed structuredissipates less power compared to the traditional DLL-based clock generators.Measurement results on two different clock generators implemented in 90-nm CMOSshow more than 10% power savings at frequencies up to 2.5 GHz. In the second part of this thesis, resonant clock distribution networks have beendiscussed as low-power alternatives for the conventional clocking schemes. In amicroprocessor, as clock frequency increases, clock power is going to be thedominant contributor to the total power dissipation. Since the power-hungry bufferstages are the main source of the clock power dissipation in the conventional clock distribution networks, it has been shown that the bufferless solution is the mosteffective resonant clocking method. Although resonant clock distribution shows greatpotential in significant clock power savings, several challenging issues have to besolved in order to make such a clocking strategy a sufficiently feasible alternative tothe power-hungry, but well-understood, conventional clocking schemes. In this part,some of these issues such as jitter characteristics and impact of tank quality factor onoverall performance have been discussed. In addition, the effectiveness of theinjection-locking phenomenon in jitter suppression has been utilized to solve the jitterpeaking problem. The presented discussion in this part is supported by experimentalresults on a test chip implemented in 130-nm CMOS at clock frequencies up to 1.8GHz. / Mikroprocessorer till dagens datorer innehåller hundratals miljoner transistorersom utför åtskilliga miljarder komplexa databeräkningar per sekund. I stort settalla operationer i dagens mikroprocessorer ordnas genom att synkronisera demmed en eller flera klocksignaler. Dessa signaler behöver ofta distribueras överhela chippet och driva alla synkroniseringskretsar med klockfrekvenser pååtskilliga miljarder svängningar per sekund. Detta utgör en stor utmaning förkretsdesigners på grund av att klocksignalerna behöver ha en extremt högtidsnoggranhet, vilket blir svårare och svårare att uppnå då chippen blir större.Idealt ska samma klocksignal nå alla synkroniseringskretsar exakt samtidigt föratt uppnå optimal prestanda, avvikelser ifrån denna ideala funktionalitet innebärlägre prestanda. Ytterliggare utmaningar inom klockning av digitala chip, är atten betydande andel av processorns totala effekt förbrukas i klockdistributionen.Därför krävs nya innovativa kretslösningar för att lösa problemen med bådeonoggrannheten och den växande effektförbrukningen i klockdistributionen. att lösa de problem som finns i dagens konventionella kretslösningar förklocksignaler på chip. I den första delen av denna avhandling presenterasforskningsresultat på oscillatorer vilka utgör mycket viktiga komponenter igeneringen av klocksignalerna på chippen. Teoretiska studier avfaslåsningsfenomen i integrerade klockoscillatorer har presenterats. Studiernahar visat att det finns stor potential för reducering av tidsonoggrannhet iklocksignalerna med hjälp av faslåsning till en annan signal. I avhandlingensförsta del presenteras även en diskussion om klockgeneratorer baserade påfördröjningslåsta element. Dessa fördröjningslåsta elementen, kända som DLLkretsar, har egenskapen att de kan fördröja en klocksignal med en bestämdfördröjning, vilket möjliggör skapandet av multipla klockfaser. En nykretsteknik har introducerats för klockgenerering av multipla klockfaser vilken reducerar effektförbrukningen och onoggranheten i DLL-baseradeklockgeneratorer. I denna teknik används en övervakningskrets vilken ser till attalla delar i klockgeneratorn utnyttjas effektivt och att oanvända kretsarinaktiveras. Baserat på experimentalla mätresultat från tillverkade testkretsar ikisel har en effektbesparing på mer än 10% uppvisats vid klockfrekvenser påupp till 2.5 GHz tillsammans med en betydande ökning av klocknoggranheten. I avhandlingens andra del diskuteras en klockdistributionsteknik som baseraspå resonans, vilken har visat sig vara ett lovande alternativ till konventionllabufferdrivna klockningstekniker när det gäller minskande effektförbrukning.Principen bakom tekniken är att återanvända den energi som utnyttjas till attladda upp klocklasten. Teoretiska resonemang har visat att storaenergibesparingar är möjliga, och praktiska mätningar på tillverkadeexperimentchip har visat att effektförbrukingen kan mer än halveras. Ettproblem med den föreslagna klockningstekniken är att data som används iberäkningarna kretsen direkt påverkar klocklasten, vilket även påverkarnoggranheten på klocksignalen. För att komma till rätta med detta problemetpresenteras en teknik, baserad på forskning inom ovan nämndafaslåsningsfenomen, som kan minska onoggrannheten på klocksignalen medöver 50%. Både effektbesparingen och förbättringen av tidsnoggranheten harverifierats med hjälp av mätningar på tillverkade chip vid frekvenser upp mot1.8 GHz.

Master thesis involves the development of quality measurement issues and performance parameters in data networks. It describes the main technologies as they affect the quality and performance parameters and the effect of these parameters for voice, video and data services. Next are listed some methods for measuring parameters of the data network.In the practical part is selected one method of measuring network parameters and properties of this method are demonstrated by illustrative examples.

The aim of the project is to design a concept of function generator with digital synthesis. The device will be controlled using microprocessor which allows synthesizing basic functions (sin, square, raw) as well as arbitrary functions stored in memory. User friendly graphical interface will be controlled by keyboard and rotary switch (IRC). The work emphasizes correct selection of DDS clock source, circuit elements and proper application of signal filtration method with attention to low distortion and low output phase noise.

The main aim of this thesis is to familiarize with options of services using real-time data transfer in wireless networks. Theoretical part presents wireless network based on IEEE 802.11 standard and its practical use. Large part is focuses on 802.11e standart, that provides support for quality of service in wireless networks. Furthemore this thesis deals with transport and applicaton protocols supporting multimedia streaming over computer network. Second chapter is focused on analyzing real computer network with purpose in measuring parametrs influencing quality of service such as bandwith, delay, jitter and loss. Last part deals with the design of wireless network in OPNET Modeler enviroment with focus on simulating parameters that influence quality of service.

The thesis examines the impact of VoIP transmission channel characteristics on speech parameters. It seeks ways of emulating properties of a selected VoIP transmission channel and creating a network emulation environment. Several scripts have been created in the Matlab development environment and used to modify and divide a continuous recording into parts identical to the original speeches, before passing through the transmission channel. Subsequently a database of speech recordings is created, as affected by selected characteristics - jitter, bandwidth, loss. Within these databases, symptoms are sought as the most evident characteristics of the transmission channel. Using correlation, symptoms are selected that are best suited for automated determination of the properties of transmission channel characteristics such as jitter, loss and bandwidth.