La numérisation de plus en plus rapide de signaux à très large bande-passante permet aujourd'hui d'envisager de nombreuses applications pour les systèmes de télécommunication, les mesures expérimentales ou les systèmes radar. Les signaux issus des capteurs peuvent être analysés directement, en évitant la conversion en fréquences intermédiaires. Dans ce travail, nous nous intéressons plus particulièrement au système d'échantillonnage pour des applications radar, qui nécessitent une amélioration significative de la résolution des systèmes existants. L'objectif que nous visons inclus les spécifications suivantes : une fréquence d'échantillonnage de 40 GEch/s, une bande-passante supérieure à 15 GHz et une résolution de 10 bits effectifs à 8 GHz. Partant des excellents résultats obtenus sur les architectures mono-coup à entrelacement temporel, nous avons choisi d'adapter leur principe à un fonctionnement répétitif. Nous avons aussi choisi de baser cette étude sur la technologie TBH sur InP car elle présente les meilleures potentialités pour notre application. Deux éléments de base de ces systèmes ont fait l'objet d'une optimisation particulière pour améliorer la résolution du système : l'inverseur pour minimiser le jitter et l'échantillonneur-bloqueur, principalement pour améliorer la linéarité. Partant de ces résultats, trois architectures innovantes ont été proposées. Pour chacune nous avons conçu un système dont nous avons simulé les performances

<p>Random numbers are required for cryptographic applications such as IT security products, smart cards etc. Hardwarebased random number generators are widely employed. Cryptographic algorithms are implemented on FieldProgrammable Gate Arrays (FPGAs). In this work a True Random Number Generator (TRNG) employed for spaceapplication was designed, investigated and evaluated. Several cryptographic requirements has to be satisfied for therandom numbers. Two different noise sources was designed and implemented on the FPGA. The first design wasbased on ring oscillators as a noise source. The second design was based on astable oscillators developed on a separatehardware board and interfaced with the FPGA as another noise source. The main aim of the project was to analyse theimportant requirement of independent noise source on a physical level. Jitter from the oscillators being the source forthe randomness, was analysed on both the noise sources. The generated random sequences was finally subjected tostatistical tests.</p>

Denna avhandling presenterar en undersökning av orsakerna och effekterna av timingosäkerhet i Sigma-Delta Analog-Digital-Omvandlare, med speciellt fokus på Sigma-Delta av den switchade kapacitanstypen. Det undersökta området för orsakerna till timingosäkerhet är digital klockgenerering och området för effekterna är sampling. Upplösningsnivån på analysen i detta arbete börjar på beteendenivå och slutar på transistornivå. Samplingskretsen är den intuitiva komponenten att söka i efter orsakerna till effekterna av timing-osäkerhet i en Analog-Digital-Omvandlare eftersom transformationen från reell tid till digital tid sker i samplingskretsen. Därför har prestandaeffekterna av timingosäkerhet i den typiska samplingskretsen för switchad kapacitans Sigma-Delta Analog-Digital-Omvandlare analyserats utförligt, modellerats och beskrivits i denna avhandling. Under analysprocessen har idéer om förbättrade samplingskretsar med naturlig tolerans mot timing-osäkerhet utvecklats och analyserats, och presenteras även. Två typer av förbättrade samplingstopologier presenteras: parallelsamplern och Sigma-Delta-samplern. Den första erhåller tolerans mot timing-osäkerhet genom att utnyttja ett teorem inom statistiken medan den andra är tolerant mot timing-osäkerhet p.g.a. spektral formning som trycker ut brus ur signalens frekvensband. Digital klockgenerering är ett fundamentalt steg i genereringen av multipla klocksignaler som behövs t.ex. i switchade kapacitansversioner av Sigma-Delta Analog-Digital-Omvandlare. Klockgeneratorkretsarna konverterar en tidsreferens, d.v.s. en klocksignal, som vanligen kommer från en faslåst loop till multipla tidsreferenser. De två typerna av klockgenereringskretsar som behandlas i denna avhandling används för att skapa två icke-överlappande klockor från en klocksignal. Processen som undersökts och beskrivits är hur matningsspänningsbrus och substratbrus omvandlas till timing-osäkerhet då en referenssignal passerar genom en av ovannämnda klockgenereringskretsar. Resultaten i denna avhandling har erhållits genom olika analystekniker. Modelleringarna och beskrivningarna har utförts från ett matematiskt och fysikaliskt perspektiv. Detta har fördelen av att kunna förutsäga prestandainfluenser som olika kretsparametrar har utan att behöva utföra datorsimuleringar. Svårigheterna med den matematiska och fysikaliska modelleringen är balansgången mellan olöslighet och överförenkling som måste hittas. Den andra infallsvinkeln är användandet av datorbaserade simuleringsverktyg både för beskrivnings- och verifieringsändamål. Simuleringsverktygen som använts är MATLAB och Spectre/Cadence. Som nämnts har deras syfte varit både som modell- och beskrivningsverifiering och även som ett sätt att erhålla kvantitativa resultat. Generellt talat bryter simuleringsverktyg den mentala kopplingen mellan resultat och diverse kretsparametrar och det kan vara svårt att uppnå en solid prestandaförståelse. Dock är det ibland bättre att erhålla ett prestandamått utan full förståelse än inget mått alls. / This dissertation presents an investigation of the causes and effects of timing uncertainty in Sigma-Delta Analog-to-Digital Converters, with special focus on the switched-capacitor Sigma-Delta type. The investigated field for cause of timing uncertainty is digital clock generation and the field for effect is sampling. The granularity level of the analysis in this work begins at behavioral level and finishes at transistor level. The sampling circuit is the intuitive component to look for the causes to the effects of timing uncertainty in an Analog-to-Digital Converter since the transformation from real time to digital time takes place in the sampling circuit. Hence, the performance impact of timing uncertainties in a typical sampling circuit of a switched-capacitor Sigma-Delta Analog-to-Digital Converter has been thoroughly analysed, modelled, and described in this dissertation. During the analysis process, ideas of improved sampling circuits with inherent tolerance to timing uncertainties were conceived and analysed, and are also presented. Two cases of improved sampling topologies are presented: the Parallel Sampler and the Sigma- Delta sampler. The first obtains its timing uncertainty tolerance from taking advantage of a theorem in statistics whereas the second is tolerant against timing uncertainties because of spectral shaping that effectively pushes the in-band timing noise out of the signal band. Digital clock generation is a fundamental step of generating multiple clock signals that are needed for example in switched-capacitor versions of Sigma-Delta Analog-to-Digital Converters. The clock generation circuitry converts a single time reference, i.e. a clock signal, usually coming from a phase-locked loop into multiple time references. The two types of clock-generation circuits that are treated in this dissertation are used to create two nonoverlapping clocks from a single clock signal. The process that has been investigated and described is how power-supply noise and substrate noise transforms into timing uncertainty when a reference signal is passed through one of the aforementioned clock generation circuits. The results presented in this dissertation have been obtained using different analysis techniques. The modelling and descriptions have been done from a mathematical and physical perspective. This has the benefit of predicting the performance impact by different circuit parameters without the need for computer based simulations. The difficulty with the mathematical and physical modelling is the balance that has to be found between intractability and oversimplification. The other angle of approach has been the use of computer based simulations for both description and verification purposes. The simulation tools that have been used in this work are MATLAB and Spectre/Cadence. As mentioned, their purpose has been both for model and description verification and also as a means of obtaining result metrics. Generally speaking, simulation tools mentally decouple the result from the various circuit parameters and reaching a solid performance understanding can be difficult. However, obtaining a performance metric without full comprehension can at times be better than having no metric at all. / QC 20100921

L'intégration d'un plus grand nombre de fonctions sur des circuits intégrés plus rapides à chaque nouvelle génération. Malheureusement, elles ont rendu la tâche des concepteurs plus difficile, avec notamment la montée de la puissance consommée et des temps de propagation des signaux à travers la puce. La distribution de l'horloge, assurant le synchronisme des opérations du circuit, en est l'élément le plus symptomatique. La génération distribuée de l'horloge apparaît comme une alternative aux solutions classiques. Elle repose sur la mise en place d'un réseau de N oscillateurs géographiquement distribués sur l'ensemble de la puce. Chaque oscillateur génère localement une horloge pour la zone de la puce dans laquelle il se trouve. La phase d'une horloge est accordée sur celle de ces proches voisines. Ainsi, l'horloge n'a plus à parcourir de long chemin. Toutefois, les performances du circuit d'horloge sont liées, non pas à un, mais à N oscillateurs évoluant dans un environnement hostile (variations de l'alimentation, de la température, etc.). Aussi, les travaux de cette thèse portent sur la conception d'un oscillateur contrôlé numériquement. Plus précisément, notre problématique est : " Comment concevoir un DCO (Digitally Controlled Oscillator) robuste soumis à l'environnement hostile d'un SoC en technologie CMOS submicronique ? ". Pour répondre à cette question, nous proposons, dans un premier temps, la modélisation d'une topologie d'oscillateur contrôlé numériquement ; le but étant de déterminer sa pertinence quant à notre application d'horlogerie. Comme cette dernière est émergente, il n'y a à l'heure actuelle aucune théorie la caractérisant. A travers notre analyse, nous mettons en évidence ses faiblesses et la nécessité de lui adjoindre des circuits de protection. De ce fait, les performances du circuit d'horloge ne sont plus seulement dépendantes de l'oscillateur, mais aussi des dispositifs mis en place pour le protéger des agressions des circuits environnants. Ce constat a motivé le développement d'une alternative qui ne serait pas soumise aux mêmes contraintes. Nous proposons finalement un oscillateur contrôlé numériquement robuste à la fois contre les variations de l'alimentation et de la température. Cet oscillateur est conçu à partir de blocs analogiques connus et bien décrits par la littérature. Pour limiter l'influence de la tension d'alimentation et de la température à laquelle évolue l'oscillateur, nous tirons profit des effets de canal court propres aux technologies submicroniques.

Random numbers are required for cryptographic applications such as IT security products, smart cards etc. Hardwarebased random number generators are widely employed. Cryptographic algorithms are implemented on FieldProgrammable Gate Arrays (FPGAs). In this work a True Random Number Generator (TRNG) employed for spaceapplication was designed, investigated and evaluated. Several cryptographic requirements has to be satisfied for therandom numbers. Two different noise sources was designed and implemented on the FPGA. The first design wasbased on ring oscillators as a noise source. The second design was based on astable oscillators developed on a separatehardware board and interfaced with the FPGA as another noise source. The main aim of the project was to analyse theimportant requirement of independent noise source on a physical level. Jitter from the oscillators being the source forthe randomness, was analysed on both the noise sources. The generated random sequences was finally subjected tostatistical tests.

Ultrawideband (UWB) is one of the promising technologies for future short-range high data rate communications (e.g. for wireless personal area networks) and longer range low data rate communications (e.g. wireless sensor networks).Despite its various advantages and potentials (e.g. low-cost circuitry, unlicensed reuse of licensed spectrum, precision ranging capability etc.), UWB also has its own challenges. The goal of this dissertation is to identify and address some of those challenges, and provide a framework for practical UWB transceiver design.In this dissertation, various modulation options for UWB systems are reviewed in terms of their bit error rate (BER) performances, spectral characteristics, modem and hardware complexities, and data rates. Time hopping (TH) code designs for both synchronous (introduced an adaptive code assignment technique) and asynchronous UWB impulse radio (IR) systems are studied. An adaptive assignment of two different multiple access parame ters (number of pulses per symbol and number of pulse positions per frame)is investigated again considering both synchronous and asynchronous scenarios, and a mathematical framework is developed using Gaussian approximations of interference statistics for different scenarios. Channel estimation algorithms for multiuser UWB communication systems using symbol-spaced (proposed a technique that decreases the training size), frame-spaced (proposed a pulse-discarding algorithm for enhanced estimationperformance), and chip-spaced (using least squares (LS) estimation) sampling are analyzed.A comprehensive review on multiple accessing andinterference avoidance/cancellation for IR-UWB systems is presented.BER performances of different UWB modulation schemes in the presence of timing jitter are evaluated and compared in static and multipath fading channels, and finger estimation error, effects of jitter distribution, and effects of pulse shape are investigated. A unified performance analysis app roach for different IR-UWB transceiver types (stored-reference, transmitted-reference, and energy detector) employing various modulation options and operating at sub-Nyquist sampling rates is presented. The time-of-arrival (TOA) estimation performance of different searchback schemesunder optimal and suboptimal threshold settings are analyzed both for additive white Gaussian noise (AWGN) and multipath channels.

The analysis, verification and emulation of attitude control hardware for nanosatellite spacecraft is described. The overall focus is on hardware that pertains to a multitude of missions currently under development at the University of Toronto Institute for Aerospace Studies - Space Flight Laboratory. The requirements for these missions push the boundaries of what is currently the accepted performance level of attitude control hardware. These new performance envelopes demand new acceptance test methods which must verify the performance of the attitude control hardware. In particular, reaction wheel and hysteresis rod actuators are the focus. Results of acceptance testing are further employed in post spacecraft integration for hardware emulation. This provides for a reduced mission cost as a function of reduced spare hardware. The overall approach provides a method of acceptance testing to new performance envelopes with the benefit of cost reduction with hardware emulation for simulations during post integration.

The analysis, verification and emulation of attitude control hardware for nanosatellite spacecraft is described. The overall focus is on hardware that pertains to a multitude of missions currently under development at the University of Toronto Institute for Aerospace Studies - Space Flight Laboratory. The requirements for these missions push the boundaries of what is currently the accepted performance level of attitude control hardware. These new performance envelopes demand new acceptance test methods which must verify the performance of the attitude control hardware. In particular, reaction wheel and hysteresis rod actuators are the focus. Results of acceptance testing are further employed in post spacecraft integration for hardware emulation. This provides for a reduced mission cost as a function of reduced spare hardware. The overall approach provides a method of acceptance testing to new performance envelopes with the benefit of cost reduction with hardware emulation for simulations during post integration.

Zugl.: Rostock, Univ., Diss., 2007

Cloud computing is a technology that uses the internet and central remote servers to maintain data and applications. There are different cloud services of which cloud Infrastructure as a service enables a company to grow very fast. All small and large-scale companies are shifting their applications towards cloud. As usage of the internet all over the world, the number of video applications are increasing more and becoming popular. Smart phones use wireless networks to transfer large amount of data. Users access the video application from the cloud through web browsers in laptop and smart phone. First, a systematic literature review is conducted on the performance issues of cloud infrastructure as a service. Second, the performance metrics jitter, round trip time and page loading time are analyzed while accessing a video application from the cloud. Finally, results are analyzed for various browsers in Smartphone and laptop. From the obtained results it helps the users to choose better browser for accessing cloud applications.