La tendance dans la conception de cartes électroniques imprimées est de remplacer les traditionnels bus parallèles par des liens série rapides dont le débit peut atteindre plusieurs dizaines de Gigabit par seconde (Gbps). Cette thèse proposée par THALES Communications & Security en collaboration avec le laboratoire SATIE de l'ENS de Cachan a pour objectif de définir une approche adaptée au traitement des problèmes de liens multi-gigahertz, de manière à garantir le fonctionnement d'une carte numérique complexe (multicouches, haute densité d'intégration, ...) sans qu'une phase de prototypage ne soit nécessaire. Après un état de l'art, ce travail s'est organisé en trois parties : La première partie porte sur l'étude du canal de propagation. La décomposition spectrale des liens multi-gigabits couvrant plusieurs gigahertz voir plusieurs dizaines de gigahertz montre la nécessité d'employer des logiciels de simulations spécifiques au domaine des hyperfréquences. Une évaluation de certains solveurs électromagnétiques 3D parmi les plus récents a été réalisée afin d'extraire les paramètres S du canal de propagation de façon précise et rapide a partir des informations issues des logiciels de CAO utilisés à THALES. La seconde partie traite de la prise en compte des émetteurs, des récepteurs et des traitements numériques associés dans la simulation afin de réaliser des calculs de diagrammes de l'œil, de taux d'erreurs binaires (BER) et de jitter. L'utilisation de la norme IBIS-AMI, très récente, et la comparaison des performances aves d'autres outils, tel que HSPICE, a demandé l'évaluation de simulateurs circuit de dernière génération. Cette étape a été réalisée en étroite collaboration avec les éditeurs des logiciels car certains outils ne sont pas suffisamment matures pour s'inscrire dans un flot global de conception. Enfin, la chaîne de simulation complète ayant été validée par la mesure, nous avons effectué une analyse approfondie des différentes composantes du jitter en fonction des phénomènes physiques plus ou moins destructeurs pour la qualité du signal. Cela nous a ensuite permis d'établir les règles et la méthodologie de conception, en tenant compte des marges allouées à partir des résultats de l'analyse du jitter.

Next generation communication systems are reaching 110Gbps rates. At these frequencies, the skin effect and dielectric loss of copper cables cause inter-symbol interference (ISI) and frequency dependent loss, severely limiting the channel bandwidth. In this thesis, different methods for alleviating ISI are explored. The design of the critical blocks of an adaptive channel equalizer with up to two times oversampling are presented. The circuits were fabricated in a 0.13μm SiGe BiCMOS technology. The linear, adaptive equalizer operates up to 70Gbps and its measured S-parameters exhibit a single-ended peak gain of 12.2dB at 52GHz, allowing for 31dB of peaking between DC and 52GHz. Equalization is demonstrated experimentally at 59Gbps for a cable loss of 17.9dB. These results make it the fastest receive equalizer published to date. A retiming flip-flop operating between 72 and 118 GHz, the highest reported in silicon, is also designed and characterized, showing less than 500-fs jitter.

Next generation communication systems are reaching 110Gbps rates. At these frequencies, the skin effect and dielectric loss of copper cables cause inter-symbol interference (ISI) and frequency dependent loss, severely limiting the channel bandwidth. In this thesis, different methods for alleviating ISI are explored. The design of the critical blocks of an adaptive channel equalizer with up to two times oversampling are presented. The circuits were fabricated in a 0.13μm SiGe BiCMOS technology. The linear, adaptive equalizer operates up to 70Gbps and its measured S-parameters exhibit a single-ended peak gain of 12.2dB at 52GHz, allowing for 31dB of peaking between DC and 52GHz. Equalization is demonstrated experimentally at 59Gbps for a cable loss of 17.9dB. These results make it the fastest receive equalizer published to date. A retiming flip-flop operating between 72 and 118 GHz, the highest reported in silicon, is also designed and characterized, showing less than 500-fs jitter.

Communication security is a very important part of modern life. A crucial aspect of security is the ability to identify with near 100% certainty who is on the other side of a connection. This problem can be overcome through the use of random number generators, which create unique identities for each person in a network. The effectiveness of an identity is directly proportional to how random a generator is. The speed at which a random number can be delivered is a critical factor in the design of a random number generator. This thesis covers the design and fabrication of three ring oscillator based truly random number generators, the first two of which were fabricated in 0.13µ m CMOS technology. The randomness from this type of random number generator originates from phase noise in a ring oscillator. The second and third ring oscillators were designed to have a low slew rate at the inverter switching threshold. The outputs of these designs showed vast increases in timing jitter compared to the first design. The third design exhibited improved randomness with respect to the second design.

Aim : The purpose of this study was to examine the impact of simulated hearing loss on the acoustic contrasts between declarative questions and declarative statements and on the perception of speech intonation. A further purpose of the study was to investigate whether any such effects are universal or language specific. Method: Speakers included four native speakers of English and four native speakers of Mandarin and Taiwanese, with two female and two male adults in each group. Listeners included ten native English and ten native speakers of Mandarin and Taiwanese, with five female and five male adults in each group. All participants were aged between 19 and 55 years old. The speaker groups were asked to read a list of 28 phrases, with each phrase expressed as a declarative statement or a declarative question separately. These phrases were then filtered through six types of simulated hearing loss configurations, including three levels of temporal jittering for simulating a loss in neural synchrony, a high level of temporal jittering in combination with a high-pass or a low-pass filter that simulate falling and rising audiometric hearing loss configurations, and a vocoder processing procedure to simulate cochlear implant processing. A selection of acoustic measures was derived from the sentences and from some embedded vowels, including /i/, /a/, and /u/. The listener groups were asked to listen to the tokens in their native language and indicate if they heard a statement or a question. Results: The maximum fundamental frequency (F0) of the last syllable (MaxF0-last) and the maximum F0 of the remaining sentence segment (MaxF0-rest) were found to be consistently higher in declarative questions than in declarative statements. The percent jitter measure was found to worsen with simulated hearing loss as the level of temporal jittering increased. The vocoder-processed signals showed the highest percent jitter measure and the spread of spectral energy around the dominant pitch. Results from the perceptual data showed that participants in all three groups performed significantly worse with vocoder-processed tokens compared to the original tokens. Tokens with temporal jitter alone did not result in significantly worse perceptual results. Perceptual results from the Taiwanese group were significantly worse than the English group under the two filtered conditions. Mandarin listeners performed significantly worse with the neutral tone on the last syllable, and Taiwanese listeners performed significantly worse with the rising tone on the last syllable. Perception of male intonation was worse than female intonation with temporal jitter and high-pass filtering, and perception of female intonation was worse than male intonation with most temporal jittering conditions, including the temporal jitter and low-pass filtering condition. Conclusion: A rise in pitch for the whole sentence, as well as that in the final syllable, was identified as the main acoustic marker of declarative questions in all of the three languages tested. Perception of intonation was significantly reduced by vocoder processing, but not by temporal jitter alone. Under certain simulated hearing loss conditions, perception of intonation was found to be significantly affected by language, lexical tone, and speaker gender.

The overall aim of this thesis is to increase our knowledge of the physical environment of office workers with special focus on electromagnetic fields and to address the question of whether electromagnetic fields can directly or indirectly contribute to symptoms or discomfort among video display terminal ( VDT) workers. Furthermore, we have measured light modulation from various commonly used light sources in laboratory conditions and, as a second step, used modulated light as stimulus for provocation of neurophysiological responses in persons with perceived “electrical hypersensitivity” (EHS).During the last 20 years work-related illness among office workers has received increased attention. Changes in the physical environment, the introduction of VDTs and other electrical equipment and changes in light conditions have been discussed in this context. The basis for this thesis is the interdisciplinary Office Illness Project in Northern Sweden. Using a questionnaire completed by 4,943 office workers, 150 VDT workers with or without facial skin symptoms were selected for a case referent study of the electromagnetic fields in offices.When the measurements in the offices were performed in 1989, the general level of the 50 Hz magnetic fields in the offices was rather low, but in 5% of the offices the flux density exceeded 0.5 pT. At this level VDT monitors were shown to display detectable instability (jitter). Furthermore, the ability of test subjects (healthy volunteers) to detect jitter was shown to depend on both the amplitude and frequency characteristics of this instability. The study indicates that the instability of computer monitors and thereby the instability of the visual image of the VDT screen might be an increasing problem since it is known that the harmonic content of the general magnetic field in offices is on the rise.VDT monitors contributed to the magnetic field level at VDT workplaces in both extremely low and very low frequency ranges. However, the dominant source of electric fields in rooms was ungrounded electrical equipment, not VDT screens.High electric fields in the extremely low frequency range in the offices were associated with skin symptoms among VDT workers. The causal nature of this association cannot be determined since it may depend on undetected factors related to exposure. No associations were found, however, for any of the VDT-related electromagnetic fields and skin symptoms.Commonly used fluorescent tubes in our office environment have a degree of modulation of the light (flicker) that varies widely from less than 1% (fluorescent tubes with high frequency gear) up to nearly 100%. When persons with perceived EHS were exposed to flickering light, a higher amplitude of brain cortex responses were found at all tested frequencies compared with control subjects. These findings are of considerable interest, but further studies are required in order to establish a possible relationship between flickering light and discomfort/symptoms in persons with perceived EHS. / digitalisering@umu

Time-interleaved analog-to-digital converters are an attractive architecture for achieving a high speed, high resolution ADC in a power efficient manner. However, due to process and manufacturing variations, timing skews occur between the sampling clocks of the sub ADCs within the TI-ADC. These timing skews compromise the spurious free dynamic range of the converter. In addition, jitter on the sampling clocks, degrades the signal-to-noise ratio of the TI-ADC. Therefore, in order to maintain an acceptable spurious free dynamic range and signal to noise ratio, it is necessary to correct the timing skews while adding minimal jitter. Two analog-based architectures for correcting timing skews were investigated, with one being selected for implementation. The selected architecture and additional test circuitry were designed and fabricated in a 0.18??m CMOS process and tested using a 125 MSPS 16 bit ADC. The circuit achieves a correction precision on the order of 10???s of femtoseconds for timing skews as large as approximately 180 picoseconds, while adding less than 200 femtoseconds of rms jitter.

Stuttgart, Univ., Diss., 2007.

Apresentamos um novo Protocolo de Controle de Transporte fim-a-fim, implementado somente do lado do transmissor, chamado TCP HolyWood ou, abreviadamente, TCP-HW. Em um ambiente de rede cabeada simulada, TCP HolyWood supera em vazão media três dos mais importantes protocolos TCPs já elaborados. Estamos falando de TCP Reno, TCP Westwood, e TCP Vegas; e em variação de retardo media ao TCP Reno bem como ao TCP Vegas. Alem disso, de acordo com o índice de Jain, nossa proposta e tão imparcial quanto o padrão, TCP Reno. / We introduce a new end-to-end, sender side Transport Control Protocol called TCP HolyWood or in short TCP-HW. In a simulated wired environment, TCP HolyWood outperforms in average throughput, three of the more important TCP protocols ever made, we are talking about TCP Reno, TCP Westwood, and TCP Vegas; and in average jitter to TCP Reno and TCP Vegas too. In addition, according to Jain’s index, our proposal is as fair as TCP Reno, the Standard.

Technological advancements in video technology have placed stringent requirements on video analog front ends (AFEs) to deliver high resolutions crisp images while consuming low power to deliver optimal performance. One of the vital parts of an AFE is a delay locked loop (DLL). The DLL is a first order system that aligns  a delayed signal with respect to a reference signal while working in a feedback manner. DLLs find their applications in many electronic devices that deal with clocks in their operation. They are used to improve timing margins and clock delays in microprocessors, memory elements and other such applications. The vital function of a DLL is to delay the input clock (one period delay), by passing it through delay line and aligning the input clock and the delayed clock of the DLL through phase detector. Once this is done multiple phases canbe derived from various stages of the delay line with each providing a stable clock signal that is a delayed version of the input clock. Due to the increasing clock speeds this task of deriving multiple phases has become quite cumbersome. The task may become complicated due to noise generated from switching activity in digital circuits thus resulting in jitter at DLL output. As the design of analog circuits becomes quite exigent especially below the 100 nm mark, the goal hereis to design an all digital DLL to take advantage of the 65 nm process and a simplified design cycle. The aim of this thesis is to implement an all digital delay locked loop with an input frequency range of 60 MHz to 300 MHz with a worst case jitter of 66 ps.The DLL provides 32 uniformly spaced phases between input and output clocks.The DLL operation is divided in to two stages. In the first step the first delayline quantizes input clock period with the help of a binary time to digital converter.Based on this quantization information second delay line introduces actual delay between input and output clocks with 32 intermediate phases in between.The entire process takes up to 9 clock cycles until a lock state is achieved. These 32 phases provide a greater phase resolution enhancing the sync processing characteristics of the video AFE thus improving the one screen display characteristics.