Leakage current and process variations are two primary hurdles in modern VLSI design. It depends exponentially on process and environmental parameters and hence small variations in these result in a large spread in leakage current of manufactured dies. Traditionally, Exponential Quadratic(EQ) models have been used to model leakage current as a function of process parameters which can model limited non-linearity and hence become inaccurate for large process variations. Artificial Neural Networks (ANN) have shown great promise in modeling circuit parameters for CAD applications. We model leakage with ANN models which perform better than the EQ models for increased process variations. However, the complex nature of the ANN model, with the standard sigmoidal activation functions, does not allow analytical expressions for its mean and variance for the case of Gaussian process variations. We propose the use of a new activation function that allows us to derive an analytical expression for the mean and a semi-analytical expression for the variance of the ANN based leakage model. To the best of our knowledge this is the first result in this direction. All existing SLA frameworks are closely tied to the EQ leakage model and hence fail to work with sophisticated ANN models. We therefore set up an SLA framework that can efficiently work with these ANN models. Results show that the CDF of leakage current of ISCAS'85 circuits can be predicted accurately with the error in mean and standard deviation, compared to Monte Carlo based simulations, being less than 1\% and 2\% respectively across a range of voltage and temperature values. The complexity of our framework is similar to existing SLA frameworks yet more accurate over a larger range of variations. Ignoring the thermal profile of the chip leads to a gross error of nearly 50\% in the prediction of leakage yield. Our neural network model also includes the voltage and temperature as input parameters, thereby enabling voltage and temperature aware statistical leakage analysis (SLA). Similarly leakage CDF can be predicted across a range of supply and body voltages since they are both part of the model. Our framework used analytical techniques to account for local variations and Monte Carlo techniques for global variations and hence it can also be used for Non-Gaussian global variations.

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In it´s first part, this presented master´s thesis focuses on the problematics of actions taking place in dielectric materials and phenomenons on the surface of real insulators placed in electric field. This research is followed by selection and rating of appropriate ceramic materials for the actual design of the metal – ceramic assembly. The greatest emphasis is given to design of the optimal configuration of the insulator and electrode, which is supported by simulations from the software that implements finite element method. Eventually, the high voltage tests of the assembly used for measuring leakage currents are performed.

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Der Graben-Gate-MOSFET ist eine herausragende Bauelementarchitektur unter den vertikalen Bauelementen auf GaN-Basis, die derzeit für die nächste Generation der Leistungselektronik untersucht werden. Ein niedriges Reststromniveau im Aus-Zustand bei hoher Drain-Spannung ist für vertikale Transistoren von großer Bedeutung, da es ein entscheidendes Merkmal für eine hohe Durchbruchspannung und Zuverlässigkeit der Bauelemente ist. Die Drain-Restströme im Aus-Zustand haben ihren Ursprung in verschiedenen Quellen im vertikalen Trench-Gate-MOSFET. Neben dem Trench-Gate-Modul können auch die Reststrompfade an der trockengeätzten Seitenwand des lateralen Kantenabschlusses erheblich zum Drain-Reststrom im Aus-Zustand beitragen. In diesem Bericht wird der Einfluss jedes relevanten Prozessschritts auf den Drain-Reststrom im Aus-Zustand anhand spezifischer Teststrukturen auf hochwertigem epitaktischem GaN-Material, welche den lateralen Kantenabschluss des MOSFETs nachbilden, untersucht. Die elektrische Charakterisierung zeigt die Empfindlichkeit des Reststroms gegenüber plasmabezogenen Prozessen. Es wird eine Technologie der Randterminierung vorgestellt, die zu einem niedrigen Reststrom führt und gleichzeitig dicke dielektrische Schichten aus plasma-unterstützter Abscheidung enthält, die für die Herstellung einer Feldplattenstruktur über dem Kantenabschluss vorgesehen sind. / The trench gate MOSFET represents a prominent device architecture among the GaN based vertical devices currently investigated for the next generation of power electronics. A low leakage current level in off-state under high drain bias is of great importance for vertical transistors since it is a crucial feature for high breakdown voltage and device reliability. The off-state drain leakage originates from different sources in the vertical trench gate MOSFET. Besides the trench gate module, the leakage paths at the dry-etched sidewall of the lateral edge termination can also significantly contribute to the off-state drain-current. In this report, the influence of each relevant process step on the drain leakage current in off-state is investigated utilizing specific test structures on high-quality GaN epitaxial material which mimic the lateral edge termination of the MOSFET. Electrical characterization reveals the sensitivity of the leakage current to plasma-related processes. A termination technology is presented that results in low leakage current while including thick dielectric layers from plasma-assisted deposition as intended for fabrication of a field plate structure over the edge termination.

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Les transistors ayant un faible niveau de bruit à basse fréquence, une faible puissance de dissipation et fonctionnant à basse température (≤ 4.2 K) sont actuellement inexistants alors qu’ils sont très demandés pour la réalisation de préamplificateurs à installer au plus près des détecteurs ou des dispositifs à la température de quelques dizaines de mK, dans le domaine de l’astrophysique, de la physique mésoscopique et de l’électronique spatiale. Une recherche menée depuis de nombreuses années au LPN vise à réaliser une nouvelle génération de HEMTs (High Electron Mobility Transistors) cryogéniques à haute performance pour répondre à ces demandes. Cette thèse, dans le cadre d’une collaboration entre le CNRS/LPN et le CEA/IRFU, a pour but la réalisation de préamplificateurs cryogéniques pour des microcalorimètres à 50 mK.Les travaux de cette thèse consistent en des caractérisations systématiques des paramètres électriques et des bruits des HEMTs (fabriqués au LPN) à basse température. En se basant sur les résultats expérimentaux, l’une des sources de bruit à basse fréquence dans les HEMTs a pu être identifiée, c’est-à-dire la part du courant tunnel séquentiel dans le courant de fuite de grille. Grâce à ce résultat, les hétérostructures ont été optimisées pour minimiser le courant de fuite de grille ainsi que le niveau de bruit à basse fréquence. Au cours de cette thèse, différentes méthodes spécifiques ont été développées pour mesurer de très faibles valeurs de courant de fuite de grille, les capacités du transistor et le bruit 1/f du transistor avec une très haute impédance d’entrée. Deux relations expérimentales ont été observées, l’une sur le bruit 1/f et l’autre sur le bruit blanc dans ces HEMTs à 4.2 K. Des avancées notables ont été réalisées, à titre d’indication, les HEMTs avec une capacité de grille de 92 pF et une consommation de 100 µW peuvent atteindre un niveau de bruit en tension de 6.3 nV/√Hz à 1 Hz, un niveau de bruit blanc de 0.2 nV/√Hz et un niveau de bruit en courant de 50 aA/√Hz à 10 Hz. Enfin, une série de 400 HEMTs, qui répondent pleinement aux spécifications demandées pour la réalisation de préamplificateurs au CEA/IRFU, a été réalisée. Les résultats de cette thèse constitueront une base solide pour une meilleure compréhension du bruit 1/f et du bruit blanc dans les HEMTs cryogéniques afin de les améliorer pour les diverses applications envisagées. / Transistors with low noise level at low frequency, low-power dissipation and operating at low temperature (≤ 4.2 K) are currently non-existent, however, they are widely required for realizing cryogenic preamplifiers which can be installed close to sensors or devices at a temperature of few tens of mK, in astrophysics, mesoscopic physics and space electronics. Research conducted over many years at LPN aims to a new generation of high-performance cryogenic HEMTs (High Electron Mobility Transistors) to meet these needs. This thesis, through the collaboration between the CNRS/LPN and the CEA/IRFU, aims for the realization of cryogenic preamplifiers for microcalorimeters at 50 mK.The work of this thesis consists of systematic characterizations of electrical and noise parameters of the HEMTs (fabricated at LPN) at low temperatures. Based on the experimental results, one of the low-frequency-noise sources in the HEMTs has been identified, i.e., the sequential tunneling part in the gate leakage current. Thanks to this result, heterostructures have been optimized to minimize the gate leakage current and the low frequency noise. During this thesis, specific methods have been developed to measure very low-gate-leakage-current values, transistor’s capacitances and the 1/f noise with a very high input impedance. Two experimental relationships have been observed, one for the 1/f noise and other for the white noise in these HEMTs at 4.2 K. Significant advances have been made, for information, the HEMTs with a gate capacitance of 92 pF and a consumption of 100 µW can reach a noise voltage of 6.3 nV/√ Hz at 1 Hz, a white noise voltage of 0.2 nV/√ Hz, and a noise current of 50 aA/√Hz at 10 Hz. Finally, a series of 400 HEMTs has been realized which fully meet the specifications required for realizing preamplifiers at CEA/IRFU. The results of this thesis will provide a solid base for a better understanding of 1/f noise and white noise in cryogenic HEMTs with the objective to improve them for various considered applications.

Dans les années 2000, les composants de puissance en carbure de silicium (SiC) font leur apparition sur le marché industriel offrant d'excellentes performances. Elles se traduisent par de meilleurs rendements et des fréquences de découpage plus élevées, entrainant une réduction significative du volume et de la masse des convertisseurs de puissance. Le SiC présente de plus un potentiel important de fonctionnement en haute température (>200°C) et permet donc d'envisager de placer l'électronique dans des environnements très contraints jusqu'alors inaccessibles. Pourtant les parts de marche du SiC restent limitées dans l'industrie vis à vis du manque de retour d'expérience concernant la fiabilité de ces technologies relativement nouvelles. Cette question reste aujourd'hui sans réponse et c'est avec cet objectif qu'a été menée cette étude axée sur le vieillissement et l'analyse des mécanismes de dégradation sur des composants de puissance SiC pour des applications haute température. Les tests de vieillissement ont été réalisés sur des transistors MOSFET SiC car ces composants attirent les industriels grâce à leur simplicité de commande et leur sécurité "normalement bloqué" (Normally-OFF). Néanmoins, la fiabilité de l'oxyde de grille est le paramètre limitant de cette structure. C'est pourquoi l'étude de la dérive de la tension de seuil a été mesurée avec une explication du phénomène d'instabilité du VTH. Les résultats ont montré qu'avec l'amélioration des procédés de fabrication, l'oxyde du MOSFET est robuste même pour des températures élevées (jusqu'à 300°C) atteintes grâce à un packaging approprié. Les durées de vie moyennes ont été extraites grâce à un banc de vieillissement accéléré développé pour cette étude. Des analyses macroscopiques ont été réalisées afin d'observer l'évolution des paramètres électriques en fonction du temps. Des études microscopiques sont conduites dans l'objectif d'associer l'évolution des caractéristiques électriques par rapport aux dégradations physiques internes à la puce. Pour notre véhicule de test, la défaillance se traduit par un emballement du courant de grille en régime statique et par l'apparition de fissures dans le poly-Silicium de la grille. Pour finir, une étude de comparaison avec des nouveaux transistors MOSFET a été réalisée. Ainsi l'analogie entre ces composants s'est portée sur des performances statiques, dynamiques, dérivé de la tension de seuil et sur la durée de vie moyenne dans le test de vieillissement. Le fil rouge de ces travaux de recherche est une analyse des mécanismes de dégradation avec une méthodologie rigoureuse permettant la réalisation d'une étude de fiabilité. Ces travaux peuvent servir de base pour toutes analyses d'anticipation de défaillances avec une estimation de la durée de vie extrapolée aux températures de l'application visée / Since 2000, Silicon Carbide (SiC) power devices have been available on the market offering tremendous performances. This leads to really high efficiency power systems, and allows achieving significative improvements in terms of volume and weight, i.e. a better integration. Moreover, SiC devices could be used at high temperature (>200°C). However, the SiCmarket share is limited by the lack of reliability studies. This problem has yet to be solved and this is the objective of this study : aging and failure mechanisms on power devices for high temperature applications. Aging tests have been realized on SiC MOSFETs. Due to its simple drive requirement and the advantage of safe normally-Off operation, SiCMOSFET is becoming a very promising device. However, the gate oxide remains one of the major weakness of this device. Thus, in this study, the threshold voltage shift has been measured and its instability has been explained. Results demonstrate good lifetime and stable operation regarding the threshold voltage below a 300°C temperature reached using a suitable packaging. Understanding SiC MOSFET reliability issues under realistic switching conditions remains a challenge that requires investigations. A specific aging test has been developed to monitor the electrical parameters of the device. This allows to estimate the health state and predict the remaining lifetime.Moreover, the defects in the failed device have been observed by using FIB and SEM imagery. The gate leakage current appears to reflect the state of health of the component with a runaway just before the failure. This hypothesis has been validated with micrographs showing cracks in the gate. Eventually, a comparative study has been realized with the new generations of SiCMOSFET

A new high-k dielectric material, i.e., zirconium-doped tantalum oxide (Zr-doped TaOx), in the form of a sputter-deposited thin film with a thickness range of 5-100 nm, has been studied. Important applications of this new dielectric material include the gate dielectric layer for the next generation metal-oxide-semiconductor field effect transistor (MOSFET). Due to the aggressive device scaling in ultra-large-scale integrated circuitry (ULSI), the ultra-thin conventional gate oxide (SiO2) is unacceptable for many practical reasons. By replacing the SiO2 layer with a high dielectric constant material (high-k), many of the problems can be solved. In this study, a novel high-k dielectric thin film, i.e., TaOx doped with Zr, was deposited and studied. The film’s electrical, chemical, and structural properties were investigated experimentally. The Zr dopant concentration and the thermal treatment condition were studied with respect to gas composition, pressure, temperature, and annealing time. Interface layer formation and properties were studied with or without an inserted thin tantalum nitride (TaNx) layer. The gate electrode material influence on the dielectric properties was also investigated. Four types of gate materials, i.e., aluminum (Al), molybdenum (Mo), molybdenum nitride (MoN), and tungsten nitride (WN), were used in this study. The films were analyzed with ESCA, XRD, SIMS, and TEM. Films were made into MOS capacitors and characterized using I-V and C-V curves. Many promising results were obtained using this kind of high-k film. It is potentially applicable to future MOS devices.

In the last three decades, the electronic industry has registered a tremendous progress. The continuous and aggressive downsizing of the transistor feature sizes (CMOS scaling) has been the main driver of the astonishing growth and advancement of microelectronic industry. Currently, the CMOS scaling is almost reaching its limits. The gate oxide is now only a few atomic layers thick, and this extremely thin oxide causes a huge leakage current through the oxide. Therefore, a further reduction of the gate oxide thickness is extremely difficult and new materials with higher dielectric constant are being explored. However, the phenomena of oxide breakdown and reliability are still serious issues in these thin oxides. Oxide breakdown exhibits a soft breakdown behavior at low voltages, and this is posing as one of the most crucial reliability issues for scaling of the ultra-thin oxides. In addition, the stress-induced leakage current (SILC) due to oxide has emerged as a scaling problem for the non-volatile memory technologies. In this dissertation, a percolation modeling approach is introduced to study and understand the dramatic changes in the conductivity of a disordered medium. Two different simulation methods of percolative conduction, the site and bond percolation, are studied here. These are used in simulating the post-breakdown conduction inside the oxide. Adopting a Monte-Carlo method, oxide breakdown is modeled using a 2-D percolation theory. The breakdown statistics and post-breakdown characteristics of the oxide are computed using this model. In this work, the effects of different physical parameters, such as dimension and the applied stress are studied. The simulation results show that a thinning of oxide layer and increasing the oxide area result in softening of breakdown. It is observed that the breakdown statistics appear to follow Weibull characteristics. As revealed by simulations, the Weibull slope changes linearly with oxide thickness, while not having a significant change when the area is varied and when the amount of the applied stress is varied. It is shown that the simulation results are well correlated with the experimental data reported in the literature. In this thesis, studying the conduction through the oxide using percolation model, it was discovered that a critical or a quasi-critical phenomenon occurs depending on the oxide dimensions. The criticality of the phase-transition results in a hard breakdown while the soft breakdown occurs due to a quasi-critical nature of percolation for ultra-thin oxides. In the later part of the thesis, a quantum percolation model is studied in order to explain and model the stress induced leakage current. It is explained that due to the wave nature of electrons, the SILC can be modeled as a tunneling path through the stressed oxide with the smaller tunneling threshold compared to the virgin oxide. In addition to the percolation model, a Markov chain theory is introduced to simulate the movement of electron as a random walk inside the oxide, and the breakdown is simulated using this random-walk of electron through the accumulated traps inside the oxide. It is shown that the trapping-detrapping of electrons results in an electrical noise in the post-breakdown current having 1/f noise characteristics. Using simulation of a resistor network with Markov theory, the conductance of the oxide is computed. An analytical study of a 2-D site percolation system is conducted using recursive methods and useful closed-form expressions are derived for specialized networks.