In the last three decades, the electronic industry has registered a tremendous progress. The continuous and aggressive downsizing of the transistor feature sizes (CMOS scaling) has been the main driver of the astonishing growth and advancement of microelectronic industry. Currently, the CMOS scaling is almost reaching its limits. The gate oxide is now only a few atomic layers thick, and this extremely thin oxide causes a huge leakage current through the oxide. Therefore, a further reduction of the gate oxide thickness is extremely difficult and new materials with higher dielectric constant are being explored. However, the phenomena of oxide breakdown and reliability are still serious issues in these thin oxides. Oxide breakdown exhibits a soft breakdown behavior at low voltages, and this is posing as one of the most crucial reliability issues for scaling of the ultra-thin oxides. In addition, the stress-induced leakage current (SILC) due to oxide has emerged as a scaling problem for the non-volatile memory technologies. In this dissertation, a percolation modeling approach is introduced to study and understand the dramatic changes in the conductivity of a disordered medium. Two different simulation methods of percolative conduction, the site and bond percolation, are studied here. These are used in simulating the post-breakdown conduction inside the oxide. Adopting a Monte-Carlo method, oxide breakdown is modeled using a 2-D percolation theory. The breakdown statistics and post-breakdown characteristics of the oxide are computed using this model. In this work, the effects of different physical parameters, such as dimension and the applied stress are studied. The simulation results show that a thinning of oxide layer and increasing the oxide area result in softening of breakdown. It is observed that the breakdown statistics appear to follow Weibull characteristics. As revealed by simulations, the Weibull slope changes linearly with oxide thickness, while not having a significant change when the area is varied and when the amount of the applied stress is varied. It is shown that the simulation results are well correlated with the experimental data reported in the literature. In this thesis, studying the conduction through the oxide using percolation model, it was discovered that a critical or a quasi-critical phenomenon occurs depending on the oxide dimensions. The criticality of the phase-transition results in a hard breakdown while the soft breakdown occurs due to a quasi-critical nature of percolation for ultra-thin oxides. In the later part of the thesis, a quantum percolation model is studied in order to explain and model the stress induced leakage current. It is explained that due to the wave nature of electrons, the SILC can be modeled as a tunneling path through the stressed oxide with the smaller tunneling threshold compared to the virgin oxide. In addition to the percolation model, a Markov chain theory is introduced to simulate the movement of electron as a random walk inside the oxide, and the breakdown is simulated using this random-walk of electron through the accumulated traps inside the oxide. It is shown that the trapping-detrapping of electrons results in an electrical noise in the post-breakdown current having 1/f noise characteristics. Using simulation of a resistor network with Markov theory, the conductance of the oxide is computed. An analytical study of a 2-D site percolation system is conducted using recursive methods and useful closed-form expressions are derived for specialized networks.

A new high-k dielectric material, i.e., zirconium-doped tantalum oxide (Zr-doped TaOx), in the form of a sputter-deposited thin film with a thickness range of 5-100 nm, has been studied. Important applications of this new dielectric material include the gate dielectric layer for the next generation metal-oxide-semiconductor field effect transistor (MOSFET). Due to the aggressive device scaling in ultra-large-scale integrated circuitry (ULSI), the ultra-thin conventional gate oxide (SiO2) is unacceptable for many practical reasons. By replacing the SiO2 layer with a high dielectric constant material (high-k), many of the problems can be solved. In this study, a novel high-k dielectric thin film, i.e., TaOx doped with Zr, was deposited and studied. The film’s electrical, chemical, and structural properties were investigated experimentally. The Zr dopant concentration and the thermal treatment condition were studied with respect to gas composition, pressure, temperature, and annealing time. Interface layer formation and properties were studied with or without an inserted thin tantalum nitride (TaNx) layer. The gate electrode material influence on the dielectric properties was also investigated. Four types of gate materials, i.e., aluminum (Al), molybdenum (Mo), molybdenum nitride (MoN), and tungsten nitride (WN), were used in this study. The films were analyzed with ESCA, XRD, SIMS, and TEM. Films were made into MOS capacitors and characterized using I-V and C-V curves. Many promising results were obtained using this kind of high-k film. It is potentially applicable to future MOS devices.

Submitted by Johnny Rodrigues (johnnyrodrigues@ufcg.edu.br) on 2018-04-21T14:21:51Z No. of bitstreams: 1 GERALDO BEZERRA LIMA JÚNIOR - DISSERTAÇÃO PPGEE 2014..pdf: 4130681 bytes, checksum: 7aa2b6dbcd9d18892be46ec5c14536b6 (MD5) / Made available in DSpace on 2018-04-21T14:21:51Z (GMT). No. of bitstreams: 1 GERALDO BEZERRA LIMA JÚNIOR - DISSERTAÇÃO PPGEE 2014..pdf: 4130681 bytes, checksum: 7aa2b6dbcd9d18892be46ec5c14536b6 (MD5) Previous issue date: 2014-09-02 / Nos dias atuais a confiabilidade e a continuidade no fornecimento de energia elétrica são cada vez mais exigidos. Os para-raios tem uma importante função neste processo que é de proteger os demais equipamentos integrantes da rede elétrica de sobretensões atmosféricas e de manobra. Quando falham, normalmente provocam o desligamento de linhas de transmissão ou de transformadores, penalizando severamente a concessionária pela indisponibilidade ou por multas impostas pela agência reguladora. Como todo equipamento importante para o sistema elétrico, os para-raios necessitam de técnicas eficazes de monitoramento. Na literatura e na indústria podem ser encontradas diversas técnicas, procedimentos ou equipamentos destinados ao seu monitoramento. Todos os procedimentos ou equipamentos possuem suas limitações, vantagens e desvantagens, sejam elas técnicas, econômicas ou operacionais. Visando suplantar algumas das limitações existentes nas técnicas e procedimentos normalmente empregados no setor elétrico, encontrase proposto neste trabalho uma metodologia de análise da condição operacional de para-raios em campo, com base em medições da corrente de fuga total. Com esta metodologia pretende-se minimizar as dificuldades operacionais relacionadas às atividades de monitoramento, uma vez que será medida apenas a corrente de fuga total, diferentemente de técnicas e procedimentos usuais que requerem também a medição da tensão aplicada. Um banco de dados de correntes de fuga foi obtido com medições realizadas em 05 (cinco) subestações. As medições foram agrupadas por modelo/fabricante e tempo de operação dos para-raios. O instrumento de medição utilizado é composto de um amperímetro do tipo alicate e um osciloscópio digital portátil. O processo de medição em campo mostrou-se efetivo e prático devido à facilidade de manuseio do instrumento utilizado. Ensaios em laboratório foram realizados para avaliação da metodologia e dos instrumentos de medição. A partir da base de dados produzida, foi possível com emprego de técnicas de processamento de sinais e estatística, observar o comportamento gaussiano dos dados e o crescimento do valor médio da componente de 3ª harmônica da corrente total em função do tempo de operação, evidenciando, assim, a correlação entre a elevação da corrente de fuga e a diminuição da vida útil dos para-raios. / Nowadays the reliability and continuity in the electricity supply are increasingly required. The surge arresters has an important function in this process, which is to protect the other utility equipment against lightning and switching surges. When they fail, usually causing the shutdown of transmission lines or transformers, severely penalizing the power utility for the unavailability or regulator fines. As any important equipment for the electrical system, surge arresters need effective monitoring techniques. In the literature and industry several techniques, procedures or equipment for their monitoring can be found. All procedures or devices have their limitations, advantages and disadvantages, whether technical, economic or operational. Aiming to overcome some of the limitations in existing techniques and procedures commonly employed in the electrical industry, a methodology for analyzing the surge arrester operational condition based on measurements of total leakage current is proposed in this paper. With this methodology is intended to minimize operational difficulties associated with monitoring activities, since it will only measure the total leakage current unlike the usual techniques and procedures, which require the measurement of the applied voltage, too. A database of leakage currents with measurements performed in five (05) power substations was obtained. Measurements were grouped by arresters model/manufacturer and operation time. The measuring instrument used consists of a clamp type ammeter and a portable digital oscilloscope. The process of field measurement was effective and practical due to the ease of handling of the used instrument. Laboratory tests were performed to evaluate the methodology and measuring instruments. From the database produced, it was possible through the use of techniques of signal processing and statistical observe the Gaussian behavior of the data and the average increase of the 3rd harmonic component of the total current as a function of operating time, which highlights thus, the correlation between the increase of the leakage current and the decrease of the lifetime of the surge arrester.

La miniaturisation croissante des systèmes électroniques implique de réduire la taille des composants électroniques, en particulier des composants passifs (condensateurs, résistances et inductances), notamment les condensateurs, volumineux et de surcroît nombreux. Pour répondre à cette attente, une des options est d’intégrer « enterrer » les couches capacitives dans le circuit imprimé à base de matériaux composites céramique/polymère. Dans un premier temps, plusieurs types de matériaux composites à base de nanoparticules de céramique (BaTiO3 et BaSrTiO3) et de polyester pour des condensateurs enterrés sont développés. Ensuite, la permittivité ε’ et les pertes diélectriques des composites sont évaluées dans les gammes de fréquences entre [10 kHz – 10 MHz] et [1 GHz – 5 GHz]. En vue d’intégrer ces composants à l’intérieur du circuit imprimé parfois souple et flexible, le comportement piézoélectrique des composites est évalué. La mesure du courant de fuite permettant d’effectuer une analyse qualitative des matériaux composites a été également effectuée.Au niveau de l’étude des condensateurs enterrés dans le circuit imprimé, deux structures de tests ont été réalisées : l’une montée en parallèle et l’autre en série. L’étude est réalisée sur deux gammes de condensateurs. La première est à base de matériau composite stable en fréquence et la seconde varie avec la fréquence. Pour cela, une méthode originale qui permet d’extraire la variation de la permittivité εr (f) à haute fréquence a été développée. La méthode se repose principalement sur l’utilisation des résultats de mesure de la permittivité relative du condensateur en basse fréquence, et les résultats de la valeur de la fréquence de résonance obtenue en simulation électromagnétique.Enfin, pour améliorer la fréquence de fonctionnement des condensateurs enterrés, des règles de conception permettant de comprendre l’influence des vias de connexions et de la géométrie des électrodes sur la fréquence de résonance du dispositif de test sont étudiées. / The increasing miniaturization of electronic systems involves reducing the size of electronic components, in particular passive components (capacitors, resistors and inductors), including capacitors, large and many more. To meet this expectation, one of the options is to integrate "bury" the capacitive layers based on ceramic / polymer composites in the PCB. In a first step, several types of composite materials based on nanoparticle ceramic (BaTiO3 and BaSrTiO3) and polyester for buried capacitors are developed. Then, the permittivity ε' and the dielectric losses of the composites are measured in the ranges of frequencies between [10 kHz - 10 MHz] and [1 GHz - 5 GHz]. To integrate these components within the PCBs sometimes soft and flexible, the piezoelectric behavior of composites is evaluated. The measurement of leakage current to perform a qualitative analysis of composite materials was also made.At the level of the study of buried capacitors in the circuit board, two test structures were carried out: one mounted in parallel and the other in serial. The study is produced in two ranges of capacitors. The study is conducted on two capacitors ranges. The first case, the relative permittivity does not depend on the frequency while in the second case the frequency dependence is taken into account. For this, an original method which allows to extract the permittivity εr(f) variation in high-frequency was developed. The method is mainly based on the use of measurement results of the relative permittivity of low-frequency capacitor, and the results of resonance frequency value obtained by 3D HFSS electromagnetic simulation. Finally, to improve the operating frequency of the buried capacitors, design rules allowing understand the influence of the vias and geometry of electrodes on the resonant frequency of the structures are studied.

Les matériaux III-N ont apporté un gain considérable au niveau des performances des composants pour les applications en électronique de puissance. Les potentialités majeures du GaN pour ces applications résident dans son grand champ de claquage qui résulte de sa large bande interdite, son champ de polarisation élevé et sa vitesse de saturation importante. Les hétérostructures AlGaN/GaN ont été jusqu’à maintenant le système de choix pour l’électronique de puissance. Les limites sont connues et des alternatives sont étudiées pour les surmonter. Ainsi, les hétérostructures InAlN/GaN en accord de maille ont suscité beaucoup d’intérêts, notamment pour des applications en électronique de puissance à haute fréquence. L’enjeu de ce travail de thèse consiste à élaborer et caractériser des hétérostructures HEMTs (High Electron Mobility Transistors) afin d’établir des corrélations entre défauts structuraux, électriques et procédés de fabrication. Une étude sera donc menée sur la caractérisation de composants AlGaN/GaN afin de cerner les paramètres de croissance susceptibles d’avoir un impact notable sur la qualité structurale et électrique de la structure, notamment sur l’isolation électrique des couches tampons et le transport des porteurs dans le canal. En ce qui concerne les HEMTs InAlN/GaN, l’objectif est d’évaluer la qualité de la couche barrière. Pour cela, une étude de l’influence des épaisseurs ainsi que la composition de la barrière sera menée. La combinaison de ces études permettra d’identifier la structure optimale. Ensuite, l’analyse des contacts Schottky par des mesures de courant et de capacité à différentes températures nous permettra d’identifier les différents modes de conduction à travers la barrière. Enfin, les effets de pièges qui constituent l’une des limites fondamentales inhérentes aux matériaux étudiés seront caractérisés par différentes méthodes de spectroscopie de défauts. / III-N materials have made a significant gain in component performance for power electronics applications. The major potential of GaN for these applications lies in its large breakdown field resulting from its wide bandgap, high polarization field and high electronic saturation velocity. AlGaN/GaN heterostructures have been, until recently, the system of choice for power electronics. The limits are known and alternatives are studied to overcome them. Thus, lattice matched InAlN/GaN heterostructures have attracted a great deal of research interest, especially for high frequency power electronic applications. The aim in this work of thesis consists in developing and in characterizing High Electron Mobility Transistors (HEMTs) to establish correlations between structural, electrical defects and technologic processes. A study will therefore be conducted on the characterization of AlGaN/GaN components to enhance the parameters of growth susceptible to have a notable impact on the structural and electrical quality of the structure, in particular on the electrical isolation of the buffer layers and the transport properties. For InAlN/GaN HEMTs, the objective is to evaluate the quality of the barrier layer. For this, a study of the influence of the thickness as well as the composition of the barrier will be conducted. The combination of these studies will allow identifying the optimum structure. Then, the analysis of Schottky contacts by measurements of current and capacity at different temperatures will allow us to identify the several conduction modes through the barrier. Finally, the effects of traps which constitute one of the fundamental limits inherent to the studied materials will be characterized by various defects spectroscopy methods.

This work deals with questions about the measuring of the tantalum capacitor leakage current. This thesis answers to many questions of this sphere e.g. Study of basic parameters, analysis of the measurment LI Head, creating software for the connection between the measuring LI Head, the computer and the analog measuring card, activation of the measuring set, verification of set functionality and economic evaluation of the whole project.

The aim of the thesis is to examine the dielectric function Ta2O5 insulating layers in tantalum capacitors. The capacitor plugged in the regular mode represents a MIS structure of reverse direction. Three different factors can be determined for the residual current of the component according to its charge transmission mode: the ohmic, Pool–Frenkel, tunnel and Schottky. An apparatus was constructed by the author of the thesis to measure the temporary connection between residual current and rise of temperature of the tantalum capacitors. Annealing of three different sets of tantalum capacitors made by different producers was performed at the temperature of 400 K and nominal voltage of 35 V during the period of 20 days.The experiment has proved the residual current in the electric field changes with rising temperature in time as a result of the ion movement. The singular factors of the residual current are influenced during the process. By the “ion movement” is meant the ion drift influenced by the attached electric field and diffusion caused by the concentration gradient. First, the samples were being annealed for c. 2 x 106 s, and then the residual current was being regenerated under the voltage of 5 V for 106 s. The residual current values increased considerably after annealing, and decreased again to more or less the original level after the regeneration, some of the samples reaching even values bellow the original level. The VA characteristics of the samples measured before and after the process of controlled obsolescence, and after the regeneration prove not only a change in parameters of the different current factors, but also a change of the current transmission mechanism employed in the process.

High electron mobility transistors (HEMTs) realized using AlxGa1-xN/GaN are relatively new technology which is prominent for high-speed and high-power applications. Some of the main problems with this technology were identified as dynamic RDSon, current collapse and threshold voltage instabilities due to the off-state stress. What was less investigated is the effect of the off-state stress on the leakage current at lower voltages. In this work, multiple devices with various initial leakage currents are stressed at different stress conditions (drain voltage, temperature, duration) and the development of drain-source on-state resistance (RDSon), threshold voltage (Vth) and drain-source leakage current (IDSS) after stress are tracked. It was found out that devices with initially higher leakage exhibit higher RDSon and Vth before stress, which simulations attributed to the higher Al mole fraction in the back-barrier or less unintentional doping in the channel layer. During the off-state stress (VDS = 900 V), the leakage current shortly rises and then sharply drops, presumably because of the charge redistribution in the back-barrier. After the stress, no larger changes were observed for RDSon and Vth , but they were for the leakage current i.e., initially low leakage devices had post-stress leakage increase, while initially high leakage devices had post-stress leakage decrease. This is assumed to be caused by the charge redistribution. Parasitic capacitance measurements showed the rise of the pre-stress input, output and reverse transfer capacitances with the pre-stress leakage, which could presumably be explained by higher Al mole fraction inducing more charges in the channel layer, deeming higher Al mole fraction in the back-barrier as a main assumed cause for all the observed effects. After the stress, capacitance changes were tentatively explained by the charge redistribution in the back-barrier. Finally, high temperature was shown to significantly reduce the observed long time to recovery. However, more measurements are needed to further observe this influence. Additionally, more experiments (e.g., on wafer, G-ω measurement, etc.) are needed in general to further investigate the mechanisms behind these memory effects. / Transistorer med extra hög elektronmobilitet, sk HEMT-ar (high electron mobility transistor) kan fabriceras med hjälp av materialen galliumnitrid (GaN) och aluminium-galliumnitrid (AlxGa1-xN). GaN HEMT-ar lämpar sig mycket väl för kraftkomponenter för höga frekvenser. Några av problemen med denna nya teknologi är hög resistans mellan ”drain” och ”source”, RDSon, reduktion av mättnadsströmmen (”current collapse”) och instabiliteter hos styrets tröskelspänning (Vth) när komponenterna stressas i avslaget tillstånd. Mindre känt är effekterna av stress för en avslagen komponent på läckströmmen (IDSS) vid låga påkänningar. I detta arbete har komponenter med varierande läckströmmar utsatts för olika typer av stress, t ex drain-spänning och höjd temperatur under olika långa tider samtidigt som parametrarna RDSon, Vth och IDSS har uppmätts. Det kunde noteras att komponenter med initialt högre läckströmmar hade högre RDSon och Vth innan de utsattes för stress, vilket med hjälp av simuleringar kunde visas bero på högre Al-molfraktion i skiktet under AlxGa1-xN-lagret, alternativt lägre dopning i kanal-lagret. Vid stress (VDS = 900 V) med komponenterna i avslaget tillstånd ökade läckströmmen kortvarigt för att sedan minska, troligtvis beroende på att laddningar omfördelas i lagret under kanal-skiktet. Efter stress sågs inte några större förändringar hos RDSon och Vth , men förändringar syntes på läckströmmen: komponenter med initialt låga läckströmmar visade ökning av läckströmmen efter stress, medan komponenter med initialt höga läckströmmar visade en post-stress minskning av läckström. Detta antas bero på den nämnda omfördelningen av laddningar djupare ner i komponenterna. Mätningar av parasitisk kapacitans visade på en ökning av pre-stress in- och ut-kapacitanserna (Ciss, Coss) samt ”gate-drain”-kapacitansen som funktion av pre-stress läckströmmar. Detta kan möjligtvis förklaras av att en högre andel Al inducerar mer laddningar i kanalen, vilket indikerar att högre Al-molfraktion i skiktet under kanal-lagret är orsaken till många av de effekter som setts. Kapacitansförändringar efter stress förklaras troligen av att laddningarna i detta lager återgår. Till sist noteras också att hög temperatur tydligt reducerade den långa tiden som komponenterna behövde för att återhämta sig. Det var också tydligt att mer mätningar är nödvändiga för att ytterligare säkerställa de uppmätta förändringarna, t ex mätningar av G-ω på icke kapslade chips, skulle kunna öka förståelsen för dessa minneseffekter.

This report presents the development, implementation, and testing of a current monitor system that is specifically developed for testing a neuromuscular electrical stimulation system (NMES). The NMES system, developed by KTH and its academic and industrial partners Karolinska institute and Matrix Muscle Support, incorporates advanced features aimed at preventing cardiovascular diseases. The problem statement revolves around the necessity of developing a system capable of detecting any instances of overcurrent or leakage current in the neuromuscular electrical stimulation system. The purpose of this current monitoring system is to offer real-time monitoring of current levels within the electrical stimulation system. The project’s goal is to design and implement a comprehensive software and hardware solution that allows users to simultaneously monitor voltage levels across multiple channels and detect any abnormalities. The project was executed using a top-down approach. Each subtask is processed separately and finally tested to be verified and approved according to the expectations set. Test-driven development (TDD) methodology was employed to ensure the reliability and accuracy of the software and hardware implementation. The project has produced several significant results, the most important of which include the successful implementation of a real-time monitoring system for the multi-channel NMES system. A dedicated circuit board design has been prepared according to the specified requirements described in the report. The software interface has been designed to provide the user with real-time readings of voltage levels as well as visual identification of normal and abnormal values. The measurements carried out during all the tests gave clear answers to the set question, with the exception of some displacement (offset) which can be investigated more closely in future research. Furthermore, the reference images showed that the system was functioning in accordance with its original intended purpose. / Denna rapport presenterar utvecklingen, implementeringen och testningen av ett strömmätningssystem som är speciellt utvecklat för att testa ett neuromuskulärt elektriskt stimuleringssystem (NMES). NMES-systemet, utvecklat av KTH och dess akademiska och industriella partners Karolinska institutet och Matrix Muscle Support, innehåller avancerade funktioner som syftar till att förebygga hjärt-kärlsjukdomar. Problemformuleringen kretsar kring nödvändigheten av att utveckla ett system som kan detektera fall av överström eller läckström i det neuromuskulära elektriska stimuleringssystemet. Syftet med detta strömmätningssystem är att erbjuda realtidsövervakning av strömnivåer inom det elektriska stimuleringssystemet. Projektets mål är att designa och implementera en omfattande mjukvaru- och hårdvarulösning som tillåter användare att samtidigt övervaka spänningsnivåer över flera kanaler och upptäcka eventuella avvikelser. Projektet genomfördes med en top-down-metod. Varje deluppgift bearbetas separat och testas slutligen för att verifieras och godkännas enligt de förväntningar som satts. Testdriven utvecklingsmetod (TDD) användes för att säkerställa tillförlitligheten och noggrannheten hos implementeringen av mjukvara och hårdvara. Projektet har gett flera betydande resultat, av vilka de viktigaste inkluderar framgångsrik implementering av ett realtidsövervakningssystem för flerkanals NMES-systemet. En dedikerad kretskortsdesign har utarbetats enligt de specificerade kraven som beskrivs i rapporten. Mjukvarugränssnittet har utformats för att ge användaren realtidsavläsningar av spänningsnivåer samt visuell identifiering av normala och onormala värden. De mätningar som genomfördes under samtliga tester gav tydliga svar på frågeställningen, med undantag för viss förskjutning (offset) som kan undersökas närmare i framtida forskning. Vidare visade referensbilderna att systemet fungerade i enlighet med det ursprungliga syftet.

Este trabalho apresenta um estudo sobre a corrente de fuga de modo comum em inversores monofásicos sem transformador utilizados para a conexão de sistemas fotovoltaicos (FV) à rede de distribuição de energia elétrica. O estudo se concentra em inversores do tipo fonte de tensão que empregam a topologia em ponte completa. A partir da adequada modelagem do sistema (rede, conversor e módulo fotovoltaico) identifica-se e quantifica-se a contribuição das tensões de modo comum e modo diferencial para a corrente de fuga. Conclui-se que a tensão de modo comum de alta frequência produzida pelo inversor, que depende da estratégia de modulação por largura de pulso (PWM Pulse Width Modulation) empregada, fornece a maior contribuição para produção da corrente de fuga. Esse estudo mostra que os inversores sem transformador, com topologia em ponte completa e modulação que produz tensão de saída com três níveis, necessitam de medidas adicionais para a minimização da corrente fuga quando aplicados em sistemas fotovoltaicos conectados à rede. Algumas soluções propostas na literatura para a minimização da corrente de fuga baseadas em topologias modificadas e filtros de modo comum são listadas e discutidas. Neste trabalho é proposto um filtro integrado de modo comum e modo diferencial com amortecimento passivo de baixas perdas, para minimizar a corrente de fuga produzida por um inversor monofásico sem transformador. Um exemplo de aplicação do filtro proposto é apresentado juntamente com seu procedimento de projeto, resultados de simulação e experimentais que validam a proposta. Além disso, a influência da variação da indutância da rede elétrica e da capacitância parasita do sistema fotovoltaico no comportamento do filtro proposto é analisada. A influência da variação da indutância da rede no comportamento do sistema de controle e o impacto da corrente de modo comum no projeto dos indutores do lado do conversor também são analisados. / This paper presents a study on the common mode leakage current in single-phase transformerless inverters for grid-connected photovoltaic (PV) systems. The study focuses on voltage source inverters (VSI) employing the full-bridge topology. The common mode and differential mode voltages that contribute to the leakage current are identified and quantified from the analysis of the system model (utility grid, converter and PV module). The system model analysis shows that the high frequency common mode voltage produced by the inverter, which depends on the Pulse Width Modulation (PWM) strategy, is the main source contributing to the leakage current. This work shows that transformerless inverters employing the full-bridge topology and a modulation strategy that produces a three-level output voltage require some leakage current minimization strategy when they are employed in grid-connected PV systems. Some solutions proposed in the literature for leakage current minimization based on modified topologies and common mode filters are listed and discussed. In this dissertation an integrated common and differential filter with low loss passive damping is proposed to minimize the leakage current produced by a single-phase transformerless PV inverter. An application example of the proposed filter is presented with design procedure, simulation and experimental results validating the proposal. Additionally, the influence of grid inductance and PV module parasitic capacitance variations on the behavior of the proposed filter is analyzed. The behavior of the control system considering the grid inductance variation and the impact of the common mode current on the converter side inductors design are also analyzed.