Recently, as a promising lighting source, light-emitting diodes (LEDs) have become more and more attractive and have great opportunity to replace traditional lighting sources - incandescent, fluorescent and HID because of the advantages such as high luminous efficacy, long lifetime, quick on/off time, wide color gamut, eco-friendly etc. Based on the research from U.S. Department of Energy, over 30% of total electric consumption in U.S. each year is for lighting, 75% of which are for indoor lighting (including both residential and commercial buildings). In the indoor LED lighting application, to provide multiple current source outputs for multiple LED strings, traditional solutions usually adopt a two-stage structure, which is complicated and cost-ineffective. How to design a simple, low-cost and efficient LED driver with multiple current source outputs is in great demand and really challenging. In this thesis, a single-stage multi-channel constant current (MC3) LED driver structure has been proposed. Multiple transformer structure is utilized to provide multiple current source outputs. The current control scheme is also simple - only one LED string current is sensed and controlled; other strings' currents are cross regulated. Firstly, a PWM half bridge topology is chosen to implement the proposed single-stage MC3 LED driver concept. In order to analyze the current cross regulation, a general model is derived. The circuit has been simulated under various LED load conditions to verify its good current sharing capability. In order to further improve efficiency, simplify the driver's complexity and reduce cost, a LLC resonant topology is also investigated. LLC current gain characteristic has been derived by considering LED's i-v character and a design procedure is developed. A 100 kHz, 200 W, 4-string MC3 LLC LED driver is designed and tested. The experimental results show that the driver can maintain constant current output within the whole input and output variations, achieve good efficiency and realize current sharing under both balanced and unbalanced LED conditions. The dimming function can also be realized through frequency modulation method and burst mode control method. As a conclusion, a single-stage MC3 LED driver concept is proposed and implemented with two topologies. The proposed idea provides a simple, low-cost and efficient solution for indoor LED lighting application with multiple LED string configuration. It also has good current sharing capability and robustness to LED forward voltage variations or short failures. / Master of Science

Notre équipe a précédemment démontré que l'Interleukine (IL)-24 une cytokine de la famille de l'IL-10 a un effet cytostatique voire cytotoxique sur des cellules B normales ou leucémiques mises préalablement en cycle mais non sur des cellules quiescentes. L'IL-24 inhibe également la différenciation plasmocytaire des cellules B humaines du centre germinatif dans un modèle de différentiation in vitro. Nous avons utilisé ce modèle pour analyser pour la première fois le transcriptome de cellules B stimulées ou non par IL-24 au bout de 6 et 36 h. Plusieurs transcrits impliqués dans le métabolisme et la réplication de l'ADN sont inhibés précocement à l'exception d'IGF-1 qui est stimulé. L'IGF1 ayant été décrit comme une molécule de survie des cellules B ou pré-B, nous avons analysé son effet biologique et démontré qu'il a au contraire un rôle proapoptotique à doses physiologiques. En revanche, l'IL-24 induit l'expression plus tardive des gènes de la voie mitochondriale de la mort cellulaire programmée (MCP). Cet effet est également retrouvé dans des LLC « IgVH mutées » ou non mais avec une cinétique distincte des cellules B normales. Au total, dans des cellules activées au préalable, l'IL-24 induit séquentiellement un blocage précoce du cycle cellulaire suivi d'une apoptose. D'autres gènes potentiellement importants dans la synapse immune ainsi que dans la régulation de l'immunité innée sont décrits et suggèrent que l'IL-24 a un rôle immunologique particulier au-delà de son effet cytostatique et potentiellement anti-tumoral / We have previously shown that Interleukin(IL)-24 a class-II cytokine of the IL-10 family has cytostatic and cytotoxic properties on normal and malignant human B-cells previously engaged into the cell cycle, but not on quiescent B-cells. IL-24 also inhibits the differentiation of germinal center B-cells in plasma cells in an in vitro model; the later was used to compare for the first time the transcriptome of B-cells cultured or not with IL-24 for 6 and 36h. Several "early" transcripts involved in DNA metabolism and replication were inhibited whereas that of Igf1 a molecule described as a B-cell growth factor was induced. We show herein that IgF1 has instead a proapoptotic role on B-cells at physiological concentrations. In contrast, several genes of the intrinsic apoptotic pathway were stimulated after 36h. This expression pattern was also found in CLL cells whether they were "IgVH mutated" or "unmutated", albeit with distinct kinetics from normal B-cells. In addition several genes belonging to the immune synapse and innate immunity were regulated by IL-24. These results disclose additional, possibly immunoregulatory properties, for IL-24 than its already described cytostatic and potentially anti-tumoral effects

The thesis is focused on the process of trading in credit derivatives on the global financial markets. The first part deals with the history and the development of credit derivatives from the very beginning to the present and all factors that influenced and affected them during that time. Various derivative instruments are explained, in terms of their purpose, suitability for use and the risks arising from them. Mainy focus of the thesis is put on the selected stock markets (CME Group Inc., Eurex AG, NYSE Liff Holdings LLC). This section begins with their history, then it describes their structure and purpose. It explains stock market membership conditions and settlement of exchange contracts principles. The final part clarifies the role of credit derivatives in the financial crisis and the reasons that led to it. In the final part of the thesis organizations that regulate credit derivatives are described, in addition to regulation methods and aids, specifically in terms of new regulatory measures under Basel III and the organization of ISDA, which are also included. At the very end the possibilities of securitization and credit risk diversification are explained as well as methods of credit instruments valuation, which are demonstrated on an example of Credit Default Swap.

This thesis investigates a novel DC/AC resonant inverter of Induction Heating (IH) system presenting a Multilevel Neutral Point Clamped (MNPCI) topology, as a new part of power supply design. The main function of the prototype is to provide a maximum and steady state power transfer from converter to the resonant load tank, by achieving zero current switching (ZCS) with selecting the best design of load tank topology, and utilizing the advantage aspects of both the Voltage Fed Inverter (VFI) and Current Fed Inverter (CFI) kinds, therefore it can considered as a hybrid-inverter (HVCFI) category . The new design benefits from series resonant inverter design through using two bulk voltage source capacitors to feed a constant voltage delivery to the MNPCI inverter with half the DC rail voltage to decrease the switching losses and mitigate the over voltage surge occurred in inverter switches during operation which may cause damage when dealing with high power systems. Besides, the design profits from the resonant load topology of parallel resonant inverter, through using the LLC resonant load tank. The design gives the advantage of having an output current gain value of about Quality Factor (Q) times the inverter current and absorbs the parasitic components. On the contrary, decreasing inverter current means decreasing the switching frequency and thus, decreasing the switching losses of the system. This aspect increases the output power, which increases the heating efficiency. In order for the proposed system to be more reliable and matches the characteristics of IH process , the prototype is modelled with a variable LLC topology instead of fixed load parameters with achieving soft switching mode of ZCS and zero voltage switching (ZVS) at all load conditions and a tiny phase shift angle between output current and voltage, which might be neglected. To achieve the goal of reducing harmonic distortion, a new harmonic control modulation is introduced, by controlling the ON switching time to obtain minimum Total Harmonic Distortion (THD) content accompanied with optimum power for heating energy.

The world is heading towards an energy crisis and desperate efforts are being made to find an alternative, reliable and clean source of energy. Solar Energy is one of the most clean and reliable source of renewable energy on earth. Conventionally, extraction of solar power for electricity generation was limited to PV farms, however lately Distributed Generation form of Solar Power has emerged in the form of residential and commercial Grid Tied Micro-Inverters. Grid Tied Micro-Inverters are costly when compared to their string type counterparts because one inverter module is required for every single or every two PV panels whereas a string type micro-inverter utilizes a single inverter module over a string of PV panels. Since in micro-inverter every panel has a dedicated inverter module, more power per panel can be extracted by performing optimal maximum power tracking over single panel rather than over an entire string of panels. Power per panel extracted by string inverters may be lower than its maximum value as few of the panels in the string may or may not be shaded and thereby forming the weaker links of the system. In order to justify the higher costs of Micro-Inverters, it is of utmost importance to convert the available power with maximum possible efficiency. Typically, a microinverter consists of two important blocks; a Front End DC-DC Converter and Output DCAC Inverter. This thesis proposes efficiency optimization techniques for both the blocks of the micro-inverter. iv Efficiency Optimization of Front End DC-DC Converter This thesis aims to optimize the efficiency of the front end stage by proposing optimal design procedure for resonant parameters of LLC Topology as a Front End DC-DC Converter for PV Applications. It exploits the I-V characteristics of a solar panel to design the resonant parameters such that resonant LLC topology operates near its resonant frequency operating point which is the highest efficiency operating point of LLC Converter. Efficiency Optimization of Output DC-AC Inverter Due to continuously variable irradiance levels of solar energy, available power for extraction is constantly varying which causes the PV Inverter operates at its peak load capacity for less than 15% of the day time. Every typical power converter suffers through poor light load efficiency performance because of the load independent losses present in a power converter. In order to improve the light load efficiency performance of Three Phase Inverters, this thesis proposes Phase Skipping Control technique for Three Phase Grid Tied Micro-Inverters. The proposed technique is a generic control technique and can be applied to any inverter topology, however, in order to establish the proof of concept this control technique has been implemented on Three Phase Half Bridge PWM Inverter and its analysis is provided. Improving light load efficiency helps to improve the CEC efficiency of the inverter.

The advent of wide band-gap semiconductors in power electronics has led to the scope of efficient power conversion being pushed further than ever before. This development has allowed for systems to operate at higher and higher voltages than previously achieved. One area of consideration during this high voltage transition is the synchronous rectifier, which is traditionally designed as an afterthought. Prior research in synchronous rectifiers have been limited to low voltage, high current converters. There is practically no research in high voltage synchronous rectification. Therefore, this dissertation focuses on discovering the unknown nuances behind high voltage synchronous rectifier design, and ultimately developing a practical, scalable solution. There are three main issues that must be addressed when designing a high voltage synchronous rectifier: (1) high voltage sensing; (2) light load effects; (3) accuracy. The first hurdle to designing a high voltage SR system is the high voltage itself. Traditional methods of synchronous rectification (SR) attempt to directly sense voltage or current, which is not possible with high voltage. Therefore, a solution must be designed to limit the voltage seen by the sensing mechanism without sacrificing accuracy. In this dissertation, a novel blocking solution is proposed, analyzed, and tested to over 1-kV. The solution is practical enough to be implemented on practically any commercial drain-source SR controller. The second hurdle is the light load effect of the SR system on the converter. A large amount of high voltage systems utilize a LLC-based DC transformers (DCX) to provide an efficient means of energy conversion. The LLC-DCX's attractive attributes of soft-switching and high efficiency allure many architects to combine it with an SR system. However, direct implementation of SR on a LLC-DCX will result in a variety of light load oscillation issues, since the rectifier circuitry can excite the resonant tank through a false load transient phenomena. A universal limiting solution is proposed and analyzed, and is validated with a commercial SR controller. The final hurdle is in optimizing the SR system itself. There is an inherent flaw with drain-source sensing, namely parasitic inductance in the drain-source sense loop. This parasitic inductance causes an error in the sensed voltage, resulting in early SR turn-off and increased losses through the parallel diode. The parasitic will always be present in the circuit, and current solutions are too complex to be implemented. Two solutions are proposed depending on the rectifier architecture: (1) multilevel gate driving for single switch rectifiers; (2) sequential parallel switching for parallel switch rectifiers. In summary, this dissertation focuses on developing a practical and reliable high voltage SR solution for LLC-DCX converters. Three main issues are addressed: (1) high voltage sensing; (2) light load effects; (3) accuracy. Novel solutions are proposed for all three issues, and validated with commercial controllers. / Doctor of Philosophy / High voltage power electronics are becoming increasing popular in the electronics industry with the help of wide band-gap semiconductors. While high voltage power electronics research is prevalent, a key component of high voltage power converters, the synchronous rectifier, remains unexplored. Conventional synchronous rectifiers are implemented on high current circuits where diode losses are high. However, high voltage power electronics operate at much lower current levels, necessitating changes in current synchronous rectifier methods. This research aims to identify and tackle issues that will be faced by both systems and IC designers when attempting to implement high voltage synchronous rectifiers on LLC-DCXs. While development takes planes on a LLC-DCX, the research is applicable to most resonant converters and applications utilizing drain-source synchronous rectifier technology. This dissertation focuses primarily on three areas of synchronous rectifier developments: (1) high voltage compatibility; (2) light load effects; (3) accuracy. The first issue opens the gate to high voltage synchronous rectifier research, by allowing high voltage sensing. The second issue explores issues that high voltage synchronous rectifiers can inadvertently influence on the LLC-DCX itself - a light load oscillation issue. The third issue explores novel methods of improving the sensing accuracy to further reduce losses for a single and parallel switch rectifier. In each of these areas, the underlying problem is root-caused, analyzed, and a solution proposed. The overarching goal of this dissertation is to develop a practical, low-cost, universal synchronous rectifier system that can be scaled for commercial use.

Isolated inverter can provide galvanic isolation which is necessary for some applications with safety regulations. Traditionally, a two-stage configuration is widely applied with isolated dc-dc stage and a sinusoidal pulse-width-modulated (SPWM) dc-ac stage. However, this two-stage configuration suffers from more components count, more complex control and tend to have lower efficiency and lower power density. Meanwhile, a large dc bus capacitor is needed to attenuate the double line frequency from SPWM for two-stage configuration. Therefore, the single-stage approach including an isolated dc-rectified sine stage and a line frequency unfolder is preferable. Since the unfolder circuit is at line frequency being almost lossless, the isolated dc-rectified sine stage becomes critical. However, the relevant research for the single-stage isolated inverter is limited. People either utilize PWM based converter as dc-rectified sine stage with duty cycle adjustment or apply SRC or LLC resonant converter for better soft switching characteristics. For PWM based converter, hard switching restricts the overall inverter efficiency, while for SRC/LLC, enough wide voltage gain range and full range ZVS are the major issues. This dissertation aims to provide solutions for a high-efficiency, high-frequency resonant converter based single-stage soft-switching isolated inverter design. The LLC and LCLCL resonant converters are applied as the isolated dc-rectified sine stage with variable frequency modulation (VFM). Therefore, the rectified sine wave generation consists of many dc-dc conversion with different switching frequencies and an efficient dc-rectified sine stage design needs each dc-dc conversion to be with high efficiency. This dissertation will first propose the optimization methods for LLC converter dc-dc conversion. ZVS models are derived to ensure fully ZVS performance for primary side GaN devices. As a large part in loss breakdown, the optimization for transformer is essential. The LLC converter can achieve above 99% efficiency with proposed optimization approach. Moreover, the channel turn-off energy model is presented for a more accurate loss analysis. With all the design and optimization considerations, a MHz LLC converter based isolated inverter is designed and a hybrid modulation method is proposed, which includes full bridge (FB) VFM for output high line region and half bridge (HB) VFM for output low line region. By changing from FB to HB, the output voltage gain is reduced to half to have a wider voltage gain range. However, the total harmonic distortion (THD) of output voltage at light load will be impacted since the voltage gain will be higher with lighter load at the maximum switching frequency. A MHz LCLCL converter based isolated inverter is proposed for a better output voltage THD at light load conditions. The paralleled LC inside the LCLCL resonant tank can naturally create a zero voltage gain point at their resonant frequency, which shows superior performance for rectified sine wave generation. Besides the better THD performance, the LCLCL converter based isolated inverter also features for easier control, better ZVS performance and narrower switching frequency range. Meanwhile, the LCLCL based inverter topology has bi-directional power flow capability as well. With variable frequency modulation for ac-dc, this topology is still a single-stage solution compared to the traditional two-stage solution including PFC + LLC configuration. / Doctor of Philosophy / Inverters can convert dc voltage to ac voltage and typically people use two-stage approach with isolated dc-dc stage and dc-ac stage. However, this two-stage configuration suffers from more components count, more complex control and tend to have lower efficiency and lower power density. Therefore, the single-stage solution with dc-rectified sine wave stage and a line frequency unfolder becomes appealing. The unfolder circuit is to unfold the rectifier sine wave to an ac sine wave at the output. Since the unfolder is at line frequency and can be considered lossless, the key design is for the dc-rectified sine stage. The resonant converter featured for soft switching seems to be a good candidate. However, the inverter needs soft switching for the whole range and an enough wide voltage gain, which makes the design difficult, especially the target is high efficiency for the overall inverter. This dissertation aims to provide solutions for a high-efficiency, high-frequency resonant converter based single-stage soft-switching isolated inverter design. The LLC and LCLCL resonant converters are applied as the isolated dc-rectified sine stage with variable frequency modulation (VFM). Therefore, the rectified sine wave generation consists of many dc-dc conversion with different switching frequencies and an efficient dc-rectified sine stage design needs each dc-dc conversion to be with high efficiency. The design considerations and optimization methods for the LLC dc-dc conversion are firstly investigated. Based on these approaches, a MHz LLC converter based isolated inverter is designed with proposed hybrid modulation method. To further improve the light load performance, a MHz LCLCL converter based isolated inverter topology is proposed. The paralleled LC inside the LCLCL resonant tank can naturally create a zero voltage gain point which shows superior characteristics for rectified sine wave generation. Moreover, the LCLCL resonant converter based topology has bi-directional capability as well so it can work well for ac voltage to dc voltage conversion.

With the development of information technology, power management for telecom and computer applications become a large market for power supply industries. To meet the performance and reliability requirement, distributed power system (DPS) is widely adopted for telecom and computer systems, because of its modularity, maintainability and high reliability. Due to limited space and increasing power consumption, power supplies for telecom and server systems are required to deliver more power with smaller volume. As the key component of DPS system, front-end AC/DC converter is under the pressure of continuously increasing power density. For conventional industry practices, some limitations prevents front-end converter meeting the power density requirement. In this dissertation, different techniques have been investigated to improve power density of front-end AC/DC converters. For PFC stage, at low switching frequency, PFC inductor size is large and limits the power density. Although increasing switching frequency can dramatically reduce PFC inductor size, EMI filter size might be larger at higher switching frequency because of the change of noise spectrum. Since the relationship between EMI filter size and PFC switching frequency is unclear for industry, PFC circuits always operate with switching frequency lower than 150 kHz. Based on the EMI filter design method, together with a simple EMI noise prediction model, relationship between EMI filter corner frequency and PFC switching frequency was revealed. The analysis shows that switching frequency of PFC circuit should be higher than 400 kHz, so that both PFC inductor and EMI filter size can be reduced. Although theoretical analysis and experimental results verify the benefits of high switching frequency PFC, it is essential to find a suitable topology that allows high switching frequency operation while maintains high efficiency. Three PFC topologies, single switch PFC, three-level PFC with range switch and dual Boost PFC, were evaluated with analysis and experiments. By using advanced semiconductor devices, together with proposed control methods, these topologies could achieve high efficiency at high switching frequency. Thus, the benefits of high frequency PFC can be realized. In front-end converter, large holdup time capacitor size is another barrier for power density improvement. To meet the holdup time requirement, bulky holdup time capacitor is normally used to provide energy during holdup time. Holdup time capacitor requirement can be reduced by using wider input voltage range DC/DC converte. Because LLC resonant converter can realized with input voltage range without sacrificing its normal operation efficiency, it becomes an attractive solution for DC/DC stage of front-end converters. Moreover, its small switching loss allows it operating at MHz switching frequency and achieves smaller passive component size. However, lack of design methodology makes the topology difficult to be implemented. An optimal design methodology for LLC resonant converter has been developed based on the analysis on the circuit during normal operation condition and holdup time. The design method is verified by a 1 MHz switching frequency LLC resonant converter with 76W/in3 power density. When front-end converter operates at high switching frequency, negative effects of circuit parasitics become more pronounced. By integrating active devices together with their gate drivers, Active Integrated power electronics module (IPEM) can largely reduce circuit parasitics. Therefore, switching loss and voltage stress on switching devices can be reduced. Moreover, IPEM concept can be extended into passive integration and EMI filter integration By using this power integration technology, power density and circuit performance of front-end converter can be improved, which is verified by theoretical analysis and experimental results. / Ph. D.

自Nelson和Plosser (1982)後，研究經濟資料是否具有單位根現象，已成為近二十年來熱門且重要的課題。因 為資料性質的不同(恆定或非恆定)，對實證計量模型的設定、統計推論以及原理論的發展有深遠的影響。與傳 統探討單一時間數列之單位根的論文不同的是，本篇論文將橫斷面的資料擴大，探討混合型資料的單位根現象 ( Panel Unit Root )。就此課題，文獻上已有兩個不同的檢定方法: Levin、Lin和Chu (1997)的LLC檢定法以及Im、 Pesaran和Shin (1995)的IPS檢定法。 我們的研究，有別於以上兩者，是從「概似比」的角度(likelihood ratio) 和應用檢定共積關係的Johansen (1988)「Trace檢定」，建構新的單位根檢定統計量。首先於文中推導出，「Trace檢定」可用於檢測單一時間數 列的單位根現象。進而，再將橫斷面資料擴大，採用mean group方法，加總平均每個橫斷面時間數列的「Trace 檢定」統計量，形成混合型資料之單位根檢定統計量 。根據中央極限定理，標準化後的 檢定統計量，極限上 收斂至標準常態分配。此外，我們也推導得出 檢定統計量與傳統ADF、LLC以及IPS檢定統計量極限上的關係。 最後，我們以「蒙地卡羅」模擬方法，分析小樣本下「型一誤差」與「檢定力」的表現。發現新的混合型資 料之單位根檢定統計量表現優良，近似於標準常態分配。故在做混合型資料的單位根分析時，採用 檢定統計 量，可得到較精確的推論。

This master thesis presents the development of a 100 W LED driver, suitable for outdoor and street lighting. In order to match the driver and LED features, special functionalities are added to the electronic system. To obtain a long lifetime, electrolytic capacitor are exchanged by film capacitor, with longer useful lifetime. However, this practice outcome in higher bus voltage ripple, which have to be compensated in the LED current control stage, named as power control stage. To achieve special functionalities, the proposed driver is designed to operate with universal input voltage and dimming capability, being the entire driver control implement in a digital way, increasing significantly the LED driver flexibility. After the literature review, which aimed to evaluate the characteristics of the LED driver topology structure, the two independent stage topology is selected. The buckboost converter operating in discontinuous conduction mode is employed on the power factor correction stage. The power control stage is composed by the DC/DC LLC resonant converter. Once the LED driver topology is defined, each converter is designed, following by the small signal modeling and the control system design. Experimental results of the driver operating with a reduced bus voltage capacitance (25 μF), are presented for a universal input voltage (85 – 265 VRMS) and different dimming levels (100% − 30%). A high power factor (> 0,94) and a medium to high efficiency (> 82%) is noticed in whole operation points, as well as, a reduced flicker (< 10%), being in accordance with the recent released IEEE Std 1789-2015 and IEC61000-3-2 Class C. / Este trabalho apresenta o desenvolvimento de um driver para o acionamento de um módulo de LEDs de 100 W, destinado a iluminação de exteriores ou iluminação pública. De forma a compatibilizar as características do LED com o driver, diferentes funcionalidades e condições de operação são adicionadas ao sistema eletrônico desenvolvido. Para alcançar longa vida útil, o driver desenvolvido substituiu os capacitores eletrolíticos por capacitores de filme. No entanto, essa prática resulta em maiores ondulações da tensão de barramento, as quais são compensadas pelo estágio de controle da corrente dos LEDs. De modo a aumentar as funcionalidades do driver, o mesmo opera com tensão de entrada universal e controle da intensidade luminosa, sendo o sistema de controle do driver implementado de forma digital, aumentando consideravelmente sua flexibilidade. Após revisão da literatura, a qual objetivou avaliar as características das estruturas e topologias empregadas em drivers para LEDs, seleciona-se a estrutura de dois estágios independentes. O conversor buck-boost operando no modo de condução descontínuo de corrente é empregado no estágio de correção do fator de potência. Para o estágio de controle da corrente dos LEDs, utiliza-se o conversor CC/CC meia ponte ressonante LLC. Definida a estrutura topológica, bem como os conversores utilizados, o projeto dos elementos é desenvolvido, seguido da modelagem dinâmica e do projeto do sistema de controle de cada estágio. Resultados experimentais do driver com reduzida capacitância de barramento (25 μF) mostram a sua operação com tensão de entrada universal (85 – 265 VRMS) e controle de intensidade luminosa (100% − 30%). Verificou-se um alto fator de potência (> 0,94) em toda a faixa de operação, rendimento média-alto (> 82%), bem como reduzida modulação de intensidade luminosa (< 10%), estando em conformidade com a IEEE Std 1789-2015 e a IEC61000-3-2 Classe C.