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<p>Ovaj rad ima za cilj da ispita prisutnost i značaj videoigara u<br />kontekstu scenske arhitekture i da ukaže na rastući značaj jedne mlade<br />discipline, a to je kreiranje prostora u videoigrama. Teorijski i<br />naučno-istraživački deo rada ukazuju, svaki na svoj način, na već<br />postojeće i nove moguće oblike primene koncepata prostora i vizuelnih<br />percepcija iz oblasti arhitekture i urbanizma u oblasti kreiranja<br />videoigara. Od Vitruvijevog trojnog načela, preko trojnog načela<br />ključnih odrednica videoigara i problematike prostornih situacija,<br />do uloge i položaja korisnika/igrača u kontekstu sadejstva sa datim<br />prostorom, u radu je predočen niz načina na koje elementi<br />arhitektonskog teorijskog nasleđa, pre svega elementi i principi<br />scenske arhitekture, mogu biti implementirani u proces kreiranja<br />prostora u videoigrama.</p> / <p>The goal of this thesis is to examine the presence and significance of<br />videogames in the context of scene architecture and to indicate a growing<br />importance of a young field &ndash; level design in videogames. Theoretical and<br />scientific research portions of the paper point, each in their own manner, to<br />existing as well as new modes of applying concepts of space and visual<br />perception from the domain of architecture and urbanism in the field of<br />videogame design. This paper offers a significant number of methods of<br />implementing aspects of architectural theory heritage, primarily elements and<br />principles of scene architecture, in the process of designing space in<br />videogames - starting with Vitruvius&rsquo;s triple principle, followed by the triple<br />principle of key features of videogames and the issue of spatial situations, to<br />the role and position of user/player in the context of cooperation with a given<br />space.</p>

Planners are well developed tools in computer science, but their role is rather limited in games. We decided to test the possibilities of writing such a game around them. Proving that freely available, general purpose planning systems are worthy alternatives to custom made solutions could open a new path to small developers and popularize a new kind of gameplay powered by these tools. We attempted to exploit planners in two roles, in the development, to partially automate the level design process; and in the gameplay as a decision making tool for the acting agents. Our program is a puzzle game, more precisely an anticipation game, where the player has to foresee the future actions of the acting agents, then discover the pitfalls where they are heading. Using this knowledge he can modify their environment and force them to a desired outcome. A part of our program is a generator of such game challenges. We came to a conclusion that within some limitations planners are capable of creating believable agent behavior and while not all decisions can be handed over to the planning systems, they can lighten the task of the level designer.

The purpose of this thesis is to examine how compositional techniques developed for fine art may be applied to 3-dimensional level design. It uses game design theory and best practices as a starting point and then investigates how graphic theory can be applied to further them by creating natural graphic focal points in a level, providing a set of tools the designer might use to graphically communicate with the player. The thesis investigates four main techniques used to achieve graphic control: Managing hues and values. Managing shapes. Using linear and atmospheric perspective. Managing levels of detail. Each technique is linked to compositional theory through historical paintings which feature the techniques in question. Examples are then provided from contemporary games that testify the validity of using the technique in level design. In some cases altered scenes are also provided; over paints done in Adobe Photoshop exemplify how a technique may be used to change a scene’s meaning and convey other messages to the player. The conclusions and analysis testify to the value of incorporating compositional theory into level design and suggest further areas of research along the same line.

The United States Navy is committed to developing technology for an All-Electric Ship (AES) that promises to improve the affordability and capability of its next-generation warships. With the addition of power-intensive 21st century electrical systems, future thermal loads are projected to exceed current heat removal capacity. Furthermore, rising fuel costs necessitate a careful approach to total-ship energy management. Accordingly, the aim of this research is to develop computer tools for early-stage design of shipboard energy distribution systems. A system-level model is developed that enables ship designers to assess the effects of thermal and electrical system configurations on fuel efficiency and survivability. System-level optimization and design exploration, based on these energy system models, is challenging because the models are sometimes computationally expensive and characterized by discrete design variables and discontinuous responses. To address this challenge, a classifier-guided sampling (CGS) method is developed that uses a Bayesian classifier to pursue solutions with desirable performance characteristics. The CGS method is tested on a set of example problems and applied to the AES energy system model. Results show that the CGS method significantly improves the rate of convergence towards known global optima, on average, when compared to genetic algorithms. / text

The current trend in embedded systems design is to move the initial design and exploration phase to a higher level of abstraction, in order to tackle the rapidly increasing complexity of embedded systems. One approach of abstracting software development from the low level platform details is host- compiled simulation. Characteristics of the target platform are represented in a host-compiled simulation model by annotating the high level source code. Compiler optimizations make accurate annotation of the code a challenging task. In this thesis, we describe an approach to enable correct back-annotation of C code at the basic block level, while taking compiler optimizations into account. / text

Denna studie undersöker olika designval inom datorspel för att skapa intressanta och varierade nivåer som kan tilltala både erfarna spelare och nybörjare inom en av de populäraste fritidsaktiviterna i världen. Att designa en nivå i ett spel är en tidskrävande process, och ett sätt att korta ner på detta arbete är att låta en dator skapa nivåer efter specifika instruktioner, genom en process som kallas för procedurell generering. Målet med denna studie är att ta reda på vilka designval som behöver tas i åtanke för att skapa program för att procedurellt generera nivåer i spel som är anpassade efter en specifik målgrupp. Studiens forskningsfråga lyder: Vilka element krävs i ett 2D-plattformsspel för att spelare skall tycka om spelet? Samt vilka undersökta PCG-algoritmer och parameterinställningar lämpar sig för att skapa ett spel som uppfyller dessa önskemål? För att göra detta utvecklades ett datorspel som använde sig av olika former av procedurell generering. Respondenter från olika målgrupper utformade efter deras spelvanor intervjuades för att ta reda på vilka aspekter personer från varje grupp letade efter i ett datorspel, och det egenutvecklade spelet utformades efter respondenternas svar. Efter detta så fick ett större antal informanter testa spelet och svara på enkätfrågor som sedan sammanställdes och analyserades för att ta reda på vilka aspekter av spelets genererade nivåer som informanterna från varje målgrupp tyckte att datorn hade lyckats med. En del av de resultat vi fått från studien var bland annat att folk som spelar ofta blir mer motiverade av ett poängsystem än folk som spelar mer sällan, samt att alla målgrupper tyckte om en stor variation mellan nivåerna. / This study examines different design choices within computer games to create interesting and varied levels that can appeal to both seasoned gamers and newcomers in one of the most popular hobbies in the world. Designing a level is a time-consuming process, and a way to shorten this work is to let a computer create the levels based on specific instructions, through a process called procedural generation. The goal of this study is to find out what design choices that needs to be taken into account in order to create programs to procedurally generate levels in games that are tailored for a specific target audience. The research question of this study is: Which elements are required in a 2D-platforming game in order for players to enjoy it? And which of the examined PCG-algorithms and parameter settings are suitable for creating a game that fulfils these requirements? In order to do this, a computer game was developed which used various forms of procedural generation. Respondents from target audiences based on their gaming habits were interviewed in order to find out what aspects people from each group looked for in a video game, and the in-house developed computer game was designed based on the respondents’ answers. After this a larger number of people tested the game and answered a survey, which was later compiled and analysed to find out which aspects of the games generated levels that the players from each target audience felt that the computer had been successful in. A part of the results that we found in this study are among other thing that people who play games more often are more motivated by a score system than other players who play less. And that all target audiences prefer varied level design.

Les nouveaux besoins en communications sans fil pussent le développement de systèmes de transmission RF en termes the reconfigurabilité, multistandard et à basse consommation. Ces travaux de thèse font l’objet de la proposition d’une nouvelle architecture de réception capable d’adresser ces aspects dans le contexte des réseaux WPAN. La technique de sous échantillonnage (BPS-Bandpass Sampling) est appliquée et permet d’exploiter et certain nombre d’avantages liées au traitement du signal à Temps Discret (DT-Discrete Time signal processing), notamment le filtrage et la décimation. Si comparées à la Radio Logicielle, ces techniques permettent de relâcher les contraintes liées aux ADCs en maintenant des caractéristiques multistandard et de reconfigurabilité. Un simulateur dans le domaine fréquentiel large bande a été développé sous MATLAB pour répondre à des limitations au niveau système comme par exemple le repliement spectral et le produit gain bande. En addition avec une nouvelle méthode de conception système, cet outil permet de séparer les différentes contraintes des blocs pour la définition d’un plan de fréquence et the filtrage optimaux. La séparation des différentes contributions dans la dégradation du SNDR (notamment le bruit thermique, bruit de phase, non linéarité et le repliement), permet de relâcher de spécifications critiques liées à la consommation de puissance. L’architecture à sous échantillonnage proposée dans la thèse est résultat d’une comparaison quantitative des différentes architectures à sous échantillonnage, tout en appliquant la méthode et l’outil de conception système développés. Des aspects comme l’optimisation du filtrage entre les techniques à temps continu et temps discret et le plan de fréquence associé, permettent de trouve l’architecture qui représente le meilleur compromis entre la consommation électrique et l’agilité, dans le contexte voulu. Le bloc de filtrage à temps discret est identifié comme étant critique, et une étude sur les limitations d’implémentation circuit est menée. Des effets come les capacités parasites, l’imparité entre les capacités, le bruit du commutateur, la non linéarité, le gain finit de Ampli OP, sont évalués à travers d’une simulation comportementale en VHDL-AMS. On observe la robustesse des circuits orientés temps discret par rapport les contraintes des nouvelles technologies intégrés. Finalement, le système est spécifié en termes de bruit de phase, qui peuvent représenter jusqu’à 30% de la consommation en puissance. Dans ce but, une nouvelle méthode numérique est proposée pour être capable d’évaluer le rapport signal sur distorsion due au jitter SDjR dans le processus de sous échantillonnage. En plus, une conclusion non intuitive est survenue de cette étude, où on que réduire la fréquence d’échantillonnage n’augmente pas les contraintes en termes de jitter pour le système. L’architecture proposée issue de cette étude est sujet d’un développement circuit pour la validation du concept. / New needs on wireless communications pushes the development in terms reconfigurable, multistandards and low power radio systems. The objective of this work is to propose and design new receiver architecture capable of addressing these aspects in the context of the WPAN networks. The technique of Bandpass Sampling (BPS) is applied and permits to exploit a certain number of advantages linked to the discrete time (DT) signal processing, notably filtering and decimation. Compared to the Software-defined Radio (SDR), these techniques permit to relax the ADC constraints while keeping the multi standard and reconfigurable features. A wide band system level simulation tool is developed using MATLAB platform to overcome system level limitations such spectral aliasing and gain bandwidth product. In addition to a new system design method, the tool helps separating the blocks constraints and defining the optimum frequency plan and filtering. Separating the different contributions on the SNDR degradation (noise, phase noise, non linearity, and aliasing), critical specifications for power consumption can be relaxed. The proposed BPS architecture on the thesis is a result of a quantitative comparison of different BPS architectures, applying the system design method and tool. Aspects such filtering optimization between continuous and discrete time filtering and the associated frequency plan permitted to find the architecture which represents the best trade-off between power consumption and agility on the aimed context. The DT filtering block is therefore identified as critical block, which a study on the circuit implementation limitations is carried out. Effects such parasitic capacitances and capacitance mismatch, switch noise, non linear distortion, finite gain OTA, are evaluated through VHDL-AMS modelling. It is observed the robustness of discrete time oriented circuits. Finally, phase noise specifications are given considering that frequency synthesis circuits may represent up to 30% of the power consumption. For that goal, a new numerical method is proposed, capable of evaluating the signal to jitter distortion ratio SDjR on the BPS process. Moreover, a non intuitive conclusion is given, where reducing the sampling frequency does not increase the constraints in terms of jitter. The proposed architecture issue from this study is in stage of circuit level design in the project team of LETI for final proof of concept.

Les applications de calcul haute-performance (HPC) nécessitent des capacités de calcul conséquentes, qui sont généralement atteintes à l'aide de fermes de serveurs au détriment de la consommation énergétique d'une telle solution. L'accélération d'applications sur des plateformes hétérogènes, comme par exemple des FPGA ou des GPU, permet de réduire la consommation énergétique et correspond donc à un compromis architectural plus séduisant. Elle s'accompagne cependant d'un changement de paradigme de programmation et les plateformes hétérogènes sont plus complexes à prendre en main pour des experts logiciels. C'est particulièrement le cas des développeurs de produits financiers en finance quantitative. De plus, les applications financières évoluent continuellement pour s'adapter aux demandes législatives et concurrentielles du domaine, ce qui renforce les contraintes de programmabilité de solutions d'accélérations. Dans ce contexte, l'utilisation de flots haut-niveaux tels que la synthèse haut-niveau (HLS) pour programmer des accélérateurs FPGA n'est pas suffisante. Une approche spécifique au domaine peut fournir une réponse à la demande en performance, sans que la programmabilité d'applications accélérées ne soit compromise.Nous proposons dans cette thèse une approche de conception haut-niveau reposant sur le standard de programmation hétérogène OpenCL. Cette approche repose notamment sur la nouvelle implémentation d'OpenCL pour FPGA introduite récemment par Altera. Quatre contributions principales sont apportées : (1) une étude initiale d'intégration de c'urs de calculs matériels à une librairie logicielle de calcul financier (QuantLib), (2) une exploration d'architectures et de leur performances respectives, ainsi que la conception d'une architecture dédiée pour l'évaluation d'option américaine et l'évaluation de volatilité implicite à partir d'un flot haut-niveau de conception, (3) la caractérisation détaillée d'une plateforme Altera OpenCL, des opérateurs élémentaires, des surcouches de contrôle et des liens de communication qui la compose, (4) une proposition d'un flot de compilation spécifique au domaine financier, reposant sur cette dernière caractérisation, ainsi que sur une description des applications financières considérées, à savoir l'évaluation d'options. / The need for resources in High Performance Computing (HPC) is generally met by scaling up server farms, to the detriment of the energy consumption of such a solution. Accelerating HPC application on heterogeneous platforms, such as FPGAs or GPUs, offers a better architectural compromise as they can reduce the energy consumption of a deployed system. Therefore, a change of programming paradigm is needed to support this heterogeneous acceleration, which trickles down to an increased level of programming complexity tackled by software experts. This is most notably the case for developers in quantitative finance. Applications in this field are constantly evolving and increasing in complexity to stay competitive and comply with legislative changes. This puts even more pressure on the programmability of acceleration solutions. In this context, the use of high-level development and design flows, such as High-Level Synthesis (HLS) for programming FPGAs, is not enough. A domain-specific approach can help to reach performance requirements, without impairing the programmability of accelerated applications.We propose in this thesis a high-level design approach that relies on OpenCL, as a heterogeneous programming standard. More precisely, a recent implementation of OpenCL for Altera FPGA is used. In this context, four main contributions are proposed in this thesis: (1) an initial study of the integration of hardware computing cores to a software library for quantitative finance (QuantLib), (2) an exploration of different architectures and their respective performances, as well as the design of a dedicated architecture for the pricing of American options and their implied volatility, based on a high-level design flow, (3) a detailed characterization of an Altera OpenCL platform, from elemental operators, memory accesses, control overlays, and up to the communication links it is made of, (4) a proposed compilation flow that is specific to the quantitative finance domain, and relying on the aforementioned characterization and on the description of the considered financial applications (option pricing).

Ce manuscrit présente une méthode de conception au niveau système reposant sur la programmation fonctionnelle typée et visant à atténuer certains des problèmes complexifiant le développement des systèmes numériques modernes, tels que leurs tailles importantes ou la grande variété des blocs les constituant. Nous proposons un ensemble de mécanismes permettant de mélanger au sein d'un même design plusieurs formalismes de description distincts («modèles de calcul») se situant potentiellement à des niveaux d'abstraction différents. De plus, nous offrons au concepteur la possibilité d'expliciter directement les paramètres explorables de chaque sous-partie du design, puis d'en déterminer des valeurs acceptables via une étape d'exploration partiellement ou totalement automatisée réalisée à l'échelle du système. Les gains qu'apportent ces stratégies nouvelles sont illustrés sur plusieurs exemples. / This work presents a novel system-level design method based on typed functional programming and aiming at mitigating some of the issues making the development of modern digital systems complex, such as their increasing sizes and the variety of their subcomponents. We propose a range of mechanisms allowing to mix within a single design several description formalisms (``models of computation''), possibly at different abstraction levels. Moreover, the designer is provided with means to directly express the explorable parameters of each part of their design, and to find acceptable values for them through a partially or totally automatic system-wide architectural exploration step. The advantages brought by those new strategies are illustrated on several examples.