This thesis focuses on the characterization and optimization of microwave power transistors using a commercial on-wafer harmonic load pull system. Specific attention is paid to the output tuning of the second harmonic impedance presented to the device. The ability to quantify the level of accuracy in a load pull system is explored by using various calibration validation methods, including a method called Delta-Gt. In this work experiments and simulation comparisons are described for three different device technologies, namely GaAs pHEMT, GaAs HJFET and InGaP HBT. Externally supplied non-linear models were used for the simulations and these were exercised and compared against 2.45 GHz fundamental frequency measurements made as part of this work to first validate the models against IV, S-Parameter and fundamental load-pull data and finally to explore performance variations under 2nd harmonic impedance tuning. The measured harmonic load-pull data pointed to different guidance on how one would match the 2nd harmonic for best performance. With regard to the model validation/assessment work it was found that only in the case of the pHEMT did the available non-linear model provide a good fit to all the different types of measurement data, including 2nd harmonic tuning data. This model was then used to show that even though the 2nd harmonic tuning measurement had a limited maximum reflection coefficient of about 0.8. Simulated results showed that the worst case linearity condition occurred for the same reflection angle as that measured, but that the variation between worst-case and best case linearity under 2nd harmonic tuning grows considerably larger as the magnitude of the 2nd harmonic reflection coefficient approaches 1. A key aspect of the methodology presented in this work is that once a non-linear model is proved to be valid for harmonic tuning conditions it can be used to explore harmonic tuning-related design trade-offs under a much wider range of frequency and tuning conditions than can be practically explored with measurements alone.

De manière classique, une caractérisation large signal des amplificateurs de puissance s'effectue en présence d'un signal sinusoïdal CW dans le but de fournir aux concepteurs les informations nécessaires permettant un compromis entre puissance de sortie et rendement en puissance ajoutée. Cependant, Dans les systèmes de communications modernes, les amplificateurs de puissance sont soumis à des signaux de plus en plus complexes (modulations numériques) pour lesquels la linéarité est un critère capital supplémentaire pour les performances globales de ces systèmes. Il est donc indispensable de disposer d'outils de caractérisation fonctionnelle permettant de mesurer l'ensemble de ces critères en présence de ces signaux complexes afin de rendre compte au mieux du comportement du dispositif sous test en le plaçant dans ses conditions réelles de fonctionnement. Ce mémoire présente l'étude et la mise en oeuvre d'un banc de caractérisation fonctionnelle de type "load-pull" pour la mesure de l'ensemble des critères de puissance, rendement et linéarité en présence de tous types de signaux (CW, CW-pulsés, GMSK, QPSK, QAM, etc.). L'ENST dispose d'un banc de mesure "source-pull" et "load-pull" multi-harmonique capable d'optimiser la puissance de sortie et le rendement en puissance ajoutée en mode CW. Ce banc est constitué de réflectomètres six-portes, pour la mesure des impédances et des puissances. Afin de permettre l'utilisation de signaux modulés nous avons implémenté des détecteurs de puissance rapides bas coût à base de diodes Schottky non polarisées pour la détection de puissance au niveau des jonctions six-portes. Pour l'optimisation de la linéarité en plus, nous avons ajouté des modules de contrôle des impédances basses fréquences en entrée et en sortie du composant à tester. Un transistor de puissance MESFET a été testé à la fréquence 1.575 GHz en présence d'un signal modulé QPSK de largeur 1.25 MHz et d'un signal bi-porteuses séparées de 800 kHz pour une polarisation de type A et AB. L'ensemble des mesures effectuées permet d'aboutir aux trois principales conclusions montionnées ci-dessous. Premièrement, les contours "load-pull" d'iso-puissances, d'iso-rendement, d'iso-ACPR et d'iso-produits d'intermodulation d'ordre 3 et 5 montrent que les conditions optimales de puissance, de rendement et de linéarité sont différentes d'où la nécessité de trouver des compromis entre les différents critères. D'autre part, ces résultats montrent qu'il existe une forte corrélation entre l'ACPR et le produit d'intermodulation d'ordre 3 en classe A mais pas en classe AB. De toute façon, quel que soit le degré de corrélation, il apparaît difficile de prédire l'ACPR à partir de la connaissance des produits d'intermodulation. Deuxièmement, l'effet des impédances de source BF n'est notable qu'en classe AB dans la zone de saturation. Cet effet se fait sentir uniquement sur la linéarité (variation de 5 dB pour l'ACPR). Finalement, l'effet des impédances de charge BF apparaît quelle que soit la classe de fonctionnement avec évidemment un effet très prononcé pour les classes fortement non-linéaire comme la classe AB pour laquelle on a observé des variations de 5 à 20 dB pour l'ACPR sur toute la dynamique de mesure. Notons que l'impédance optimale n'est pas obligatoirement un court-circuit, et que cette impédance optimale n'est pas toujours l'impédance minimisant la dissymétrie. Par ailleurs, ces impédances ont également une grande influence sur le rendement (variation observée de 10 points) et sur la puissance de sortie (variation de 1 dB).

Characterization and modeling of devices at high drive levels often requires specialized equipment and measurement techniques. Many large-signal devices will never have traditional nonlinear models because model development is expensive and time-consuming. Due to the complexity of the device or the size of the application market, nonlinear modeling efforts may not be cost effective. Scattering parameters, widely used for small-signal passive and active device characterization, have received only cursory consideration for large-signal nonlinear device characterization due to technical and theoretical issues. We review the theory of S-parameters, active device characterization, and previous efforts to use S-parameters with large-signal nonlinear devices. A robust, calibrated vector-measurement system is used to obtain device scattering parameters as a function of drive level. The unique measurement system architecture allows meaningful scattering parameter measurements of large-signal nonlinear devices, overcoming limitations reported by previous researchers. A three-port S-parameter device model, with a nonlinear reflection coefficient terminating the third port, can be extracted from scattering parameters measured as a function of drive level. This three-port model provides excellent agreement with device measurements across a wide range of drive conditions. The model is used to simulate load-pull data for various drive levels which are compared to measured data. / Master of Science

This diploma thesis is focused on design of high frequency power amplifiers in UHF band, specifically at 435 MHz. Amplifiers are designed in different classes of operation. The thesis deals with the comparison of main parameters in each class of operation, the most important parameter is effeciency. The amplifying part is unipolar transistor which is working in Single-stage mode. The results were simulated in Advanced Design Systems Software.

L’évolution des technologies silicium rend aujourd’hui possible le développement de nombreuses applications dans les domaines millimétriques tels que pour les systèmes de communication à très haut débit. Cette évolution se caractérise par une croissance des performances en fréquence des transistors disponibles dans ces technologies et nécessite la mise en place d’outils de mesure performants pour valider la modélisation et l’optimisation technologique de ces dispositifs. La caractérisation load-pull est une méthode incontournable pour modéliser le comportement en fort signal des transistors. En bande G [140-220 GHz], l’environnement de mesure classiquement disponible n’a plus les performances requises pour ce type de caractérisation compte tenu des pertes dans les accès au dispositif sous test. Ce travail de thèse a pour objectif de lever ce verrou en proposant de réaliser, en technologie BiCMOS 55 nm de STMicroelectronics, un banc load-pull entièrement intégré sur silicium afin d’être au plus près du dispositif à caractériser. Le mémoire est articulé autour de quatre chapitres. Le premier chapitre présente l’état de l’art de l’instrumentation actuellement disponible pour la caractérisation en puissance aux fréquences millimétriques et leurs limitations. Le second chapitre détaille la conception et la caractérisation des blocs constituant le banc intégré : le tuner et la source MMW de puissance. Le troisième chapitre décrit la réalisation et les performances du détecteur de puissance. Enfin, le quatrième chapitre présente le banc complet et son application à la caractérisation en bande G d’un dispositif bipolaire disponible dans la technologie BiCMOS 55 nm. / The evolution of silicon technologies now makes possible the development of many applications in the millimeter areas such as high speed communication systems. The evolution of these silicon technologies is characterized by the increase of the transistor performances with the frequency that requires the development of efficient radiofrequency measurement tools for accurate modeling of active components or the optimization of integrated circuits. In this framework, the load-pull characterization is an essential method to model the behavior of transistors in nonlinear region. In the G Band, the classical measurement environment typically available has not the required performance for this kind of characterization due to the losses in the accesses to the device under test. The aim of this thesis is to lift this lock by offering, in the STMicroelectronics BiCMOS 55 nm technology, a fully integrated load-pull characterization bench on silicon in order to be as close as possible to the device to characterize. The thesis manuscript is divided into four chapters. The first chapter presents the state of the art of the currently available instrumentation for power characterization at millimeter wave frequencies band and their limitations, which leads to the G band characterization bench specifications. The second chapter details the design and characterization of the mains blocks constituting the integrated bench: the tuner and the mmw power source. The third chapter present the design and characterization of the power detector. Finally, the fourth chapter presents the complete bench and its application with the G band load-pull characterization of a transistor bipolar device.

In mobile communication new applications like wireless internet and mobile video have increased the demand of data-rates. Therefore, new more wideband systems are being implemented. Power amplifiers in the base-stations that simultaneously handle these wideband signals for many terminals (handhelds) need to be highly linear with a considerable band-width. In the past decade LDMOS has been the dominating technology for use in these RF-power amplifiers. In this work LDMOS transistors possible to fabricate in a normal CMOS process have been optimized and analyzed for RF-power applications. Their non-linear behavior has been explored using load-pull measurements. The mechanisms of the non-linear input capacitance have been analyzed using 2D TCAD simulations. The investigation shows that the input capacitance is a large contributor to phase distortion in the transistor. Computational load-pull TCAD methods have been developed for analysis of RF-power devices in high-efficiency operation. Methods have been developed for class-F with harmonic loading and for bias-modulation. Load-pull measurements with drain-bias modulation in a novel measurement setup have also been conducted. The investigation shows that the combination of computational load-pull of physical transistor structures and direct measurement evaluation with modified load-pull is a viable alternative for future design of RF-power devices. Simulations and measurements on the designed LDMOS shows a 10 to 15 % increase in drain efficiency in mid-power range both in simulations and measurements. The computational load-pull method has also been used to investigate the power capability of LDMOS transistors on SOI. This study indicates that either a low-resistivity or high-resistivity substrate should be used in manufacturing of RF-power LDMOS transistors on SOI to achieve optimum efficiency. Based on a proper substrate selection these devices exhibit a 10 % higher drain-efficiency mainly due to lower dissipated power in the devices.

The emergence of new communication standards has put a key challenge for semiconductor industry to develop RF devices that can handle high power and high data rates simultaneously. The RF devices play a key role in the design of power amplifiers (PAs), which is considered as a heart of base-station. From economical point of view, a single wideband RF power module is more desirable rather than multiple narrowband PAs especially for multi-band and multi-mode operation. Therefore, device modeling has now become much more crucial for such applications. In order to reduce the device design cycle time, the researchers also heavily rely on computer aided design (CAD) tools. With improvement in CAD technology the model extraction has become more accurate and device physical structure optimization can be carried out with less number of iterations. LDMOS devices have been dominating in the communication field since last decade and are still widely used for PA design and development. This thesis deals with the optimization of RFLDMOS transistor and its evaluation in different PA classes, such as linear, switching, wideband and multi-band applications. For accurate evaluation of RF-LDMOS transistor parameters, some techniques are also developed in technology CAD (TCAD) using large signal time domain computational load-pull (CLP) methods. Initially the RF-LDMOS is studied in TCAD for the improved RF performance. The physical intrinsic structure of RF-LDMOS is provided by Infenion Technologies AG. A reduced surface field (RESURF) of low-doped drain (LDD) region is considered in detail because it plays an important role in RF-LDMOS devices to obtain high breakdown voltage (BVDS). But on the other hand, it also reduces the RF performance due to high on-resistance (Ron). The excess interface state charges at the RESURF region are introduced to reduce the Ron, which not only increases the dc drain current, but also improve the RF performance in terms of power, gain and efficiency. The important achievement is the enhancement in operating frequency up to 4 GHz. In LDD region, the effect of excess interface charges at the RESURF is also compared with dual implanted-layer of p-type and n-type. The comparison revealed that the former provides 43 % reduction in Ron with BVDS of 70 V, while the later provides 26 % reduction in Ron together with BVDS of 64 - 68 V. In the second part of my research work, computational load pull (CLP) simulation technique is used in TCAD to extract the impedances of RF-LDMOS at different frequencies under large signal operation. Flexible matching is an issue in the design of broadband or multi-band PAs. Optimum impedance of RF-LDMOS is extracted at operating frequencies of 1, 2 and 2.5 GHz in class AB PA. After this, CLP simulation technique is further developed in TCAD to study the non-linear behavior of RF devices. Through modified CLP technique, non-linear effects inside the transistor structure are studied by conventional two-tone RF signals in time domain. This is helpful to detect and understand the phenomena, which can be resolved to improve the device performance. The third order inter-modulation distortion (IMD3) of RF- LDMOS was observed at different power levels. The IMD3 of −22 dBc is obtained at 1-dB compression point (P1-dB), while at 10 dB back off the value increases to −36 dBc. These results were also verified experimentally by fabricating a linear PA. Similarly, CLP technique is developed further for the analysis of RF devices in high efficiency operation by investigating the odd harmonic effects for the design of class-F PA. RF-LDMOS can provide a power added efficiency (PAE) of 81.2 % in class-F PA at 1 GHz in TCAD simulations. The results are verified by design and fabrication of class-F PA using large signal model of the similar device in ADS. In fabrication, a PAE of 76 % is achieved.

In this thesis we introduce a two-way Doherty amplifier architecture with multiple feedbacks for digital predistortion based on impedance-inverting directional coupler (transcoupler). The tunable two-way Doherty amplifier with a tuned circulator-based impedance inverter is presented. Compact N-way Doherty architectures that subsume impedance inverter and offset line functionality into output matching networks are derived. Comprehensive N-way Doherty amplifier design and analysis techniques based on load-pull characterization of active devices and impedance modulation effects are developed. These techniques were then applied to the design of a two-way Doherty amplifier and a three-way Doherty amplifier which were manufactured and their performance measured and compared to the amplifier performance specifications and simulated results.

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