Innovations in the microarchitecture and prominent advances in the semiconductor process technology enable sophisticated and powerful microprocessors. However, they also lead to increased power consumption. The main contribution of the thesis is the demonstration of Semantics-Oriented Low Power Architecture techniques that use the semantics of memory references and variables used in an application program to reduce the power consumption in the memory sub-system of a microprocessor. The Semantic-Aware Multilateral Partitioning (SAM) technique reduces the cache and TLB power consumption by decoupling the data TLB lookups and the data cache accesses, based on the semantic regions defined by the programming languages and the software convention, into discrete reference sub-streams, namely, stack, global static, and heap. To reduce the power consumed by the snoops in Chip Multiprocessor, we propose a hardware technique called Selective Snoop Probe (SSP) and a compiler-based hardware supported technique called Essential Snoop Probe (ESP) that use the properties of the program variables. By selectively sending the snoop probes, the SSP and ESP techniques relax the conservative nature of the cache coherency protocol and its implementation to reduce power and improve performance.

The continuing trend of miniaturization in semiconductor devices has enabled the integration of complex functionalities on-chip, leading to a proliferation of wireless devices for both mobile and in-office applications. The use of scaled CMOS technologies for high-frequency wireless devices is posing daunting technological challenges, both in the design and post-manufacture testing of such devices. The issue of device power consumption and heat dissipation is also dominating future wireless transceiver designs. This is driven by the trend of increasing operating speeds coupled with dense integration of multi-mode functionalities onto compact form-factors on-chip. In this thesis, a framework for reliable low-power operation of wireless devices is presented. The presented approaches significantly reduce device test costs during production, and operate the device at very low power consumption levels during field operation of the device. Low-cost test, diagnosis, and tuning techniques to reduce to reduce test cost of devices and operational reliability in field. To reduce device power consumption during field operation, adaptation is performed continuously while ensuring that system-level performance metrics are never violated. This approach has direct implications for boosting the battery life of portable wireless devices while ensuring their operational reliability.

Thesis (M.A.)--University of Massachusetts Amherst, 2009. / Open access. Includes bibliographical references (p. 144-154).

Esse trabalho apresenta um estudo sobre os efeitos de radiação em circuitos analógicos de baixa e ultra baixa potência e tensão, identificando as fragilidades destes circuitos (e das respectivas técnicas de projeto) quando aplicados em ambientes radioativos, como, por exemplo, os circuitos em satélites, e em equipamentos de instalações nucleares. Foram realizados estudos de caso, via simulação elétrica utilizando o software HSPICE, considerando os efeitos de degradação elétrica correspondentes a doses de radiação acumulada de até 500krad(Si), além de eventos singulares considerando circuitos de baixa tensão e potência projetados para a tecnologia IBM (GF) de 130nm. Pôde-se observar que o uso de transistores de óxido mais fino, apesar de afetar negativamente o consumo estático, é recomendado para as aplicações estudadas, devido a menor sensibilidade à radiação. Ainda, foi discutido o aumento dos caminhos de fuga de corrente devido ao uso de layout distribuído. Possibilidades e estratégias de mitigação foram discutidas. Por fim, obteve-se um conjunto de sugestões e informações para auxiliar o projetista de circuitos de baixo consumo a obter soluções robustas à radiação. / This work studies the radiation effects in low-power and ultra-low power analog circuits, identifying the fragility of such circuits (and associated design techniques) when employed in radioactive environments, as for example, in satellites and nuclear facilities. Case studies were carried out using HSPICE software for electrical simulation of cumulative radiation effects, corresponding to doses up to 500krad(Si), as well as for single events simulation. We showed that, the use of thin oxide (core) MOSFETS, though increasing the static consumption, is recommended for the studied applications, because they are less sensitive to radiation. Then, we discussed the increase of current leakage paths by the distributed layout style. Mitigation strategies were also discussed. Finally, we obtained a set of suggestions and information to guide the designers of low power analog circuits towards obtaining radiation robust solutions.

Charge-scaling (CS) successive approximation register (SAR) ADC's are widely used in the design of low power electronics. Significant portions of CS-SAR ADC power are consumed by CS capacitor arrays and comparator circuits. This Dissertation presents circuit techniques to reduce the power consumption of both CS capacitor array and the latch comparator during ADC operations. The impacts of the proposed techniques on ADC accuracies are analyzed and circuit techniques are presented to address the accuracy concerns. The dissertation also presents techniques to cope with capacitor mismatches, which becomes more significant with the use of very small unit capacitors in the CS array. These techniques rely on a novel programmable CS capacitor array that allow optimally grouping the unit capacitors. Based on a 0.13um CMOS technology the proposed techniques are verified with extensive circuit simulation. Post layout simulations are done to evaluate the proposed techniques for energy efficient CS capacitor array.

This dissertation presents the design and implementation of a 16-channel sinusoidal generator to stimulate microfluidic devices that use electrokinetic forces to manipulate particles. The generator has both, independent frequency and independent amplitude control for each channel. The stimulation system is based upon a CMOS application specific (ASIC) device developed using 0.35¦Ìm technology. Several generator techniques were compared based on frequency range, total harmonic distortion (THD), and on-chip area. The best alternative for the microfluidic applications is based in a triangle-to-sine converter and presents a frequency range of 8kHz to 21MHz, an output voltage range of 0V to 3.1VPP, and a maximum THD of 5.11%. The fabricated device, has a foot- print of 1560¦Ìm¡Á2030¦Ìm. The amplitude of the outputs is extended using an interface card, achieving voltages of 0V to 15VPP. The generator functionality was tested by performing an experimental set-up with particle trapping. The set-up consisted of a micromachined channel with embedded electrodes configured as two electrical ports located at different positions along the channel. By choosing specific amplitude and frequency values from the generator, different particles suspended in a fluid were simultaneously trapped at different ports. The multichannel stimulator presented here can be used in many microfluidic experiments and devices where particle trapping, separation and characterization is desired. / This dissertation presents the design and implementation of a 16-channel sinusoidal generator to stimulate microfluidic devices that use electrokinetic forces to manipulate particles. The generator has both, independent frequency and independent amplitude control for each channel. The stimulation system is based upon a CMOS application specific (ASIC) device developed using 0.35¦Ìm technology. Several generator techniques were compared based on frequency range, total harmonic distortion (THD), and on-chip area. The best alternative for the microfluidic applications is based in a triangle-to-sine converter and presents a frequency range of 8kHz to 21MHz, an output voltage range of 0V to 3.1VPP, and a maximum THD of 5.11%. The fabricated device, has a foot- print of 1560¦Ìm¡Á2030¦Ìm. The amplitude of the outputs is extended using an interface card, achieving voltages of 0V to 15VPP. The generator functionality was tested by performing an experimental set-up with particle trapping. The set-up consisted of a micromachined channel with embedded electrodes configured as two electrical ports located at different positions along the channel. By choosing specific amplitude and frequency values from the generator, different particles suspended in a fluid were simultaneously trapped at different ports. The multichannel stimulator presented here can be used in many microfluidic experiments and devices where particle trapping, separation and characterization is desired.

Este trabalho trata da aplicação de técnicas de minimização de consumo de potência para blocos digitais para o algoritmo de SAD e o decodificador H.264/AVC Intra-Only. Na descrição de hardware são acrescidas as técnicas de paralelismo e pipeline. Na síntese física e lógica, incluem-se as técnicas de inativação do relógio ( clock gating), múltiplas tensões de threshold, diferentes tecnologias e diferentes tensões de alimentação. A síntese é feita nas ferramentas da CadenceTM com exploração arquitetural e apresenta uma menor energia por operação, quando exigido desempenho equivalente (isoperformance ) para SAD, em baixa frequência, alto paralelismo e, principalmente, com um estágio de pipeline. Além disso, tecnologias CMOS mais avançadas diminuem o consumo de potência dinâmica e, em alguns casos, também diminuem a potência estática por gate equivalente, se utilizadas células High-VT e tensão de alimentação a menor possível. Outro fator a ser destacado é o uso do clock gating que no caso das arquiteturas de SAD, em vez de diminuir, aumenta o consumo de potência dinâmica. Neste trabalho foi realizada a síntese do decodificador Intra-Only. O decodificador com clock gating apresenta um menor consumo de potência, mostrando um caso em que esta técnica é benéfica. Além disso, a utilização de uma tecnologia CMOS 65 nm e, consequentemente, tensão de alimentação menor, levou a uma sensível diminuição no consumo de potência em relação a outros trabalhos similares. / This work presents low-power techniques applications to digital blocks in the SAD algorithm and in the Intra-Only H.264/AVC decoder. In the hardware description, we add parallelism and pipeline techniques. In the logical and physical synthesis exploration, includes the clock gating, multiple threshold voltage, different technologies and multiple supply voltage. The synthesis are done in the CadenceTM tools and show a smaller energy per operation in isoperformance for SAD at low frequency, high parallelism and, mainly, with one pipeline stage. In addition to that, more advanced CMOS technologies decrease the dynamic power consumption and, also, decrease the static power for equivalent gates, if using High-VT cells and lowest possible power supply. Another factor is the clock gating use that in the SAD architecture, instead of decreasing, increases the dynamic power consumption. In this work the design of an Intra-Only H.264/AVC Decoder was performed. This design with clock gating presents lower power consumption, showing a case in which this technique is beneficial in terms of dynamic power. Besides that, the 65 nm CMOS technology uses a lower power supply, resulting in lower power consumption in comparison to other related works.

A crescente utilização de equipamentos móveis que empregam a transformada rápida de Fourier (FFT) nas operações de sinal digital pode ter seu uso restrito devido ao comprometimento da durabilidade da bateria e de suas dimensões. Estas possíveis limitações de uso fazem crescer a necessidade do desenvolvimento de técnicas que visam à otimização nos três requisitos básicos de projeto digital: dissipação de potência, área e atraso. Para tanto, é abordado neste trabalho um método que realiza a implementação de arquiteturas FFT com ênfase na otimização através da decomposição dos coeficientes trigonométricos. No cálculo da FFT, as borboletas desempenham um papel central, uma vez que permitem o cálculo de termos complexos. Neste cálculo, que envolve multiplicações dos dados de entrada com coeficientes trigonométricos apropriados, a otimização das borboletas pode contribuir diretamente para a redução de potência e área. Na técnica proposta são analisados quais são os coeficientes trigonométricos existentes na arquitetura FFT utilizada como base e a escolha para decomposição será o que apresentar o menor custo de implementação em hardware. A decomposição de um coeficiente deve garantir a reconstituição de todos os demais coeficientes necessários para a implementação de toda a arquitetura FFT. Assim, a decomposição diminui o número de coeficientes necessários para reconstruir a FFT original. O conjunto dos novos coeficientes gerados são implementados com apenas somadores\subtratores e deslocamentos através de Multiplicação de Matrizes Constantes (CMM – Constant Matrix Multiplication), associados a um sistema de controle com multiplexadores que controlam o caminho para a correta operação da FFT. As implementações dos circuitos somadores/subtratores são realizadas com métrica no nível de portas lógicas, visando menor atraso e dissipação de potência para topologias com somadores dos tipos CSA (Carry Save Adder) e Ripple carry. Os resultados apresentados pelo método proposto, quando comparados com soluções da literatura, são significativamente satisfatórios, pois minimizaram a dissipação de potência e área em 30% e 24% respectivamente. Os resultados apresentam também a redução de componentes somadores necessários para a implementação de arquiteturas FFTs. / The increasing use of mobile devices using the Fast Fourier Transform (FFT) operations in digital signal may have its use restricted due compromising the durability of the battery and its dimensions. These possible limitations on usage makes grow the need to develop techniques aimed at optimizing the three basic requirements of digital design: power dissipation, area and delay. Therefore, this thesis discusses a method that performs the FFT implementation of architectures with emphasis on optimization through decomposition of twiddle factors (trigonometric coefficients). In the FFT the butterflies play a key role, since it allows the computation of complex terms. In this calculation, which involves multiplications of input data with appropriate twiddle factors, optimization of the butterflies can contribute directly to the reduction in power and area. In the proposed technique are analyzed what are the twiddle factors existing in FFT architecture used as a basis and to choose the decomposition that provide the lowest cost hardware implementation. The decomposition of coefficient to must ensure the rebuilding of all the other twiddle factors necessary for the implementation of the architecture FFT. Thus, the decomposition decreases the number of twiddle factors needed to reconstruct the original FFT. The new sets of coefficients generated are implemented with only adders\subtracters and shifting through of Constants Matrix Multiplication (CMM). A control system of multiplexers makes the way for the correct operation of the FFT. The implementations of the circuits arithmetic adders/subtracters are performed at the gate level, seeking lower delay and power consumption for topologies with adders types of CSA (Carry Save Adder) and Ripple carry. The results presented by the proposed method, compared with literature solutions are significantly satisfactory, since minimized power dissipation and area as well as reduced component adders required for implementation architectures FFTs.

Em circuitos integrados complexos, potência e desempenho têm caminhado em direções opostas tornando o desenvolvimento de dispositivos de baixo consumo uma tarefa altamente custosa. Tradicionalmente, empresas de desenvolvimento de circuitos integrados utilizam variadas técnicas para garantir os requisitos de potência, no entanto, técnicas baseadas em biblioteca de células tem se tornado um gargalo para o processo de desenvolvimento. À medida que os projetos aumentam de complexidade e densidade, maior tende a ser a potência dissipada por estes dispositivos, e assim, mais importante torna-se sua redução. Buscando aumentar a capacidade de redução de potência, projetistas tem aplicado diferentes técnicas para cada nível de abstração do fluxo de projeto. No nível físico, de maneira a contornar os limites das bibliotecas de células, o desenvolvimento de células especificamente projetadas tem se tornado uma rotina em projetos com grandes restrições de potência. Observando este requisito, este trabalho visa pesquisar a implementação e otimização de células digitais CMOS (Complementary Metal-Oxide-Semiconductor) estática em nível de transistores, e o emprego de metodologia de projeto livre de biblioteca como um recurso para a concepção de sistemas de baixa potência. De um modo geral, menos transistores são desejáveis para reduzir a dissipação de potência, no entanto, longas cadeias de transistores, necessários para implementar funções lógicas específicas, conduz ao aumento do tempo de transição, e, portanto, maior dissipação de energia. A fim de evitar este efeito, construímos uma função de mapeamento, com base no tamanho dos transistores, de forma a evitar um tempo de transição lento e minimizar o número de transistores. O uso deste método demonstrou ser eficaz para o ajuste fino de circuitos de baixa potência, resultando em uma redução média de 6.35% no consumo dinâmico e de 8.26% no consumo estático em comparação com a metodologia baseada em biblioteca de células. Como trabalho adicional, é apresentado um fluxo automatizado de mapeamento lógico e capaz de gerar redes de transistores específicas para cada projeto, tornando possível sua utilização em ferramentas de desenvolvimento tradicionais. / In complex integrated circuits, power and performance have moved in opposite directions making the design of low-power devices a highly costly task. Traditionally, integrated circuit design companies adopt many techniques to ensure power requirements, however, techniques based on cell library has become a bottleneck for the development process. As the design complexity and density increase, greater will be the power dissipated, and thus its reduction becomes more important. Seeking to increase the power reduction capability, designers have applied different techniques for each level of the design flow abstraction. At the physical level, so as to bypass the limits of cell libraries, the development of specifically designed cells has become a routine for designs with large power constraints. Observing this requirement, this work aims to investigate the implementation and optimization of digital static CMOS (Complementary Metal-Oxide-Semiconductor) cell at transistors level, and the use of library free design methodology as a resource for designing low power systems. In general, fewer transistors are desirable to reduce power dissipation, however, long chains of transistors, necessary for implementing specific logical functions, leads to the increase of the transition time, and hence greater energy dissipation. In order to avoid this effect, we constructed a mapping function, based on transistor size, in order to avoid slow transition time and minimize the number of transistors. The use of this method has proven effective for fine adjustment low power circuits, resulting in an average reduction of 6.35% in dynamic power and 8.26% in static power as compared with the cell library based methodology. As further work, an automated flow set is presented for the logical mapping able to generate specific networks of transistors for each design, making possible their use in traditional design tools.

In this work, we investigate circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). We developed four low-power SAR-ADC design techniques, which are: 1) Low-power SAR-ADC design with split voltage reference, 2) Charge recycling techniques for low-power SAR-ADC design, 3) Low-power SAR-ADC design using two-capacitor arrays, 4) Power reduction techniques by dynamically minimizing SAR-ADC conversion cycles. Matlab simulations are performed to investigate the power saving by the proposed techniques. Simulation results show that significant power reduction can be achieved by using the developed techniques. In addition, design issues such as area overhead, design complexity associated with the proposed low-power techniques are also discussed in the thesis.