In this thesis, we tackle the problem of designing and implementing a wireless video sensor network for a surveillance application. The goal was to design a low power content aware system that is able to take an image from an image sensor, determine blocks in the image that contain important information and encode those block for transmission thus reducing the overall transmission effort. At the same time, the encoder and the preprocessor must not consume so much computation power that the utility of this system is lost. We have implemented such a system which uses a combination of Edge Detection and Frame Differencing to determine useful information within an image. A JPEG encoder then encodes the important blocks for transmission. An implementation on a FPGA is presented in this work. This work demonstrates that preprocessing gives us a 48.6 % reduction in power for a single frame while maintaining a delivery ratio of above 85 % for the given set of test frames.

Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. In this paper, a 2*2 Swap gate which is a reduced implementation in terms of quantum cost and delay to the previous Swap gate is presented. Next, a novel 3*3 programmable UPG gate capable of calculating the fundamental logic calculations is presented and verified, and its advantages over the Toffoli and Peres gates are discussed. The UPG is then implemented in a reduced design for calculating n-bit AND, n-bit OR and n-bit ZERO calculations. Then, two 3*3 RMUX gates capable of multiplexing two input values with reduced quantum cost and delay compared to the previously existing Fredkin gate is presented and verified. Next, 4*4 reversible gate is presented and verified which is capable of producing the calculations necessary for two-bit comparisons. The UPG and RC are implemented in the design of novel sequential and tree-based comparators. Then, two novel 4*4 reversible logic gates (MRG and PAOG) are proposed with minimal delay, and may be configured to produce a variety of logical calculations on fixed output lines based on programmable select input lines. A 5*5 structure (MG) is proposed that extends the capabilities of both the MRG and PAOG. The comparator designs are verified and its advantages to previous designs are discussed. Then, reversible implementations of ripple-carry, carry-select and Kogge-Stone carry look-ahead adders are analyzed and compared. Next, implementations of the Kogge-Stone adder with sparsity-4, 8 and 16 were designed, verified and compared. The enhanced sparsity-4 Kogge-Stone adder with ripple-carry adders was selected as the best design, and its implemented in the design of a 32-bit arithmetic logic unit is demonstrated. The proposed ALU design is verified and its advantages over the only existing ALU design are quantitatively analyzed.

Advances in wireless technologies in the last ten years have created considerable opportunities as well as challenges for wireless body medical systems. The foremost challenge is how to build a reliable system connecting heterogeneous body sensors and actuators in an open system environment. In this dissertation, we present our work towards this goal. The system addresses four design issues: the underlying network architecture, the network scheduling disciplines, the location determination and tracking methods, and the embedded application execution architecture. We first present the design of an adaptive wireless protocol (MBStarPlus) to provide the basic wireless platform WBAN (Wireless Body Area Network). MBStarPlus is a real-time, secure, robust and flexible wireless network architecture. It is designed to utilize any low-power wireless radio as its physical layer. The TDMA mechanism is adopted for realtime data delivery. The time-slot length is adjustable for flexibility. Multiple technologies are utilized to provide reliability and security. We next investigate how to coordinate the body sensors/actuators that can optimally select from a range (maximum and minimum) of data rates. Two bandwidth scheduling algorithms are proposed. One is a greedy algorithm that works for sensors with limited computational capability. The other is the UMinMax scheduling algorithm that has better scalability and power-saving performance but is more computationally intensive. The third issue addressed in this proposal is how to achieve location determination and tracking by a mix of high-precision but expensive and lower-precision but cost-effective sensors. This is achieved by a novel collaborative location determination scheme ColLoc that can integrate different types of distance measurements into a location estimation algorithm by weighing them according to their precision levels. Through this, a localization service can be both cost-effective and sufficiently accurate. Fourth, in order to minimize the effects of long network latency when the body network scales up, we propose ControlInGateway, an architectural feature that allows a control application to be executed inside the network gateway without the host's involvement. With ControlInGateway, a wireless system could achieve the same control quality as a wired system. / text

The widespread deployment of wireless sensors in our homes, offices, factories and infrastructure has opened the door for system designers to create novel approaches for powering wireless sensor nodes. In recent years, energy harvesting has emerged as the power supply of choice for embedded system designers, enabling wireless sensors to be used in applications that previously were not feasible with conventional battery-powered designs. This report details the design and development of an energy harvesting wireless sensor from concept to production. Design constraints included the requirement to operate reliably in a wide variety of environments, the use of commercially available components, and a visually appealing form factor. The result is a very power-efficient, solar-powered wireless sensor that measures temperature, voltage, and illumination level at the solar cell and has an ultra slim form factor. / text

Multilevel inverters offer many well-known advantages for use in high-voltage and high-power applications, but they are also well suited for low-power applications. A single phase inverter is developed in this paper to deliver power from a residential-scale system of Photovoltaic panels to the utility grid. The single-stage inverter implements a novel control technique for the reversing voltage topology to produce a stepped output waveform. This approach increases the granularity of control over the PV systems, modularizing key components of the inverter and allowing the inverter to extract the maximum power from the systems. The adaptive controller minimizes harmonic distortion in its output and controls the level of reactive power injected to the grid. A computer model of the controller is designed and tested in the MATLAB program Simulink to assess the performance of the controller. To validate the results, the performance of the proposed inverter is compared to that of a comparable voltage-sourced inverter.

In this thesis we discuss the design and implementation of Digital Signal Processing (DSP) applications in a standard digital CMOS technology. The aim is to fulfill a throughput requirement with lowest possible power consumption. As a case study a frequency selective filter is implemented using a half-band FIR filter and a bireciprocal Lattice Wave Digital Filter (LWDF) in a 0.35 µm CMOS process. The thesis is presented in a top-down manner, following the steps in the topdown design methodology. This design methodology, which has been used for bit-serial maximally fast implementations of IIR filters in the past, is here extended and applied for digit-serial implementations of recursive and non-recursive algorithms. Transformations such as pipelining and unfolding for increasing the throughput is applied and compared from throughput and power consumption points of view. A measure of the level of the logic pipelining is developed, i.e., the Latency Model (LM), which is used as a tuning variable between throughput and power consumption. The excess speed gained by the transformations can later be traded for low power operation by lowering the supply voltage, i.e., architecture driven voltage scaling. In the FIR filter case, it is shown that for low power operation with a given throughput requirement, that algorithm unfolding without pipelining is preferable. Decreasing the power consumption with 40, and 50 percent compared to pipelining at the logic or algorithm level, respectively. The digit-size should be tuned with the throughput requirement, i.e., using a large digit-size for low throughput requirement and decrease the digit-size with increasing throughput. In the bireciprocal LWDF case, the LM order can be used as a tuning variable for a trade-off between low energy consumption and high throughput. In this case using LM 0, i.e., non-pipelined processing elements yields minimum energy consumption and LM 1, i.e., use of pipelined processing elements, yields maximum throughput. By introducing some pipelined processing elements in the non-pipelined filter design a fractional LM order is obtained. Using three adders between every pipeline register, i.e., LM 1/3, yields a near maximum throughput and a near minimum energy consumption. In all cases should the digit-size be equal to the number of fractional bits in the coefficient. At the arithmetic level, digit-serial adders is designed and implemented in a 0.35 µm CMOS process, showing that for the digit-sizes, , the Ripple-Carry Adders (RCA) are preferable over Carry-Look-Ahead adders (CLA) from a throughput point of view. It is also shown that fixed coefficient digitserial multipliers based on unfolding of serial/parallel multipliers can obtain the same throughput as the corresponding adder in the digit-size range D = 2...4. A complex multiplier based on distributed arithmetic is used as a test case, implemented in a 0.8 µm CMOS process for evaluation of different logic styles from robustness, area, speed, and power consumption points of view. The evaluated logic styles are, non-overlapping pseudo two-phase clocked C2MOS latches with pass-transistor logic, Precharged True Single Phase Clocked logic (PTSPC), and Differential Cascade Voltage Switch logic (DCVS) with Single Transistor Clocked (STC) latches. In addition we propose a non-precharged true single phase clocked differential logic style, which is suitable for implementation of robust, high speed, and low power arithmetic processing elements, denoted Differential NMOS logic (DN-logic). The comparison shows that the two-phase clocked logic style is the best choice from a power consumption point of view, when voltage scaling can not be applied and the throughput requirement is low. However, the DN-logic style is the best choice when the throughput requirements is high or when voltage scaling is used.

Bandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage reference for the entire IC. The most used CMOS implementation for voltage references is the bandgap circuit due to its high predictability, and low dependence of the supply voltage and temperature of operation. This work studies a CMOS implementation of a resistor-less bandgap reference, which consumes low power. The most relevant and traditional approaches usually employed to implement bandgap voltage references are investigated. The impact of process, power-supply, load and temperature variations has been analyzed and simulated. The functionality of critical components of the circuit has been verified through chip implementation. / text

Low-power digital design has been a widely researched area for the past twenty years. The growing demand for mobile computing made low power an especially important quality for such systems and encouraged researchers to find new ways of reducing power dissipation. Aggressive voltage scaling was recently published as a new paradigm for reducing power dissipation in digital circuits and the use of soft-edge flip-flops is one such technique in this category. In this thesis, we propose a soft-edge flip-flop topology that is better suited to implement the soft-edge property compared to the previously published implementations. In addition, we present the effectiveness of the soft-edge flip-flop technique by applying it to a practical VLSI design implemented with the TSMC 0.18um standard cell library. Using HSIM transistor-level SPICE simulator, we show that at least 25% power reduction is achievable in the whole circuit with a negligible area overhead. / text

This dissertation presents circuit techniques for designing high performance amplifiers. In low power design, the range of common mode input signal shrinks due to reduced power supply voltage. In addition, due to reduced bias current, noise density rises. The reduced input signal range and raised noise floor severely degrade system dynamic range. A novel rail to rail input circuit is presented. The proposed circuit has advantages over conventional circuits in term of noise and power consumption. Moreover, due to reduced bias current, low power amplifiers typically have lower bandwidth and slew rate, which limits their dynamic performance. The bandwidth is further reduced at high gain settings because of the constant gain bandwidth product. A novel self-adaptive compensation technique to extend small signal bandwidth and improve slew behavior is presented. If an amplifier needs to drive various capacitive and/or resistive loads, parallel Miller compensation is the most power efficient frequency compensation scheme. However, the frequency response of parallel Miller compensation is complicated and no thorough analysis on frequency response has been given in literatures. To illustrate the connection between poles/zeros and each individual circuit component, we use a design oriented approach to derive transfer functions for various load conditions. With these transfer functions, circuit designers can optimize their design accordingly. As a case study, a low power precision instrumentation amplifier is designed. Compared to low power instrumentation amplifiers on the market or reported in literature, it can save at least 40% power, meanwhile offer higher bandwidth and faster slew rate at typical gain settings. Many challenges also exist in designing high voltage amplifiers. To achieve low cost and high performance, a novel topology of a high voltage current sensing amplifier is proposed. With this topology, major portion of amplifiers can be designed with low voltage, for instance, 5 V, devices, and only a limited amount of LDMOS are required to stand off high voltage. This topology does not have high noise gain as conventional solutions have. The same principle can be used for other high voltage amplifiers. A prototype chip is fabricated. The amplifier functions as expected. Test results are presented.

This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3.3 V. The comparator is designed for time-interleaved bandpass sigma-delta ADC. Due to the nature of the target application, it should be possible to turn off the components to avoid the static power consumption. The comparator of this design implements the turn off technique when it is not in use. The settling time of the comparator is less than half the clock cycle which means it does not effect the functionality of the bandpass sigma-delta ADC in terms of speed. The simulation results are derived using Cadence environment. The results show that the comparator has 6-bit resolution and power consumption of 4.13 mW for the worst-case frequency of 250 MHz. It fulfills all the performance requirements, most of them with large margins.