Significant characteristic of any VLSI design circuit is its power, reliability, operating frequency and implementation cost. Dynamic CMOS designs provide high operating speeds compared to static CMOS designs combined with low silicon area requirement. This thesis describes the design and the optimization of high performance carry select adder. Previous researchers believed that existing CSA designs has reached theoretical speed bound. But, only a considerable portion of hardware resources of traditional adders are used in worst case scenario. Based on this observation our proposed design will improve on theoretical limit. The major scope of this proposed design is to increase the speed of carry generation between intermediate blocks of Carry select Adder (CSA) by introducing fast multiple clock Domino Manchester carry chain (MCC) that generates carry outputs. This design technique will have some advantages compared to pre-existing implementations in operating speed and power delay product. Simulation has been done using GPDK (Generic Process Design Kits) technology using cadence virtuoso. Thus the proposed technique provides advantages over pre-existing techniques in terms of operating speed.

Arithmetic units and logic circuits are critical components of any VLSI system. Thus realizing efficient arithmetic units and logic circuits is required for better performance of a data path unit and therefore microprocessor or digital signal processor (DSP). Adders are basic building blocks of any processor or data path application. For the design of high performance processing units, high-speed adders with low power consumption is a requirement. Carry Select Adder (CSA) is known to be one of the fastest adders used in many data processing applications. This first contribution of the dissertation is the design of a new CSA architecture using Manchester carry chain (MCC) in multioutput domino CMOS logic. It employs a novel MCC blocks in a hierarchical approach in the design of the CSA. The proposed MCC block is also extended in designing a power-delay and area efficient Vedic multiplier based on "Urdhva-Tiryakbhyam”. The simulation results shows that the proposed architecture achieves two fold advantages in terms of power-delay product (PDP) and hardware overhead. Apart from adders and multipliers, counters also play a major role in a data path unit. Counters are basic building blocks in many VLSI applications such as timers, memories, ADCs/DACs, frequency dividers etc. It is observed that design of counters has power overhead because of requirement of high power consumption for the clock signal distribution and undesired activity of flip-flops due to presence of clocks. The second contribution of the dissertation is the power efficient design of synchronous counters that reduces the power consumption due to clock distribution for different flip-flops and offers high reliability. The simulation results shows that the proposed counter design has lower power requirement and power-area product than existing counter architectures. Pipelines can be used for achieving high circuit operating speeds. However, as the operating frequency increases, the number of pipeline stages also increase linearly and so the memory elements. The third contribution of the dissertation is the dynamic memory-less pipeline design based on sinusoidal three-phase clocking scheme that reduces the power required by the clock and offers high circuit operating frequencies. Finally, the dissertation presents a novel tool for Boolean-function realization with minimum number of transistor in series. This tool is based on applying a new functional decomposition algorithms to decompose the initial Boolean-function into a network of smaller sub-functions and subsequently generating the final circuit. The effectiveness of proposed technique is estimated using circuit level simulations as well as using automated tool. The number of levels required using proposed technique is reduced by an average of 70% compared to existing techniques.

The memristor is an emerging nano-device. Low power operation, high density, scalability, non-volatility, and compatibility with CMOS Technology have made it a promising technology for memory, Boolean implementation, computing, and logic systems. This dissertation focuses on testing and design of such applications. In particular, we investigate on testing of memristor-based memories, design of memristive implementation of Boolean functions, and reliability and design of neuromorphic computing such as neural network. In addition, we show how to modify threshold logic gates to implement more functions. Although memristor is a promising emerging technology but is prone to defects due to uncertainties in nanoscale fabrication. Fast March tests are proposed in Chapter 2 that benefit from fast write operations. The test application time is reduced significantly while simultaneously reducing the average test energy per cell. Experimental evaluation in 45 nm technology show a speed-up of approximately 70% with a decrease in energy by approximately 40%. DfT schemes are proposed to implement the new test methods. In Chapter 3, an Integer Linear Programming based framework to identify current-mode threshold logic functions is presented. It is shown that threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. Experimental results show that many more functions can be implemented with predetermined hardware overhead, and the hardware requirement of a large percentage of existing threshold functions is reduced when comparing to the traditional CMOS-based threshold logic implementation. In Chapter 4, a new method to implement threshold logic functions using memristors is presented. This method benefits from the high range of memristor’s resistivity which is used to define different weight values, and reduces significantly the transistor count. The proposed approach implements many more functions as threshold logic gates when comparing to existing implementations. Experimental results in 45 nm technology show that the proposed memristive approach implements threshold logic gates with less area and power consumption. Finally, Chapter 5 focuses on current-based designs for neural networks. CMOS aging impacts the total synaptic current and this impacts the accuracy. Chapter 5 introduces an enhanced memristive crossbar array (MCA) based analog neural network architecture to improve reliability due to the aging effect. A built-in current-based calibration circuit is introduced to restore the total synaptic current. The calibration circuit is a current sensor that receives the ideal reference current for non-aged column and restores the reduced sensed current at each column to the ideal value. Experimental results show that the proposed approach restores the currents with less than 1% precision, and the area overhead is negligible.

Phase locked loop (PLLs) are the keystone for the electronic as well as for the communication circuits. Without any exaggeration, PLLs are found almost in every electronic and communication devices. Countless research has been performed, for the modification and enhancement of the PLLs circuit. While, due to the numerous advantage of the digital circuitry, the recent research is focusing on the all digital implementation of the PLLs. Therefore, it was competitive to touch with burning research. Low power and wide range all digital phase locked loop (ADPLL), for video applications is presented. ADPLL has an operating input frequency between 10kHz to 150 kHz and output frequency between 10 MHz to 300 MHz. The phase frequency detector (PFD) is based on D-flip flops, having two output error and direction signal. The traditional charge pump (CP) is replaced by time-to-digital converters (TDC) and analog low pass filter (LPF) by digital low pass filter (digital-LPF). For completely digital architecture, voltage controlled oscillator (VCO) is replaced by the digitally controlled oscillator (DCO). In DCO, eleven bits are dedicated for controlling bits, two bits for biasing and one bit for enable the DCO. The designed steps for ADPLL were almost similar to the designed steps of a second order analog PLL. The ADPLL is implemented on a CMOS 65-nm technology.

Esse trabalho apresenta um estudo sobre os efeitos de radiação em circuitos analógicos de baixa e ultra baixa potência e tensão, identificando as fragilidades destes circuitos (e das respectivas técnicas de projeto) quando aplicados em ambientes radioativos, como, por exemplo, os circuitos em satélites, e em equipamentos de instalações nucleares. Foram realizados estudos de caso, via simulação elétrica utilizando o software HSPICE, considerando os efeitos de degradação elétrica correspondentes a doses de radiação acumulada de até 500krad(Si), além de eventos singulares considerando circuitos de baixa tensão e potência projetados para a tecnologia IBM (GF) de 130nm. Pôde-se observar que o uso de transistores de óxido mais fino, apesar de afetar negativamente o consumo estático, é recomendado para as aplicações estudadas, devido a menor sensibilidade à radiação. Ainda, foi discutido o aumento dos caminhos de fuga de corrente devido ao uso de layout distribuído. Possibilidades e estratégias de mitigação foram discutidas. Por fim, obteve-se um conjunto de sugestões e informações para auxiliar o projetista de circuitos de baixo consumo a obter soluções robustas à radiação. / This work studies the radiation effects in low-power and ultra-low power analog circuits, identifying the fragility of such circuits (and associated design techniques) when employed in radioactive environments, as for example, in satellites and nuclear facilities. Case studies were carried out using HSPICE software for electrical simulation of cumulative radiation effects, corresponding to doses up to 500krad(Si), as well as for single events simulation. We showed that, the use of thin oxide (core) MOSFETS, though increasing the static consumption, is recommended for the studied applications, because they are less sensitive to radiation. Then, we discussed the increase of current leakage paths by the distributed layout style. Mitigation strategies were also discussed. Finally, we obtained a set of suggestions and information to guide the designers of low power analog circuits towards obtaining radiation robust solutions.

abstract: Improving energy efficiency has always been the prime objective of the custom and automated digital circuit design techniques. As a result, a multitude of methods to reduce power without sacrificing performance have been proposed. However, as the field of design automation has matured over the last few decades, there have been no new automated design techniques, that can provide considerable improvements in circuit power, leakage and area. Although emerging nano-devices are expected to replace the existing MOSFET devices, they are far from being as mature as semiconductor devices and their full potential and promises are many years away from being practical. The research described in this dissertation consists of four main parts. First is a new circuit architecture of a differential threshold logic flipflop called PNAND. The PNAND gate is an edge-triggered multi-input sequential cell whose next state function is a threshold function of its inputs. Second a new approach, called hybridization, that replaces flipflops and parts of their logic cones with PNAND cells is described. The resulting \hybrid circuit, which consists of conventional logic cells and PNANDs, is shown to have significantly less power consumption, smaller area, less standby power and less power variation. Third, a new architecture of a field programmable array, called field programmable threshold logic array (FPTLA), in which the standard lookup table (LUT) is replaced by a PNAND is described. The FPTLA is shown to have as much as 50% lower energy-delay product compared to conventional FPGA using well known FPGA modeling tool called VPR. Fourth, a novel clock skewing technique that makes use of the completion detection feature of the differential mode flipflops is described. This clock skewing method improves the area and power of the ASIC circuits by increasing slack on timing paths. An additional advantage of this method is the elimination of hold time violation on given short paths. Several circuit design methodologies such as retiming and asynchronous circuit design can use the proposed threshold logic gate effectively. Therefore, the use of threshold logic flipflops in conventional design methodologies opens new avenues of research towards more energy-efficient circuits. / Dissertation/Thesis / Doctoral Dissertation Computer Science 2015

abstract: With the new age Internet of Things (IoT) revolution, there is a need to connect a wide range of devices with varying throughput and performance requirements. In this thesis, a wireless system is proposed which is targeted towards very low power, delay insensitive IoT applications with low throughput requirements. The low cost receivers for such devices will have very low complexity, consume very less power and hence will run for several years. Long Term Evolution (LTE) is a standard developed and administered by 3rd Generation Partnership Project (3GPP) for high speed wireless communications for mobile devices. As a part of Release 13, another standard called narrowband IoT (NB-IoT) was introduced by 3GPP to serve the needs of IoT applications with low throughput requirements. Working along similar lines, this thesis proposes yet another LTE based solution called very narrowband IoT (VNB-IoT), which further reduces the complexity and power consumption of the user equipment (UE) while maintaining the base station (BS) architecture as defined in NB-IoT. In the downlink operation, the transmitter of the proposed system uses the NB-IoT resource block with each subcarrier modulated with data symbols intended for a different user. On the receiver side, each UE locks to a particular subcarrier frequency instead of the entire resource block and operates as a single carrier receiver. On the uplink, the system uses a single-tone transmission as specified in the NB-IoT standard. Performance of the proposed system is analyzed in an additive white Gaussian noise (AWGN) channel followed by an analysis of the inter carrier interference (ICI). Relationship between the overall filter bandwidth and ICI is established towards the end. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2017

Les technologies SOI partiellement désertées (PD-SOI), permettent de gagner en performances ou en consommation dynamique, par rapport à leur équivalent sur substrat massif (BULK). Leur inconvénient principal est la consommation statique qui est bien supérieure, en raison principalement de l'effet de body flottant de ses transistors. Ce travail propose une technique de réduction de la consommation statique, pour la technologie PD-SOI, basée sur le principe des interrupteurs de puissance. Un nouveau facteur de mérite recherchant le meilleur compromis entre vitesse, courant de fuite et surface est introduit pour la sélection du meilleur interrupteur de puissance. L'interrupteur de puissance proposé apporte par rapport à une solution de référence, et pour le même courant de fuite en mode éteint, une réduction de la résistance équivalente en mode passant de 20%. Les tests comparatifs sur Silicium de blocs LDPC incluant ces montages montrent, entre PD-SOI et BULK, un gain de 20% en vitesse pour la même tension d'alimentation, une réduction de 30% de la consommation dynamique pour la même vitesse et une division par 2 de la consommation statique. Enfin, une bascule de rétention, élément à associer aux interrupteurs de puissance, optimisée pour le PD-SOI, est proposée. Cette bascule est conçue de manière robuste et peu fuyante. / Partially depleted SOI technologies (PD-SOI), offer advantages in terms of speed and dynamic power consumption compared to bulk technologies. The main drawback of the PD-SOI technology is its static power consumption, which is higher than bulk one. It is due to the floating body of its transistors. This work presents a new static power consumption design technique based on power switches. A new factor of merit is introduced selecting the power switch with the best trade-off in terms of leakage current, speed and area. A new power switch brings, in comparison to a reference solution, a reduction of 20% of the ON mode equivalent resistance for the same OFF mode leakage current PD-SOI Silicon validation test chips include LDPC bloc supplied by the proposed solution. Comparing to the bulk technology, a speed gain of 20% is measured for the same voltage supply and a dynamic power consumption reduction of 30% at same speed is achieved. This solution allows reducing by 2 the static power consumption. Finally, a retention flip-flop associated to the implementation of power switches and optimized in PD-SOI is proposed. This flip-flop is designed to be robust with a low leakage current.

Este trabalho trata da aplicação de técnicas de minimização de consumo de potência para blocos digitais para o algoritmo de SAD e o decodificador H.264/AVC Intra-Only. Na descrição de hardware são acrescidas as técnicas de paralelismo e pipeline. Na síntese física e lógica, incluem-se as técnicas de inativação do relógio ( clock gating), múltiplas tensões de threshold, diferentes tecnologias e diferentes tensões de alimentação. A síntese é feita nas ferramentas da CadenceTM com exploração arquitetural e apresenta uma menor energia por operação, quando exigido desempenho equivalente (isoperformance ) para SAD, em baixa frequência, alto paralelismo e, principalmente, com um estágio de pipeline. Além disso, tecnologias CMOS mais avançadas diminuem o consumo de potência dinâmica e, em alguns casos, também diminuem a potência estática por gate equivalente, se utilizadas células High-VT e tensão de alimentação a menor possível. Outro fator a ser destacado é o uso do clock gating que no caso das arquiteturas de SAD, em vez de diminuir, aumenta o consumo de potência dinâmica. Neste trabalho foi realizada a síntese do decodificador Intra-Only. O decodificador com clock gating apresenta um menor consumo de potência, mostrando um caso em que esta técnica é benéfica. Além disso, a utilização de uma tecnologia CMOS 65 nm e, consequentemente, tensão de alimentação menor, levou a uma sensível diminuição no consumo de potência em relação a outros trabalhos similares. / This work presents low-power techniques applications to digital blocks in the SAD algorithm and in the Intra-Only H.264/AVC decoder. In the hardware description, we add parallelism and pipeline techniques. In the logical and physical synthesis exploration, includes the clock gating, multiple threshold voltage, different technologies and multiple supply voltage. The synthesis are done in the CadenceTM tools and show a smaller energy per operation in isoperformance for SAD at low frequency, high parallelism and, mainly, with one pipeline stage. In addition to that, more advanced CMOS technologies decrease the dynamic power consumption and, also, decrease the static power for equivalent gates, if using High-VT cells and lowest possible power supply. Another factor is the clock gating use that in the SAD architecture, instead of decreasing, increases the dynamic power consumption. In this work the design of an Intra-Only H.264/AVC Decoder was performed. This design with clock gating presents lower power consumption, showing a case in which this technique is beneficial in terms of dynamic power. Besides that, the 65 nm CMOS technology uses a lower power supply, resulting in lower power consumption in comparison to other related works.

A crescente utilização de equipamentos móveis que empregam a transformada rápida de Fourier (FFT) nas operações de sinal digital pode ter seu uso restrito devido ao comprometimento da durabilidade da bateria e de suas dimensões. Estas possíveis limitações de uso fazem crescer a necessidade do desenvolvimento de técnicas que visam à otimização nos três requisitos básicos de projeto digital: dissipação de potência, área e atraso. Para tanto, é abordado neste trabalho um método que realiza a implementação de arquiteturas FFT com ênfase na otimização através da decomposição dos coeficientes trigonométricos. No cálculo da FFT, as borboletas desempenham um papel central, uma vez que permitem o cálculo de termos complexos. Neste cálculo, que envolve multiplicações dos dados de entrada com coeficientes trigonométricos apropriados, a otimização das borboletas pode contribuir diretamente para a redução de potência e área. Na técnica proposta são analisados quais são os coeficientes trigonométricos existentes na arquitetura FFT utilizada como base e a escolha para decomposição será o que apresentar o menor custo de implementação em hardware. A decomposição de um coeficiente deve garantir a reconstituição de todos os demais coeficientes necessários para a implementação de toda a arquitetura FFT. Assim, a decomposição diminui o número de coeficientes necessários para reconstruir a FFT original. O conjunto dos novos coeficientes gerados são implementados com apenas somadores\subtratores e deslocamentos através de Multiplicação de Matrizes Constantes (CMM – Constant Matrix Multiplication), associados a um sistema de controle com multiplexadores que controlam o caminho para a correta operação da FFT. As implementações dos circuitos somadores/subtratores são realizadas com métrica no nível de portas lógicas, visando menor atraso e dissipação de potência para topologias com somadores dos tipos CSA (Carry Save Adder) e Ripple carry. Os resultados apresentados pelo método proposto, quando comparados com soluções da literatura, são significativamente satisfatórios, pois minimizaram a dissipação de potência e área em 30% e 24% respectivamente. Os resultados apresentam também a redução de componentes somadores necessários para a implementação de arquiteturas FFTs. / The increasing use of mobile devices using the Fast Fourier Transform (FFT) operations in digital signal may have its use restricted due compromising the durability of the battery and its dimensions. These possible limitations on usage makes grow the need to develop techniques aimed at optimizing the three basic requirements of digital design: power dissipation, area and delay. Therefore, this thesis discusses a method that performs the FFT implementation of architectures with emphasis on optimization through decomposition of twiddle factors (trigonometric coefficients). In the FFT the butterflies play a key role, since it allows the computation of complex terms. In this calculation, which involves multiplications of input data with appropriate twiddle factors, optimization of the butterflies can contribute directly to the reduction in power and area. In the proposed technique are analyzed what are the twiddle factors existing in FFT architecture used as a basis and to choose the decomposition that provide the lowest cost hardware implementation. The decomposition of coefficient to must ensure the rebuilding of all the other twiddle factors necessary for the implementation of the architecture FFT. Thus, the decomposition decreases the number of twiddle factors needed to reconstruct the original FFT. The new sets of coefficients generated are implemented with only adders\subtracters and shifting through of Constants Matrix Multiplication (CMM). A control system of multiplexers makes the way for the correct operation of the FFT. The implementations of the circuits arithmetic adders/subtracters are performed at the gate level, seeking lower delay and power consumption for topologies with adders types of CSA (Carry Save Adder) and Ripple carry. The results presented by the proposed method, compared with literature solutions are significantly satisfactory, since minimized power dissipation and area as well as reduced component adders required for implementation architectures FFTs.