Frequency synthesizers are essential components for modern wireless and wireline communication systems as they provide the local oscillator signal required to transmit and receive data at very high rates. They are also vital for computing devices and microcontrollers as they generate the clocks required to run all the digital circuitry responsible for the high speed computations. Data rates and clocking speeds are continuously increasing to accommodate for the ever growing demand on data and computational power. This places stringent requirements on the performance metrics of frequency synthesizers. They are required to run at higher speeds, cover a wide range of frequencies, provide a low jitter/phase noise output and consume minimum power and area. In this work, we present new techniques and architectures for implementing high speed frequency synthesizers which fulfill the aforementioned requirements. We propose a new architecture and design approach for the realization of wideband millimeter-wave frequency synthesizers. This architecture uses two-step multi-order harmonic generation of a low frequency phase-locked signal to generate wideband mm-wave frequencies. A prototype of the proposed system is designed and fabricated in 90nm Complementary Metal Oxide Semiconductor (CMOS) technology. Measurement results demonstrated that a very wide tuning range of 5 to 32 GHz can be achieved, which is costly to implement using conventional techniques. Moreover the power consumption per octave resembles that of state-of-the art reports. Next, we propose the N-Push cyclic coupled ring oscillator (CCRO) architecture to implement two high performance oscillators: (1) a wideband N-Push/M-Push CCRO operating from 3.16-12.8GHz implemented by two harmonic generation operations using the availability of different phases from the CCRO, and (2) a 13-25GHz millimeter-wave N-Push CCRO with a low phase noise performance of -118dBc/Hz at 10MHz. The proposed oscillators achieve low phase noise with higher FOM than state of the art work. Finally, we present some improvement techniques applied to the performance of phase locked loops (PLLs). We present an adaptive low pass filtering technique which can reduce the reference spur of integer-N charge-pump based PLLs by around 20dB while maintaining the settling time of the original PLL. Another PLL is presented, which features very low power consumption targeting the Medical Implantable Communication Standard. It operates at 402-405 MHz while consuming 600microW from a 1V supply.

Recently, there have been a great interest in the millimeter-wave (mmW) and terahertz (THz) bands due to the unique features they provide for various applications. For example, the mmW is not significantly affected by the atmospheric constraints and it can penetrate through clothing and other dielectric materials. Therefore, it is suitable for a vast range of imaging applications such as vision, safety, health, environmental studies, security and non-destructive testing. Millimeter-wave imaging systems have been conventionally used for high end applications implementing sophisticated and expensive technologies. Recent advancements in the silicon integrated and low loss material passive technologies have created a great opportunity to study the feasibility of low cost mmW imaging systems. However, there are several challenges to be addressed first. Examples are modeling of active and passive devices and their low performance, highly attenuated channel and poor signal to noise ratio in the mmW. The main objective of this thesis is to investigate and develop new technologies enabling cost-effective implementation of mmW and sub-mmW imaging systems. To achieve this goal, an integrated active Rotman lens architecture is proposed as an ultimate solution to combine the unique properties of a Rotman lens with the superiority of CMOS technology for fabrication of cost effective integrated mmW systems. However, due to the limited sensitivity of on-chip detectors in the mmW, a large number of high gain, wide-band and miniaturized mmW Low Noise Amplifiers (LNA) are required to implement the proposed integrated Rotman lens architecture. A unique solution presented in this thesis is the novel Band Pass Distributed Amplifier (BPDA) topology. In this new topology, by short circuiting the line terminations in a Conventional Distributed Amplifier (CDA), standing waves are created in its artificial transmission lines. Conventionally, standing waves are strongly avoided by carefully matching these lines to 50 ?? in order to prevent instability of the amplifier. This causes that a large portion of the signal be absorbed in these resistive terminations. In this thesis, it is shown that due to presence of highly lossy parasitics of CMOS transistor at the mmW the amplifier stability is inherently achieved. Moreover, by eliminating these lossy and noise terminations in the CDA, the amplifier gain is boosted and its noise figure is reduced. In addition, a considerable decrease in the number of elements enables low power realization of many amplifiers in a small chip area. Using the lumped element model of the transistor, the transfer function of a single stage BPDAs is derived and compared to its conventional counter part. A methodology to design a single stage BPDA to achieve all the design goals is presented. Using the presented design guidelines, amplifiers for different mmW frequencies have been designed, fabricated and tested. Using only 4 transistors, a 60 GHz amplifier is fabricated on a very small chip area of 0.105 mm2 by a low-cost 130 nm CMOS technology. A peak gain of 14.7 dB and a noise figure of 6 dB are measured for this fabricated amplifier. oreover, it is shown that by further circuit optimization, high gain amplification can be realized at frequencies above the cut-off frequency of the transistor. Simulations show 32 and 28 dB gain can be obtained by implementing only 6 transistors using this CMOS technology at 60 and 77 GHz. A 4-stage 85 GHz amplifier is also designed and fabricated and a measured gain of 10 dB at 82 GHz is achieved with a 3 dB bandwidth of 11 GHz from 80 to 91 GHz. A good agreement between the simulated and measured results verifies the accuracy of the design procedure. In addition, a multi-stage wide-band BPDA has been designed to show the ability of the proposed topology for design of wide band mmW amplifiers using the CMOS technology. Simulated gain of 20.5 dB with a considerable 3 dB bandwidth of 38 GHz from 30 to 68 GHz is achieved while the noise figure is less than 6 dB in the whole bandwidth. An amplifier figure of merit is defined in terms of gain, noise figure, chip area, band width and power consumption. The results are compared to those of the state of the art to demonstrate the advantages of the proposed circuit topology and presented design techniques. Finally, a Rotman lens is designed and optimized by choosing a very small Focal Lens Ratio (FL), and a high measured efficiency of greater than 30% is achieved while the lens dimensions are less than 6 mm. The lens is designed and implemented using a low cost Alumina substrate and conventional microstrip lines to ease its integration with the active parts of the system.

Το αντικείμενο της παρούσης διπλωματικής επικεντρώνεται στη σχεδίαση ανάπτυξη και μέτρηση κυκλώματος κάτω μεταλλάκτη (down converter) συχνότητας στην περιοχή 1 έως 6 GHz. Η αρχιτεκτονική περιλαμβάνει ενισχυτή χαμηλού θορύβου (LNA) κατανεμημένης τοπολογίας (distributed amplifier), μίκτη καθώς και ενισχυτές και φίλτρα στην ενδιάμεση συχνότητα. Ο σχεδιασμός συνοδεύεται από μετρήσεις όπου και διαπιστώνεται η σύγκλιση με τα αποτελέσματα εντατικών εξομοιώσεων. Κύρια εργαλεία του σχεδιασμού απετέλεσαν κυκλωματικοί και ηλεκτρομαγνητικοί εξομοιωτές. / The object of this thesis focuses on design development and measurement down converter circuit in the frequency range 1 to 6 GHz. The architecture includes low noise amplifier (LNA) Distributed topology (distributed amplifier), mixer and amplifiers and filters in intermediate frequency. The design is accompanied by measurements and found where the convergence of the results of intensive simulations. Main tools of design were kyklomatikoi and electromagnetic simulators.

Thesis (MEng)--Stellenbosch University, 2015. / ENGLISH ABSTRACT: This thesis presents the design, construction and measurement of two wide-band LNA’s for the SKA-Mid range (350-1200 MHz). The first wide-band LNA involves the investigation of classic low noise amplifier techniques, which includes basic noise theory, stability analysis, feedback design and the development of sophisticated matching techniques for ultra wide-band performance. Final measurements show a flat gain response equal to 19 dB, with a noise figure of 1.5 dB and an output return loss of 10 dB across the entire bandwidth. A multi-path cascading concept is introduced for the second low noise amplifier design, which aims to connect two single frequency amplifiers in parallel to operate from 500 to 700 MHz. The design process involves several optimization schemes to realise the matching networks for the cascaded topology and the noise performance of the device was confirmed by using multi-port noise theory. The prototype presents significant bandwidth improvements compared to a single frequency LNA design. Excellent agreement between the simulation and measurement were obtained with a flat gain response of 20 dB across a 2:1 bandwidth, with a low noise figure of 0.95 dB and an output return loss of 13 dB across the operation bandwidth of 400 to 800 MHz. / AFRIKAANSE OPSOMMING: Hierdie tesis behandel die ontwerp, konstruksie en meting van twee wyeband laeruis versterkers vir die SKA - Mid reeks (350–1200 MHz). Die eerste wyeband laeruis versterker, ondersoek klassieke laeruis versterker tegnieke wat insluit basiese ruisteorie, stabiliteit analise, terugvoerontwerp en die ontwikkeling van gevorderde aanpassingstegnieke vir ultra wyeband werkverrigting. Finale metings het ’n plat aanwins van 19 dB, met ’n ruisfiguur van 1.5 dB en ’n uittree-refleksie koëffisiënt van -10 dB oor die hele bandwydte vertoon. ’n Multi-pad konsep word bekend gestel vir die tweede laeruis versterker. Die ontwerp het twee enkel frekwensie laeruis versterkers in parallel verbind om vanaf 500 tot 700 MHz te werk. Die ontwerp proses bevat verskeie optimalisering skemas om die aanpassings netwerke vir die kaskade topologie te realiseer. Die ruissyfer van die versterker is bevestig deur die gebruik van multi-pad ruisteorie. Die prototipe het beduidende bandwydte verbeterings vertoon in vergelyking met ’n enkel frekwensie versterker ontwerp. ’n Uitstekende ooreenkoms tussen die simulasie en meting was verkry met ’n plat aanwins van 20 dB oor ’n 2:1 bandwydte, met ’n laeruisfiguur van 0.95 dB en ’n uittree-refleksie koëffisiënt van -13 dB oor die bandwydte van 400-800 MHz.

O presente trabalho tem por objetivo fornecer o embasamento teórico para o projeto de um amplificador de baixo ruído (LNA – Low Noise Amplifier) em tecnologia CMOS que opere em mais de uma faixa de frequência, de modo a permitir seu uso em receptores multibanda e de banda larga. A base teórica que este trabalho abrange desde a revisão bibliográfica do assunto em questão, passando pela análise dos modelos de transistores para alta-frequência, pelo estudo das especificações deste bloco e das métricas utilizadas em projetos de circuitos integrados de RF, bem como pela revisão de topologias clássicas existentes. Com os conhecimentos acima adquiridos, foi possível realizar o projeto de um LNA diferencial de banda larga utilizando tecnologia CMOS IBM 130nm, o qual pode ser aplicado ao padrão IEEE 802.22 para rádios cognitivos (CR). O projeto é baseado na técnica de cancelamento de ruído, sendo validado após apresentar efetiva redução de figura de ruído para banda de frequência desejada, com moderado consumo de potência e utilização moderada de área de silício, devido a solução sem o uso de indutores. O LNA banda larga opera em frequências de 50Mhz a 1GHz e apresenta uma figura de ruído abaixo de 4dB, em 90% da faixa, um ganho acima de 12dB, e perda de retorno na entrada e na saída maiores que 12dB. O IIP3 e a frequência de ocorrência de compressão a 1dB com a entrada em 580MHz estão acima de 0dBm e -10dBm respectivamente. Possui consumo de 46,5mWpara fonte de 1,5V e ocupa uma área ativa de apenas 0,28mm x 0,2mm. / This work presents the theoretical basis for the design of a low noise amplifier (LNA) in CMOS technology that operates in more than one frequency band, which enables its use in multi-band and wideband receivers. The theoretical basis that this work will address extends from the literature review on the subject, through the analysis of models of MOS transistors for high frequencies, study of specifications of this block and the metrics used in RF integrated circuit design, as well as the review of existing classical LNA topologies. Based on the knowledge acquired above, the design of a differential wideband LNA is developed using IBM 130nm RF CMOS process, which can be used in IEEE 802.22 Cognitive Radio (CR) applications. The design is based on the noise-canceling technique, with an indutctorless solution, showing that this technique effectively reduces the noise figure over the desired frequency range with moderate power consumption and a moderate utilization of silicon die area. The wideband LNA covers the frequency range from 50 MHz to 1 GHz, achieving a noise figure below 4dB in over 90% of the band of interest, a gain of 11dB to 12dB, and an input/output return loss higher than -12 dB. The input IIP3 and input P1dB at 580MHz are above 0dB and -10dB, respectively. It consumes 46.5mW from a 1.5V supply and occupies an active area of only 0.056mm2 (0.28mm x 0.2mm).

L'engouement récent pour l'Internet des Objets comme pour les communications satellites entraine des besoins forts en systèmes de communication radio-fréquence (RF) performants. Afin de répondre aux contraintes du marché de masse, ces systèmes doivent être toujours moins encombrants et permettre de maitriser leur consommation de puissance. Ils doivent également être capable d'adresser plusieurs standards de communications et d'ajuster leur performances aux besoins de leur environnement, toujours afin de réduire leur taille et leur consommation. Actuellement, beaucoup de travaux se concentrent sur le développement d'amplificateurs faible-bruits (LNA), le bloc le plus critique des récepteurs RF. L'objectif est donc de concevoir des récepteurs multi-mode et multi-standard. Pour cela, les LNA nécessitent des flots de conception capables de s'adapter aux différentes technologies et topologies afin de répondre à des cahiers des charges très diverses. Cette thèse a donc pour objectif le développement de méthodologies de conception simple et précise pour l'implémentation d'amplificateurs faible bruit.La première méthodologie présentée est dédiée à l'implémentation de LNA en technologie COTS pour des applications spatiales. Ce LNA présente une adaptation large-bande pour adresser plusieurs standards. Il a été conçu pour faire partie d'un récepteur RF dédié aux nano-satellites. Ce dernier a donc fait l'objet d'une étude préliminaire afin de déterminer le cahier des charges à partir des normes des standards visés.La seconde méthodologie est dédiée à l'implémentation de LNA en technologie CMOS pour n'importe quelle type d'applications. Cette méthodologie est d'abord présentée au travers de topologies simples, puis appliquée à un LNA sans inductances à forte linéarité. Cette méthodologie permet notamment de comparer les topologies mais également les technologies CMOS, même les plus avancées telle que la 28 nm FDSOI.Enfin le LNA sans inductances est rendu reconfigurable pour adresser plusieurs standards tout en gardant le dimensionnement optimum obtenu par la méthodologie présentée précédemment. En effet les tailles et polarisation de chaque transistor sont contrôlées numériquement afin d'adapter les performances du LNA à un standard donné. De plus, l'étude de filtres de type N-path combinés au LNA proposé permet d'étendre encore la linéarité du circuit / The recent enthusiasm for the Internet of Objects as well as for satellite communications leads to the need for high-performance radio-frequency (RF) communication systems. In order to meet the constraints of the mass market, these systems must be compact and be as low power as possible. Beside, they are expected to address multiple communication standards and to adjust their performance to the environment, still in order to reduce the size and the power consumption. Currently, many works focus on the development of low-noise amplifiers (LNA), the most critical block of RF receivers. To address this purpose, the goal is to design multi-mode and multi-standard receivers. Hence, LNAs require design flows that can adapt to the different technologies and topologies in order to meet any given set of specifications. This thesis aims at the development of simple and accurate design methodologies for the implementation of low-noise amplifiers.The first proposed methodology is dedicated to the implementation of a LNA in COTS technology for spatial applications. This LNA offers a broadband matching to address several standards. It is designed to be part of an RF receiver for nano-satellites. Thus, the latter is first studied in order to determine the specifications based on the standards of the targeted applications.The second methodology is dedicated to the implementation of LNAs in CMOS technology for any kind of applications. This methodology is first illustrated with basic topologies and then applied to an highly linear inductorless LNA. The design methodology also enables a fair comparison between the topologies and also CMOS technologies, even the most advanced ones such as the 28 nm FDSOI.Finally, reconfigurability is added to the inductorless LNA, to address several standards while retaining the optimum sizing given by the previously introduced methodology. Indeed, the size and polarization of each transistor are digitally controlled in order to adjust the LNA's performance to a given standard. Furthermore, the study of N-path filters combined with the proposed LNA is explored to improve the linearity of the circuit.

Compared to current single-standard radio solutions, multi-standard radio transceivers enable higher integration, backward compatibility and save power, area and cost. The primary bottleneck in their realization is the development of high-performance frequency-reconfigurable RF circuits. To that end, this research introduces several CMOS-integrated, transformer-based reconfigurable circuit techniques whose effectiveness is validated through measurements of designed transceiver front-end low-noise (LNA) and power amplifier (PA) prototypes. In the first part, the use of high figure-of-merit phase-change (PC) based RF switches in the reconfiguration of CMOS LNAs in the receiver front-end is proposed. The first reported demonstration of an integrated, PC-switch based, dual-band (3/5 GHz) reconfigurable CMOS LNA with transformer source degeneration and designed in a 0.13 μm process is presented. In the second part, a frequency-reconfigurable CMOS transformer combiner is introduced that can be reconfigured to have similar efficiencies at widely separated frequency bands. A 65-nm CMOS triple-band (2.5/3/3.5 GHz) PA employing the reconfigurable combiner was designed. In the final part of this work, the use of transformer coupled-resonators in mm-wave LNA designs for 28 GHz bands was investigated. To cover contiguous and/or widely-separated narrowband channels of the emerging 5G standards, a 65-nm CMOS 24.9-32.7 GHz wideband multi-mode LNA using one-port transformer coupled-resonators was designed. Finally, a 25.1-27.6 GHz tunable-narrowband digitally-calibrated merged LNA-vector modulator design employing transformer coupled-resonators is presented that proposes a compact, differential quadrature generation scheme for phased-array architectures.

O presente trabalho tem por objetivo fornecer o embasamento teórico para o projeto de um amplificador de baixo ruído (LNA – Low Noise Amplifier) em tecnologia CMOS que opere em mais de uma faixa de frequência, de modo a permitir seu uso em receptores multibanda e de banda larga. A base teórica que este trabalho abrange desde a revisão bibliográfica do assunto em questão, passando pela análise dos modelos de transistores para alta-frequência, pelo estudo das especificações deste bloco e das métricas utilizadas em projetos de circuitos integrados de RF, bem como pela revisão de topologias clássicas existentes. Com os conhecimentos acima adquiridos, foi possível realizar o projeto de um LNA diferencial de banda larga utilizando tecnologia CMOS IBM 130nm, o qual pode ser aplicado ao padrão IEEE 802.22 para rádios cognitivos (CR). O projeto é baseado na técnica de cancelamento de ruído, sendo validado após apresentar efetiva redução de figura de ruído para banda de frequência desejada, com moderado consumo de potência e utilização moderada de área de silício, devido a solução sem o uso de indutores. O LNA banda larga opera em frequências de 50Mhz a 1GHz e apresenta uma figura de ruído abaixo de 4dB, em 90% da faixa, um ganho acima de 12dB, e perda de retorno na entrada e na saída maiores que 12dB. O IIP3 e a frequência de ocorrência de compressão a 1dB com a entrada em 580MHz estão acima de 0dBm e -10dBm respectivamente. Possui consumo de 46,5mWpara fonte de 1,5V e ocupa uma área ativa de apenas 0,28mm x 0,2mm. / This work presents the theoretical basis for the design of a low noise amplifier (LNA) in CMOS technology that operates in more than one frequency band, which enables its use in multi-band and wideband receivers. The theoretical basis that this work will address extends from the literature review on the subject, through the analysis of models of MOS transistors for high frequencies, study of specifications of this block and the metrics used in RF integrated circuit design, as well as the review of existing classical LNA topologies. Based on the knowledge acquired above, the design of a differential wideband LNA is developed using IBM 130nm RF CMOS process, which can be used in IEEE 802.22 Cognitive Radio (CR) applications. The design is based on the noise-canceling technique, with an indutctorless solution, showing that this technique effectively reduces the noise figure over the desired frequency range with moderate power consumption and a moderate utilization of silicon die area. The wideband LNA covers the frequency range from 50 MHz to 1 GHz, achieving a noise figure below 4dB in over 90% of the band of interest, a gain of 11dB to 12dB, and an input/output return loss higher than -12 dB. The input IIP3 and input P1dB at 580MHz are above 0dB and -10dB, respectively. It consumes 46.5mW from a 1.5V supply and occupies an active area of only 0.056mm2 (0.28mm x 0.2mm).

O presente trabalho tem por objetivo fornecer o embasamento teórico para o projeto de um amplificador de baixo ruído (LNA – Low Noise Amplifier) em tecnologia CMOS que opere em mais de uma faixa de frequência, de modo a permitir seu uso em receptores multibanda e de banda larga. A base teórica que este trabalho abrange desde a revisão bibliográfica do assunto em questão, passando pela análise dos modelos de transistores para alta-frequência, pelo estudo das especificações deste bloco e das métricas utilizadas em projetos de circuitos integrados de RF, bem como pela revisão de topologias clássicas existentes. Com os conhecimentos acima adquiridos, foi possível realizar o projeto de um LNA diferencial de banda larga utilizando tecnologia CMOS IBM 130nm, o qual pode ser aplicado ao padrão IEEE 802.22 para rádios cognitivos (CR). O projeto é baseado na técnica de cancelamento de ruído, sendo validado após apresentar efetiva redução de figura de ruído para banda de frequência desejada, com moderado consumo de potência e utilização moderada de área de silício, devido a solução sem o uso de indutores. O LNA banda larga opera em frequências de 50Mhz a 1GHz e apresenta uma figura de ruído abaixo de 4dB, em 90% da faixa, um ganho acima de 12dB, e perda de retorno na entrada e na saída maiores que 12dB. O IIP3 e a frequência de ocorrência de compressão a 1dB com a entrada em 580MHz estão acima de 0dBm e -10dBm respectivamente. Possui consumo de 46,5mWpara fonte de 1,5V e ocupa uma área ativa de apenas 0,28mm x 0,2mm. / This work presents the theoretical basis for the design of a low noise amplifier (LNA) in CMOS technology that operates in more than one frequency band, which enables its use in multi-band and wideband receivers. The theoretical basis that this work will address extends from the literature review on the subject, through the analysis of models of MOS transistors for high frequencies, study of specifications of this block and the metrics used in RF integrated circuit design, as well as the review of existing classical LNA topologies. Based on the knowledge acquired above, the design of a differential wideband LNA is developed using IBM 130nm RF CMOS process, which can be used in IEEE 802.22 Cognitive Radio (CR) applications. The design is based on the noise-canceling technique, with an indutctorless solution, showing that this technique effectively reduces the noise figure over the desired frequency range with moderate power consumption and a moderate utilization of silicon die area. The wideband LNA covers the frequency range from 50 MHz to 1 GHz, achieving a noise figure below 4dB in over 90% of the band of interest, a gain of 11dB to 12dB, and an input/output return loss higher than -12 dB. The input IIP3 and input P1dB at 580MHz are above 0dB and -10dB, respectively. It consumes 46.5mW from a 1.5V supply and occupies an active area of only 0.056mm2 (0.28mm x 0.2mm).

Esta dissertação apresenta o projeto de um amplificador de baixo ruído (LNA) para aplicação em 2,4 GHz na tecnologia CMOS 0,35 µm. A metodologia baseia-se na obtenção das dimensões dos dispositivos do circuito considerando o consumo de potência e o desempenho em relação ao ruído. Os resultados mostram que a metodologia implementada é eficaz no projeto de um LNA quando se comparam os resultados obtidos nos cálculos com os resultados obtidos no simulador. A expressão de corrente que considera canal curto impõe maior precisão nos resultados, pois se aplica o ajuste de curva com a curva de corrente obtida pelo simulador. Isto permite maior precisão nos resultados dos cálculos de ruído. O fluxo do projeto baseia-se na implementação de dispositivos ideais obtidos de projeto com o propósito de fazer-se comparações dos resultados de cálculos com as simulações, então, usa-se dispositivos reais e ajusta-se o circuito para encontrar melhores desempenhos quanto às especificações. Os resultados mostram a necessidade de ajuste do circuito quando inserido o modelo do indutor para que se consiga desempenhos próximos dos obtidos inicialmente. Em seguida, realiza-se o layout do circuito e sua extração parasitária para fins de fabricação. Verifica-se que a metodologia apresentada é capaz de direcionar a um projeto de um LNA na tecnologia com resultados finais satisfatórios de ganho, ruído e consumo. Assim os resultados esperados são 14,66 dB de ganho, 1,9 dB de fator de ruído e 2,99 mA de consumo de corrente (9,87 mW em 3,3 V de alimentação) ambos no primeiro estágio. / This work presents the design of a low-noise amplifier (LNA) for application at 2.4 GHz using CMOS 0.35 µm technology. The methodology is based on obtaining the dimensions of the devices taking into account of power consumption and performance on noise. Results show that the implemented methodology is efficient in the design of LNAs when it compares results obtained by calculation and simulation. The expression of current that considers short-channel effects increases the precision of results because curve fitting is applied with the current of the simulator. This permits precision on the results of the noise calculation. The design-flow firstly bases on implementation of ideal devices obtained by design on purposes of doing comparisons between calculated and simulated results, then real devices is used and the circuit is fixed to find better performance regarding the specifications. The results showed the necessity of adjusts in the circuit when the inductor is inserted to reach a closer initial performance. Afterwards, the layout of the circuit and its parasitic extraction are worked out for purposes of fabrication. It is verified that this methodology is capable of directing to the design of LNAs using the proposed technology with satisfactory final results of gain, noise and power consumption. Therefore, the expected results are 14,66 dB of gain, 1,9 dB of noise figure, 2,99 mA of current consumption (9,87 mW within 3.3 V of supply voltage) both of them at first stage.