Low-density parity-check codes have recently received much attention because of their excellent performance and the availability of a simple iterative decoder. The decoder, however, requires large amounts of memory, which causes problems with memory consumption. We investigate a new decoding scheme for low density parity check codes to address this problem. The basic idea is to define a reliability measure and a threshold, and stop updating the messages for a bit whenever its reliability is higher than the threshold. We also consider some modifications to this scheme, including a dynamic threshold more suitable for codes with cycles, and a scheme with soft thresholds which allow the possibility of removing a decision which have proved wrong. By exploiting the bits different rates of convergence we are able to achieve an efficiency of up to 50% at a bit error rate of less than 10^-5. The efficiency should roughly correspond to the power consumption of a hardware implementation of the algorithm.

ITC/USA 2014 Conference Proceedings / The Fiftieth Annual International Telemetering Conference and Technical Exhibition / October 20-23, 2014 / Town and Country Resort & Convention Center, San Diego, CA / In some flight test scenarios the telemetry link is noise limited at long slant ranges or during signal fade events caused by antenna pattern nulls. In these situations, a mitigation technique such as forward error correction (FEC) can add several decibels to the link margin. The particular FEC code discussed in this paper is a variant of a low-density parity check (LDPC) code and is coupled with SOQPSK modulation in the hardware tested. This paper will briefly cover lab testing of the flight-ready hardware then present flight test results comparing a baseline uncoded telemetry link with a LDPC-coded telemetry link. This is the first known test dedicated to this specific FEC code in a real-world test environment with flight profile tailored to assess the viability of an LDPC-coded telemetry link.

At a time where almost 1.75 billion people around the world use the Internet on a regular basis, optical communication over optical fibers that is used in long distance and high demand applications has to be capable of providing higher communication speed and re-liability. In recent years, strong demand is driving the dense wavelength division multip-lexing network upgrade from 10 Gb/s per channel to more spectrally-efficient 40 Gb/s or 100 Gb/s per wavelength channel, and beyond. The 100 Gb/s Ethernet is currently under standardization, and in a couple of years 1 Tb/s Ethernet is going to be standardized as well for different applications, such as the local area networks (LANs) and the wide area networks (WANs). The major concern about such high data rates is the degradation in the signal quality due to linear and non-linear impairments, in particular polarization mode dispersion (PMD) and intrachannel nonlinearities. Moreover, the higher speed transceivers are expensive, so the alternative approaches of achieving the required rates is preferably done using commercially available components operating at lower speeds.In this dissertation, different LDPC-coded modulation techniques are presented to offer a higher spectral efficiency and/or power efficiency, in addition to offering aggregate rates that can go up to 1Tb/s per wavelength. These modulation formats are based on the bit-interleaved coded modulation (BICM) and include: (i) three-dimensional LDPC-coded modulation using hybrid direct and coherent detection, (ii) multidimensional LDPC-coded modulation, (iii) subcarrier-multiplexed four-dimensional LDPC-coded modulation, (iv) hybrid subcarrier/amplitude/phase/polarization LDPC-coded modulation, and (v) iterative polar quantization based LDPC-coded modulation.

In this thesis, we present a space-time coded system which achieves high through- put and good performance with low processing delay using low-complexity detection and decoding. Initially, Hamming codes are used in a simple interleaved bit-mapped coded modulation structure (BMCM). This is concatenated with Alamouti's or- thogonal space-time block codes. The good performance achieved by this system indicates that higher throughput is possible while maintaining performance. An analytical bound for the performance of this system is presented. We also develop a class of low density parity check codes which allows flexible "throughput versus performance" tradeoffs. We then focus on a Rate 2 quasi-orthogonal space-time block code structure which enables us to achieve an overall throughput of 5.6 bits/symbol period with good performance and relatively simple decoding using iterative parallel interference cancellation. We show that this can be achieved through the use of a bit-mapped coded modulation structure using parallel short low density parity check codes. The absence of interleavers here reduces processing delay significantly. The proposed system is shown to perform well on flat Rayleigh fading channels with a wide range of normalized fade rates, and to be robust to channel estimation errors. A comparison with bit-interleaved coded modulation is also provided (BICM).

Low-density parity-check (LDPC) codes are a class of easily decodable error-correcting codes. Published parallel LDPC decoders demonstrate high throughput and low energy-per-bit but require a lot of silicon area. Decoders based on digit-online arithmetic (processing several bits per fundamental operation) process messages in a digit-serial fashion, reducing the area requirements, and can process multiple frames in frame-interlaced fashion. Implementations on Field-Programmable Gate Array (FPGA) are usually power- and area-hungry, but provide flexibility compared with application-specific integrated circuit implementations. With the penetration of mobile devices in the electronics industry the power considerations have become increasingly important. The power consumption of a digit-online decoder depends on various factors, like input log-likelihood ratio (LLR) bit precision, signal-to-noise ratio (SNR) and maximum number of iterations. The design is implemented on an Altera Stratix IV GX EP4SGX230 FPGA, which comes on an Altera DE4 Development and Education Board. In this work, both parallel and digit-online block LDPC decoder implementations on FPGAs for WiMAX 576-bit, rate-3/4 codes are studied, and power measurements from the DE4 board are reported. Various components of the system include a random-data generator, WiMAX Encoder, shift-out register, additive white Gaussian noise (AWGN) generator, channel LLR buffer, WiMAX Decoder and bit-error rate (BER) Calculator. The random-data generator outputs pseudo-random bit patterns through an implemented linear-feedback shift register (LFSR). Digit-online decoders with input LLR precisions ranging from 6 to 13 bits and parallel decoders with input LLR precisions ranging from 3 to 6 bits are synthesized in a Stratix IV FPGA. The digit-online decoders can be clocked at higher frequency for higher LLR precisions. A digit-online decoder can be used to decode two frames simultaneously in frame-interlaced mode. For the 6-bit implementation of digit-online decoder in single-frame mode, the minimum throughput achieved is 740 Mb/s at low SNRs. For the case of 11-bit LLR digit-online decoder in frame-interlaced mode, the minimum throughput achieved is 1363 Mb/s. Detailed analysis such as effect of SNR and LLR precision on decoder power is presented. Also, the effect of changing LLR precision on max clock frequency and logic utilization on the parallel and the digit-online decoders is studied. Alongside, power per iteration for a 6-bit LLR input digit-online decoder is also reported.

Low-density parity check (LDPC) codes are very popular among error correction codes because of their high-performance capacity. Numerous investigations have been carried out to analyze the performance and simplify the implementation of LDPC codes. Relatively slow convergence of iterative decoding algorithm affects the performance of LDPC codes. Faster convergence can be achieved by reducing the number of iterations during the decoding process. In this thesis, a new approach for faster convergence is suggested by choosing a systematic parity check matrix that yields lowest Second Smallest Eigenvalue Modulus (SSEM) of its corresponding Laplacian matrix. MATLAB simulations are used to study the impact of eigenvalues on the number of iterations of the LDPC decoder. It is found that for a given (n, k) LDPC code, a parity check matrix with lowest SSEM converges quickly as compared to the parity check matrix with high SSEM. In other words, a densely connected graph that represents the parity check matrix takes more iterations to converge than a sparsely connected graph.

In the recent years, the exponential Internet traffic growth projections place enormous transmission rate demand on the underlying information infrastructure at every level, from the long haul submarine transmission to optical metro networks. In recent years, optical transmission at 100 Gb/s Ethernet date rate has been standardized by ITU-T and IEEE forums and 400Gb/s and 1Tb/s rates per DWDM channel systems has been under intensive investigation which are expected to be standardized within next couple of years.To facilitate the implementation of 400GbE and 1TbE technologies, the new advanced modulation scheme combined with advanced forward error correction code should be proposed. Instead of using traditional QAM, we prefer to use some other modulation techniques, which are more suitable for current coherent optical transmission systems and can also deal with the channel impairments. In this dissertation, we target at improving the channel capacity by designing the new modulation formats. For the first part of the dissertation, we first describe the optimal signal constellation design algorithm (OSCD), which is designed by placing constellation points onto a two dimensional space. Then, we expand the OSCD onto multidimensional space and design its corresponding mapping rule. At last, we also develop the OSCD algorithm for different channel scenario in order to make the constellation more tolerant to different channel impairments. We propose the LLR-OSCD for linear phase noise dominated channel and NL-OSCD for nonlinear phase noise dominated channel including both self-phase modulation (SPM) and cross-phase modulation (XPM) cases. For the second part of the dissertation, we target at probability shaping of the constellation sets (non-uniform signaling). In the conventional data transmission schemes, the probability of each point in a given constellation is transmitted equally likely and the number of constellation sets is set to 2!. If the points with low energy are transmitted with larger probability then the others with large energy, the non- uniform scheme can achieve higher energy efficiency. Meanwhile, this scheme may be more suitable for optical communication because the transmitted points with large probabilities, which have small energy, suffer less nonlinearity. Both the Monte Carlo simulations and experiment demonstration of both OSCD and non-uniform signaling schemes indicate that our proposed signal constellation significantly outperforms QAM, IPQ, and sphere-packing based signal constellations.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2009. / ENGLISH ABSTRACT: Low earth orbit (LEO) satellite communication presents a unique environment which inherently di ers from most other communication channels. Due to the varying orbital patterns of LEO satellites the link exhibits varying link margins. Limited communication time windows need to be optimised to maximise the volumetric data throughput. Large coding gains can be obtained by the implementation of forward error correction codes. This thesis presents a means for optimising the data throughput of LEO satellite communication through the implementation of a mission speci c error control strategy. Low density parity check (LDPC) codes are versatile and present good error performances at many di erent code rates and block lengths. With power limitations on the space segment and remote ground stations, hardware utilisation e ciency must be optimised to reduce power consumption. In response to this requirement, this thesis evaluates various algorithms for LDPC decoders. An iterative LDPC decoder, implementing an approximation algorithm, is presented as a low complexity solution with good error performance. The proposed solution provides a very good balance between required hardware complexity and coding performance. It was found that many parameters of the decoders and codes can be altered to allow the implementation of these codes in systems with varying memory and processing capabilities. / AFRIKAANSE OPSOMMING: Kommunikasiekanale van satelliete met lae wentelbane, bied 'n unieke omgewing wat inherent verskil van meeste ander kommunikasiekanale. As gevolg van veranderende wentelbaanpatrone, vertoon die kanaal 'n wisselende foutgedrag. Kommunikasievensters is beperk en moet geoptimeer word om die totale deurset van die stelsel te maksimeer. Groot koderingswinste kan verkry word deur die implementering van foutkorreksie kodes. Hierdie tesis voorsien 'n metode om die datadeurset van satelliete met lae wentelbaan te optimeer, deur middel van implementering van 'n missie-spesi eke foutbeheer strategie. Lae digtheid pariteit toetskodes (LDPC) is veelsydige kodes, bied goeie foutbeheer en is doeltre end vir verskillende kodekoerse en bloklengtes. Met drywingsbeperkinge op die ruimtesegment en afgesonderde grondstasies, moet hardeware komponente doeltreffend gebruik word om drywingsverbruik te verminder. Ten einde aan hierdie ontwerpsvereiste te voldoen, evalueer hierdie tesis verskeie LDPC dekodeerderalgoritmes. Deur 'n iteratiewe LDPC dekodeerder met 'n benaderingsalgoritme te implementeer, word 'n oplossing van lae kompleksiteit aangebied, maar wat steeds goeie foutkorreksie eienskappe toon. Die voorgestelde oplossing bied 'n baie goeie balans tussen benodigde hardeware kompleksiteit en koderingsprestasie. Daar is gevind dat heelwat parameters van die dekodeerders en kodes aangepas kan word, ten einde implementering in stelsels met 'n wye verskeidenheid van geheuespasie en verwerkingsvermoëns moontlik te maak.

Thesis (MScEng)--Stellenbosch University, 2012. / ENGLISH ABSTRACT: A collaboration between the Katholieke Universiteit van Leuven (KUL) and Stellenbosch University (SU), resulted in the development of a satellite based platform for use in agricultural sensing applications. This will primarily serve as a test platform for a digitally beam-steerable antenna array (SAA) that was developed by KUL. SU developed all flight - and ground station based hardware and software, enabling ground to flight communications and interfacing with the KUL SAA. Although most components had already been completed at the start of this M:Sc:Eng: project, final systems integration was still unfinished. Modules necessary for communication were also outstanding. This project implemented an automatic repeat and request (ARQ) strategy for reliable file transfer across the wireless link. Channel coding has also been implemented on a field programmable gate array (FPGA). This layer includes an advanced forward error correction (FEC) scheme i.e. a low-density parity-check (LDPC), which outperforms traditional FEC techniques. A flexible architecture for channel coding has been designed that allows speed and complexity trade-offs on the FPGA. All components have successfully been implemented, tested and integrated. Simulations of LDPC on the FPGA have been shown to provide excellent error correcting performance. The prototype has been completed and recently successfully demonstrated at KUL. Data has been reliably transferred between the satellite platform and a ground station, during this event. / AFRIKAANSE OPSOMMING: Tydens ’n samewerkingsooreenkoms tussen die Katholieke Universiteit van Leuven (KUL) en die Universiteit van Stellenbosch (US) is ’n satelliet stelsel ontwikkel vir sensor-netwerk toepassings in die landbou bedryf. Hierdie stelsel sal hoofsaaklik dien as ’n toetsmedium vir ’n digitaal stuurbare antenna (SAA) wat deur KUL ontwikkel is. Die US het alle hardeware en sagteware komponente ontwikkel om kommunikasie d.m.v die SAA tussen die satelliet en ’n grondstasie te bewerkstellig. Sedert die begin van hierdie M:Sc:Ing: projek was die meeste komponente alreeds ontwikkel en geïmplementeer, maar finale stelselsintegrasie moes nog voltooi word. Modules wat kommunikasie sou bewerkstellig was ook nog uistaande. Hierdie projek het ’n ARQ protokol geïmplementeer wat data betroubaar tussen die satelliet en ’n grondstasie kon oordra. Kanaalkodering is ook op ’n veld programmeerbare hekskikking (FPGA) geïmplementeer. ’n Gevorderde foutkorrigeringstelsel, naamlik ’n lae digtheids pariteit toetskode (LDPC), wat tradisionele foutkorrigeringstelsels se doeltreffendheid oortref, word op hierdie FPGA geïmplementeer. ’n Kanaalkoderingsargitektuur is ook ontwikkel om die verwerkingspoed van data en die hoeveelheid FPGA logika wat gebruik word, teenoor mekaar op te weeg. Alle komponente is suksesvol geïmplementeer, getoets en geïntegreer met die hele stelsel. Simulasies van LDPC op die FPGA het uistekende foutkorrigeringsresultate gelewer. ’n Werkende prototipe is onlangs voltooi en suksesvol gedemonstreer by KUL. Betroubare data oordrag tussen die satelliet en die grondstasie is tydens hierdie demonstrasie bevestig.

Le multicast fiable est certainement la solution la plus efficace pour la distribution de contenu via un<br />tres grand nombre (potentiellement des millions) de recepteurs. Dans cette perspective les protocoles<br />ALC et FLUTE, standardises via l'IETF (RMT WG), ont ete adoptes dans 3GPP/MBMS et dans le<br />DVB-H IP-Datacast dans les contextes des reseaux cellulaires 3G.<br />Ce travail se concentre sur le multicast fiable et a comme requis principal le passage l'echelle massif<br />en terme de nombre de clients. Cette these se base sur les solutions proposees via l'IETF RMT WG.<br />Ces protocoles de multicast fiable sont construit autour de plusieurs briques de base que nous avons<br />etudie en detail:<br />* La brique Forward Error Correction (FEC) :<br />Nous examinons la classe de codes grands blocs Low Density Parity Check (LDPC). Nous concevons<br />des derivees de ces codes, et les analysons en detail. Nous en concluons que les codes<br />LDPC et leur implementation ont des performances tres prometteuses, surtout si ils sont utilisees<br />avec des fichiers de taille importante.<br />* La brique controle de congestion :<br />Nous examinons le comportement dans la phase de demarrage de trois protocoles de controle de<br />congestion RLC, FLID-SL, WEBRC. Nous demontrons que la phase de demarrage a un grand<br />impact sur les performances de telechargement.<br />Cette these a aussi plusieurs contributions au niveau applicatif:<br />* Extensions de FLUTE :<br />Nous proposons un mecanisme permettant d'agreger plusieurs fichiers dans le protocole FLUTE.<br />Ceci ameliore les performance de transmission.<br />* Streaming video :<br />Nous proposons SVSoA, une solution de streaming base sur ALC. Cette approche beneficie de<br />tout les avantages de ALC en terme de passage a l'echelle, controle de congestion et corrections<br />d'erreurs.<br /><br />Mots cles : Multicast fiable, FLUTE, ALC, codes correcteur d'erreurs, Forward Error Correction<br />(FEC), Low Density Parity Check (LDPC) Codes, diffusion de contenu