The thesis deals with the design of wireless communication system using Wireless M- Bus, which works in the 169 MHz band. This system is designed to collect data from meters that are not equipped with a radio and have pulse outputs. The thesis describes the Wireless M-Bus standard and the current components of the communication system used by ModemTec. It also describes the selection and design of a suitable hardware implementing the receiver and transmitter modules and the firmware design for these modules. The thesis deals with the parameterization of the transmitter module in order to specify the parameters of the transmitted measured quantity.

abstract: Ultrasound B-mode imaging is an increasingly significant medical imaging modality for clinical applications. Compared to other imaging modalities like computed tomography (CT) or magnetic resonance imaging (MRI), ultrasound imaging has the advantage of being safe, inexpensive, and portable. While two dimensional (2-D) ultrasound imaging is very popular, three dimensional (3-D) ultrasound imaging provides distinct advantages over its 2-D counterpart by providing volumetric imaging, which leads to more accurate analysis of tumor and cysts. However, the amount of received data at the front-end of 3-D system is extremely large, making it impractical for power-constrained portable systems. In this thesis, algorithm and hardware design techniques to support a hand-held 3-D ultrasound imaging system are proposed. Synthetic aperture sequential beamforming (SASB) is chosen since its computations can be split into two stages, where the output generated of Stage 1 is significantly smaller in size compared to the input. This characteristic enables Stage 1 to be done in the front end while Stage 2 can be sent out to be processed elsewhere. The contributions of this thesis are as follows. First, 2-D SASB is extended to 3-D. Techniques to increase the volume rate of 3-D SASB through a new multi-line firing scheme and use of linear chirp as the excitation waveform, are presented. A new sparse array design that not only reduces the number of active transducers but also avoids the imaging degradation caused by grating lobes, is proposed. A combination of these techniques increases the volume rate of 3-D SASB by 4\texttimes{} without introducing extra computations at the front end. Next, algorithmic techniques to further reduce the Stage 1 computations in the front end are presented. These include reducing the number of distinct apodization coefficients and operating with narrow-bit-width fixed-point data. A 3-D die stacked architecture is designed for the front end. This highly parallel architecture enables the signals received by 961 active transducers to be digitalized, routed by a network-on-chip, and processed in parallel. The processed data are accumulated through a bus-based structure. This architecture is synthesized using TSMC 28 nm technology node and the estimated power consumption of the front end is less than 2 W. Finally, the Stage 2 computations are mapped onto a reconfigurable multi-core architecture, TRANSFORMER, which supports different types of on-chip memory banks and run-time reconfigurable connections between general processing elements and memory banks. The matched filtering step and the beamforming step in Stage 2 are mapped onto TRANSFORMER with different memory configurations. Gem5 simulations show that the private cache mode generates shorter execution time and higher computation efficiency compared to other cache modes. The overall execution time for Stage 2 is 14.73 ms. The average power consumption and the average Giga-operations-per-second/Watt in 14 nm technology node are 0.14 W and 103.84, respectively. / Dissertation/Thesis / Doctoral Dissertation Engineering 2019

In the energy-limited wireless sensor node applications, wake-up radios are required to reduce the average power consumption of the node. Energy-detecting receivers are the best fit for such low power operations. This thesis presents the energy-detecting receiver design; challenges; techniques to enhance sensitivity, selectivity; and multi-access operation. Self-mixers instead of the conventional envelope detectors are proposed and proved to be optimal for signal detection. A fully integrated wake-up receiver uses the self-mixer and time-encoded baseband signal processing to provide a sensitivity of -79.1dBm at 434MHz with 420pW of power, providing an 8dB better sensitivity at 10dB lower power consumption compared to the SoA. A novel approach using narrowband interferers as local oscillators will be presented to further enhance sensitivity and selectivity, effectively operating the energy-detector receiver as a direct down-conversion receiver. Additionally, a clockless continuous-time analog correlator will be introduced to enhance the selectivity to wide-band AM interferers. The architecture uses pulse-position-encoded analog signal processing with VCOs as integrators and pulse-controlled relaxation delays; it operates as a code-domain matched filter to de-spread asynchronous wake-up codes. This code-domain matched filtering also provides code-division multiple access (CDMA) for simultaneous wakeups. Additional enhancement in the link can be achieved using directional antennas, providing spatial gain and selectivity. Certain applications can leverage a nearby reflector similar to a Yagi antenna to enhance the directivity. A low power directional backscatter tag is proposed, it uses multiple antennas acting as a reflectarray by configuring constant phase gradients depending on the direction of arrival (DoA) of the signal. Thus, instead of harvesting energy, the same energy and the surrounding environment can be leveraged to enhance functionality (e.g. interferer as LO, using a backscatter tag on a wall) for low power operation. Innovations spanning both system and circuit architectures that leverage the ambient energy and environment to enable power-efficient solutions for next-generation wake-up radios are presented in this work.

<div>With the growing popularity and use of devices under the great umbrella that is the Internet of Things (IoT), the need for devices that are smaller, faster, cheaper and require less power is at an all time high with no intentions of slowing down. This is why many current research efforts are very focused on energy harvesting. Energy harvesting is the process of storing energy from external and ambient sources and delivering a small amount of power to low power IoT devices such as wireless sensors or wearable electronics. A charge pumps is a circuit used to convert a power supply to a higher or lower voltage depending on the specific application. Charge pumps are generally seen in memory design as a verity of power supplies are required for the newer memory technologies. Charge pumps can be also be designed for low voltage operation and can convert a smaller energy harvesting voltage level output to one that may be needed for the IoT device to operate. In this work, an integrated FinFET (Field Effect Transistor) charge pump for low power energy harvesting applications is proposed.</div><div><br></div><div>The design and analysis of this system was conducted using Cadence Virtuoso Schematic L-Editing, Analog Design Environment and Spectre Circuit Simulator tools using the 7nm FinFETs from the ASAP7 7nm PDK. The research conducted here takes advantage of some inherent characteristics that are present in FinFET technologies, including low body effects, and faster switching speeds, lower threshold voltage and lower power consumption. The lower threshold voltage of the FinFET is key to get great performance at lower supply voltages.</div><div><br></div><div>The charge pump in this work is designed to pump a 150mV power supply, generated from an energy harvester, to a regulated 650mV, while supplying 1uA of load current, with a 20mV voltage ripple in steady state (SS) operation. At these conditions, the systems power consumption is 4.85uW and is 31.76% efficient. Under no loading conditions, the charge pump reaches SS operation in 50us, giving it the fastest rise time of the compared state of the art efforts mentioned in this work. The minimum power supply voltage for the system to function is 93mV where it gives a regulated output voltage of 425mV.</div><div><br></div><div>FinFET technology continues to be a very popular design choice and even though it has been in production since Intel's Ivy-Bridge processor in 2012, it seems that very few efforts have been made to use the advantages of FinFETs for charge pump design. This work shows though simulation that FinFET charge pumps can match the performance of charge pumps implemented in other technologies and should be considered for low power designs such as energy harvesting.</div>

The increased interest in massive deployment of wireless sensors and network densification requires more innovation in low-latency communication across multi-hop networks. Moreover, the resource constrained nature of sensor nodes calls for more energy efficient transmission protocols, in order to increase the battery life of said devices. Therefore, it is important to investigate possible technologies that would aid in improving energy efficiency and decreasing latency in wireless sensor networks (WSN) while focusing on application specific requirements. To this end, and based on state of the art Glossy, a low-power WSN flooding protocol, this dissertation introduces two energy efficient, cooperative transmission schemes for low-power communication in WSNs, with the aim of achieving performance gains in energy efficiency, latency and power consumption. These approaches apply several cooperative transmission technologies such as physical layer network coding and transmit beamforming. Moreover, mathematical tools such as convex optimization and game theory are used in order to analytically construct the proposed schemes. Then, system level simulations are performed, where the proposed schemes are evaluated based on different criteria. First, in order to improve over all latency in the network as well as energy efficiency, MF-Glossy is proposed; a communication scheme that enables the simultaneous flooding of different packets from multiple sources to all nodes in the network. Using a communication-theoretic analysis, upper bounds on the performance of Glossy and MF-Glossy are determined. Further, simulation results show that MF-Glossy has the potential to achieve several-fold improvements in goodput and latency across a wide spectrum of network configurations at lower energy costs and comparable packet reception rates. Hardware implementation challenges are discussed as a step towards harnessing the potential of MF-Glossy in real networks, while focusing on key challenges and possible solutions. Second, under the assumption of available channel state information (CSI) at all nodes, centralized and distributed beamforming and power control algorithms are proposed and their performance is evaluated. They are compared in terms of energy efficiency to standard Glossy. Numerical simulations demonstrate that a centralized power control scheme can achieve several-fold improvements in energy efficiency over Glossy across a wide spectrum of network configurations at comparable packet reception rates. Furthermore, the more realistic scenario where CSI is not available at transmitting nodes is considered. To battle CSI unavailability, cooperation is introduced on two stages. First, cooperation between receiving and transmitting nodes is proposed for the process of CSI acquisition, where the receivers provide the transmitters with quantized (e.g. imperfect) CSI. Then, cooperation within transmitting nodes is proposed for the process of multi-cast transmit beamforming. In addition to an analytical formulation of the robust multi-cast beamforming problem with imperfect CSI, its performance is evaluated, in terms of energy efficiency, through numerical simulations. It is shown that the level of cooperation, represented by the number of limited feedback bits from receivers to transmitters, greatly impacts energy efficiency. To this end, the optimization problem of finding the optimal number of feedback bits B is formulated, as a programming problem, under QoS constraints of 5% maximum outage. Numerical simulations show that there exists an optimal number of feedback bits that maximizes energy efficiency. Finally, the effect of choosing cooperating transmitters on energy efficiency is studied, where it is shown that an optimum group of cooperating transmit nodes, also known as a transmit coalition, can be formed in order to maximize energy efficiency. The investigated techniques including optimum feedback bits and transmit coalition formation can achieve a 100% increase in energy efficiency when compared to state of the art Glossy under same operation requirements in very dense networks. In summary, the two main contributions in this dissertation provide insights on the possible performance gains that can be achieved when cooperative technologies are used in low-power wireless networks.

In the recent years, there has been a rapid development of miniature sensor based wearable devices with broad functionality. Some of these devices are designed to function continuously for weeks with a single battery charge, which requires their power usage to be as low as possible. This can be achieved either through circuit optimization, a more powerful battery, or through optimization of the software controlling the device. This thesis presents an approach to the latter option by the means of a power and energy simulator based on the Open Virtual Platform (OVP). Such a tool can simulate the embedded software and predict the power and energy usage of the system. The result of the simulator could be used in combination with other tools to optimize the software implementation of the system and to lower its overall power and energy consumption.

A high-throughput low-power Soft-Output Viterbi decoder designed for the convolutional codes used in the ECMA-368 UWB standard is presented in this thesis. The ultra wide band (UWB) wireless communication technology is supposed to be used in physical layer of the wireless personal area network (WPAN) and next generation Blue Tooth. MB-OFDM is a very popular scheme to implement the UWB system and is adopted as the ECMA-368 standard. To make the high speed data transferred over the channel reappear reliably at the receiver, the error correcting codes (ECC) are wildly utilized in modern communication systems. The ECMA-368 standard uses concatenated convolutional codes and Reed-Solomon (RS) codes to encode the PLCP header and only convolutional codes to encode the PPDU Payload. The Viterbi algorithm (VA) is a popular method of decoding convolutional codes for its fairly low hardware implementation complexity and relatively good performance. Soft-Output Viterbi Algorithm (SOVA) proposed by J. Hagenauer in 1989 is a modified Viterbi Algorithm. A SOVA decoder can not only take in soft quantized samples but also provide soft outputs by estimating the reliability of the individual symbol decisions. These reliabilities can be provided to the subsequent decoder to improve the decoding performance of the concatenated decoder. The SOVA decoder is designed to decode the convolutional codes defined in the ECMA-368 standard. Its code rate and constraint length is R=1/3 and K=7 respectively. Additional code rates derived from the "mother" rate R=1/3 codes by employing "puncturing", including 1/2, 3/4, 5/8, can also be decoded. To speed up the add-compare-select unit (ACSU), which is always the speed bottleneck of the decoder, the modified CSA structure proposed by E.Yeo is adopted to replace the conventional ACS structure. Besides, the seven-level quantization instead of the traditional eight-level quantization is proposed to be used is in this decoder to speed up the ACSU in further and reduce its hardware implementation overhead. In the SOVA decoder, the delay line storing the path metric difference of every state contains the major portion of the overall required memory. A novel hybrid survivor path management architecture using the modified trace-forward method is proposed. It can reduce the overall required memory and achieve high throughput without consuming much power. In this thesis, we also give the way to optimize the other modules of the SOVA decoder. For example, the first K-1 necessary stages in the Path Comparison Unit (PCU) and Reliability Measurement Unit (RMU) are IX removed without affecting the decoding results. The attractiveness of SOVA decoder enables us to find a way to deliver its soft output to the RS decoder. We have to convert bit reliability into symbol reliability because the soft output of SOVA decoder is the bit-oriented while the reliability per byte is required by the RS decoder. But no optimum transformation strategy exists because the SOVA output is correlated. This thesis compare two kinds of the sub-optimum transformation strategy and proposes an easy to implement scheme to concatenate the SOVA decoder and RS decoder under various kinds of convolutional code rates. Simulation results show that, using this scheme, the concatenated SOVA-RS decoder can achieve about 0.35dB decoding performance gain compared to the conventional Viterbi-RS decoder.

In line with the rising demand for smarter solutions and embedded systems, Microelectromechanical systems (MEMS) have gained increasing importance for digital computing devices and Internet-of-Things (IoT) applications, most notably for mobile wearable devices. This achievement is driven by MEMS resonators' inherent properties such as simplicity, sensitivity, reliability, and low power consumption. Hence, they are being explored for ultra-low-power computing machines. Several fundamental digital logic gates, switching, and memory devices have been demonstrated based on MEMS microstructures' static and dynamic behavior. The interest of researchers in using MEMS resonators is due to seeking an alternative approach to circumvent the notable current leakage and power density problems of complementary metal-oxide-semiconductor (CMOS) technology. The continuous miniaturization of CMOS has increased the operating speed and reduces the size of the device. However, this has led to a relative increase in the leakage energy. This drawback in CMOS has renewed the interest of researchers in mechanical digital computations, which can be traced back to the work of Charles Babbage in 1822 on calculating engines. This dissertation presents axially-loaded and coupled-MEMS resonators investigations to demonstrate memory elements and different logic functions. The studies in this dissertation can be categorized majorly into three parts based on the implementation of logic functions using three techniques: electrothermal frequency tunability, electrostatic frequency modulations, and activation/deactivation of the resonant frequency. Firstly, the influence of the competing effects of initial curvature and axial loads on the mechanical behavior of MEMS resonator arches are investigated theoretically to predict the tunability of arches under axial loads. Then, the concept of electrothermal frequency tunability is used to demonstrate fundamental 2-bit logic gates. However, this concept consumes a considerable amount of energy due to the electrothermal technique. Next, the dynamic memory element and combinational logic functions are demonstrated using the concept of electrostatic frequency modulation. Though this approach is energy efficient compared to the electrothermal technique, it does not support the cascadability of MEMS resonator-based logic devices. Lastly, complex multifunctional logic gates are implemented based on selective modes activation and deactivation, resulting in significant improvement in energy efficiency and enabling cascadability of MEMS resonator-based logic devices.

<p>Deep Neural Networks (DNNs) are a class of machine learning algorithms that are widelysuccessful in various computer vision tasks. DNNs filter input images and videos with manyconvolution operations in each layer to extract high-quality features and achieve high ac-curacy. Although highly accurate, the state-of-the-art DNNs usually require server-gradeGPUs, and are too energy, computation and memory-intensive to be deployed on most de-vices. This is a significant problem because billions of mobile and embedded devices that donot contain GPUs are now equipped with high definition cameras. Running DNNs locallyon these devices enables applications such as emergency response and safety monitoring,because data cannot always be offloaded to the Cloud due to latency, privacy, or networkbandwidth constraints.</p> <p>Prior research has shown that a considerable number of a DNN’s memory accesses andcomputation are redundant when performing computer vision tasks. Eliminating these re-dundancies will enable faster and more efficient DNN inference on low-power embedded de-vices. To reduce these redundancies and thereby reduce the energy consumption of DNNs,this thesis proposes a novel Tree-based Unidirectional Neural Network (TRUNK) architec-ture. Instead of a single large DNN, multiple small DNNs in the form of a tree work togetherto perform computer vision tasks. The TRUNK architecture first finds thesimilaritybe-tween different object categories. Similar object categories are grouped intoclusters. Similarclusters are then grouped into a hierarchy, creating a tree. The small DNNs at every nodeof TRUNK classify between different clusters. During inference, for an input image, oncea DNN selects a cluster, another DNN further classifies among the children of the cluster(sub-clusters). The DNNs associated with other clusters are not used during the inferenceof that image. By doing so, only a small subset of the DNNs are used during inference,thus reducing redundant operations, memory accesses, and energy consumption. Since eachintermediate classification reduces the search space of possible object categories in the image,the small efficient DNNs still achieve high accuracy.</p> <p>In this thesis, we identify the computer vision applications and scenarios that are wellsuited for the TRUNK architecture. We develop methods to use TRUNK to improve the efficiency of the image classification, object counting, and object re-identification problems.We also present methods to adapt the TRUNK structure for different embedded/edge ap-plication contexts with different system architectures, accuracy requirements, and hardware constraints.</p> <p>Experiments with TRUNK using several image datasets reveal the effectiveness of theproposed solution to reduce memory requirement by∼50%, inference time by∼65%, energyconsumption by∼65%, and the number of operations by∼45% when compared with existingDNN architectures. These experiments are conducted on consumer-grade embedded systems:NVIDIA Jetson Nano, Raspberry Pi 3, and Raspberry Pi Zero. The TRUNK architecturehas only marginal losses in accuracy when compared with the state-of-the-art DNNs.</p>

The notion of mechanical computation has been revived in the past few years, with the advances of nanofabrication techniques. Although electromechanical devices are inherently slow, they offer zero or very low off-state current, which reduces the overall power consumption compared to the fast complementary-metal-oxide-semiconductor (CMOS) counterparts. This energy efficiency feature is the most crucial requirement for most of the stand-alone battery-operated gadgets, biomedical devices, and the internet of things (IoT) applications, which do not require the fast processing speeds offered by the mainstream CMOS technology. In particular, using Micro-Electro-Mechanical (MEM) resonators in mechanical computing has drawn the attention of the research community and the industry in the last decade as this technology offers low power consumption, reduced circuit complexity compared to conventional CMOS designs, run-time re- programmability and high reliability due to the contactless mode of operation compared to other MEM switches such as micro-relays. In this thesis, we introduce digital circuit design techniques tailored for clamped-clamped beam MEM resonators. The main operation mechanism of these circuit blocks is based on fine-tuning of the resonance frequency of the micro-resonator beam, and the logic function performed by the devices is mainly determined by factors such as input/output terminal arrangement, signal type, resonator operation regime (linear/non-linear), and the operation frequency. These proposed circuits include the major building blocks of any microprocessor such as logic gates, a full adder which is a key block in any arithmetic and logic operation units (ALU), and I/O interface units, including digital to analog (DAC) and analog to digital (ADC) data converters. All proposed designs were first simulated using a finite element software and then the results were experimentally verified. Important aspects such as energy per operation, speed, and circuit complexity are evaluated and compared to CMOS counterparts. In all applications, we show that by proper scaling of the resonator’s dimensions, MHz operation speeds and energy consumption in the range of femto-joules per logic operation are attainable. Finally, we discuss some of the challenges in using MEM resonators in digital circuit design at the device level and circuit level and propose solutions to tackle some of them.