Dans le but d’intégrer des technologies CMOS avec des cellules mémoires, une seule étape de siliciuration de tous les contacts permettrait de diminuer les couts et de faciliter l’intégration. La formation de siliciure simultanément au niveau des sources, drains et grilles avec du NiPt(10 at.%) est nécessaire pour la technologie FD-SOI parce que cette dernière induit des spécifications exigeantes en ce qui concerne la siliciuration. En effet, le siliciure formé avec le procédé Salicide se doit d’être très fin et stable pour contenir le phénomène de diffusion anormale du Ni qui pourrait être à l’origine de fuites de la jonction. De plus, la réduction des dimensions des cellules mémoires nécessite l’incorporation de dopants d’une manière alternative à l’implantation ionique. L’introduction de dopage au phosphore de manière in-situ pendant le dépôt de silicium nécessite la compréhension de l’interaction du siliciure et des dopants. Dans cette étude, différents types de dopage sont étudiés dans des substrats mono et poly-cristallins afin de correspondre aux multiples types de silicium qui sont présents dans les technologies et qui nécessitent une siliciuration. La redistribution du phosphore entraînée par la formation du siliciure est étudiée et discutée à l’aide de caractérisations par sonde atomique tomographique et spectrométrie de masse à ionisation secondaire à temps de vol. De plus, la réaction à l’état solide est étudiée à l’aide de diffraction par rayons-X afin de comprendre l’impact des dopants sur la séquence de phases. Finalement, la redistribution des dopants observée expérimentalement est étayée par des simulations basées sur un modèle par éléments finis / For the purpose of co-integrating the CMOS technology with memory cells, a unique step of silicidation of all the contacts would decrease costs and ease the integration. The simultaneous silicide formation on the source, drain and gate contacts with NiPt(10 at.%) is required for the FD-SOI technology because the latter induces challenging specifications for the silicidation. As a matter of fact, the silicide formed with the Salicide process must be very thin and stable to contain the NiSi piping phenomenon that could lead to junction leakage. Meanwhile, new integration roads and the reduction of the dimensions of the memory cells arise the need of other ways of dopant incorporation as a substitute to ionic implantation. The introduction of phosphorus by in-situ doping during the deposition of silicon requires the understanding of the interaction of silicide and dopants with this configuration. In this study the metallization of phosphorus doped Si is presented. Different doping types are investigated with mono and poly-crystalline substrates in order to match the various silicon layers needing a silicidation and present in the technologies. The phosphorus redistribution occurring during silicide formation is studied and discussed thanks to Atom Probe Tomography and Time-of-Flight Secondary Ion Mass Spectrometry analyses. Moreover, the solid-state reaction is studied thanks to X-Ray diffraction to understand the dopants’ impact on the phase sequence. Finally, the dopant redistribution is analyzed thanks to modeling

Adhesion lithography has been used to pattern nanogaps between two electrodes of the same or different metals onto a substrate. Patterning Al and Ti/Pt bilayer electrodes have been shown to form nanogaps leaving behind relatively consistent nanogaps of less than 12 nm between the electrodes. These nanogaps are formed without the need for adhesion lithography due to the bilayer spontaneously delaminating from the aluminum electrodes, In this study, the stresses in the Ti/Pt bilayer are investigated to determine the amount of stress required for delamination and the properties causing it. The goal is to recreate this stress mechanism in other patterned metals such as Au and Al. Heat cycling is used to induce high stress in other metal electrode combinations in an attempt to induce spontaneous delamination in Al and Au but fails up to 310°C annealing temperature. Theoretical methods are used to determine the stress: searching for an appropriate mathematical model and using finite element analysis in ABAQUS software to create a simulation of the delaminating Ti/Pt bilayer. The stress is found to be caused by the residual stresses in platinum and the high energy e-beam deposition method. An experimental value for the stress and the ability to recreate it in other metals remains elusive.

Photoresist is a light sensitive material whose physical and chemical properties change when exposed to light. Photoresist makes it possible to transfer the image of a circuit pattern directly onto a substrate. The first part of this work deals with developing a photo process using AZ 1518 and AZ P4330 positive resists on SiC substrate. The aim was to determine the optimal spin parameters, softbake time, and exposure time for these resists matching their thickness. AZ 1518 process was developed for a 1.76 um thickness and AZ P4330 for 4.3 um thickness. With the parameters obtained the resist had about 5% of difference in thickness across a wafer surface. The absence of practical wet chemical etching of SiC is the reason for the study of dry, plasma etching of SiC in this thesis. There is an interest in photoresist as an etch mask because it is cheap, easy to deposit, pattern and remove. However its ability to mask etching of materials with high bond strength like SiC is limited. This work examines its selectivity under various etching parameters and determines the effect of increase in the RF power on selectivity, SiC etch rate and photoresist etch rate.

In this dissertation a simplified nondimensional approach for the thermal analysis of power hybrid circuits is presented. The new technique uses only the metallization and the substrate as layers and represents everything below the substrate by an external thermal resistance (expressed as an equivalent convective heat transfer coefficient, h). In this study, the impact on thermal management of thick film metallization and copper cladding on alumina, aluminum nitride, and beryllia ceramic substrates is compared. The thermal conductivity of the substrate material, the thickness of the copper layer, the thermal resistance of the heat sink system, the size of the device, and the spacing between two heat dissipating devices are considered. The model results show that increasing the thickness of the copper layer can significantly decrease the device temperatures on alumina but may increase temperatures on high thermal conductivity substrates. Moreover, the model results show that increasing the thickness of the copper layer requires that the devices be placed farther apart to prevent thermal interaction. The results also demonstrate that the external heat sink resistance can have a significant impact on the heat flow paths and temperatures in the substrate. As the external resistance increases, the spacing required to prevent thermal interaction also increases. In addition to the above, a series of experiments were conducted on various hybrid circuits samples for a low and high heat sink external resistance, i.e., large and small convective heat transfer coefficients, respectively. These samples were constructed using thick film resistors as heat sources on alumina and beryllia substrates. The temperature rise was measured using infrared thermal imaging technique. These experimental results were compared to results predicted by the thermal model. In general, the model underpredicts or overpredicts the experimental temperature rise by 0-2 ·C and the agreement is within the experimental uncertainty of ±2°C. / Ph. D.

Layout parasitics result from electromagnetic interaction between circuit metalizations used to connect devices on the hybrid circuit. Three linked programs have been written to calculate the capacitance and inductance between circuit metalizations. (1) XT Editor A user friendly hybrid circuit layout editor which enables the user to create circuit layouts and select portions of the circuit for parasitic computation. (2) XT Mesh A two and three dimensional fully automatic mesh generator. The mesh generator combines the quadrant/octant subdivision method and Watson's algorithm in a four step process. Initial triangulations are created and cell compatibility is ensured using an alternating initial mesh scheme. This method produces substantial time savings by avoiding the use of data tree structures and stringent cell size rules. (3) XT Field Solver A two and three dimensional finite element quasi-TEM solver which calculates the capacitance and inductance between circuit metalizations. / Master of Science

The purpose of this research is to develop an understanding of Multichip Modules, (MCMs), more specific those fabricated with a Low Temperature Co-fireable Ceramic (L TCC) tape systems. The study will consist of designing, processing, and testing two generic MCM test patterns. The effects on signal propagation caused by vias and wire bonds, crosstalk for surface and embedded transmission lines, crosstalk between vias, effects of bends in transmission lines are studied and discussed in this work. Time Domain and Frequency Domain measurements are performed and presented in this thesis work for electrical characterization of MCM structures using L TCC systems / Master of Science

ALICE (A Large Ion Collider Experiment) is the heavy-ion experiment at the Large Hadron Collider (LHC) at CERN. As an important part of its upgrade plans, the ALICE experiment will schedule the installation of a new Inner Tracking System (ITS) during the Long Shutdown 2 (LS2) of the LHC. The new ITS layout will consist of seven concentric layers, ¿ 12.5 Gigapixel camera covering about 10m2 with Monolithic Active Pixel Sensors (MAPS). This choice of technology has been guided by the tight requirements on the material budget of 0.3% X/X0 per layer for the three innermost layers and backed by the significant progress in the field of MAPS in recent years. The technology initially chosen for the ITS upgrade is the TowerJazz 180 nm CMOS Technology. It offers a standard epitaxial layer of 15 - 18 µm with a resistivity between 1 and 5 k¿ cm¿1 and a gate oxide thickness below 4 nm, thus being more robust to Total Ionizing Dose (TID). The main subject of this thesis is to implement a novel digital pixel readout architecture for MAPS. This thesis aims to study this novel readout architecture as an alternative to the rolling-shutter readout. However, this must be investigated through the study of several chip readout architectures during the R&D phase. Another objective of this thesis is the study and characterization of TowerJazz, if it meets the Non-Ionizing Energy Loss (NIEL) and Single Event Effects (SEE) of the ALICE ITS upgrade program. Other goals of this thesis are: ¿ Implementation of the top-down flow for this CMOS process and the design of multiple readouts for different prototypes up to the assembly of a full-scale prototype. xvii Abstract ¿ Characterization of the radiation hardness and SEE of the chips submitted to fabrication. ¿ Characterization of full custom designs using analog simulations and the generation of digital models for the simulation chain needed for the verification process. ¿ Implementation and study of different digital readouts to meet the ITS upgrade program in integration time, pixel size and power consumption, from the conceptual idea, production and fabrication phase. Chapter 1 is a brief overview of CERN, the LHC and the detectors complex. The ALICE ITS will be explained, focusing on the ITS upgrade in terms of detector needs and design constraints. Chapter 2 explains the properties of silicon detectors and the detector material and the principles of operation for MAPS. Chapters 3 and 4 describe the ALPIDE prototypes and their readout based on MAPS; this forms the central part of this work, including the multiple families of pixel detectors fabricated in order to reach the final design for the ITS. The ALPIDE3/pALPIDE3B chip, the latest MAPS chip designed, will be explained in detail, as well focusing in the matrix digital readout. In chapter 5 the noise measurements and its characterization are presented including a brief summary of detector response to irradiation with soft X-rays, sources and particle beams. / El sub detector ITS (Inner Tracking System) del detector ALICE (A Large Ion Collider Experiment) es un detector de vértice y es el detector mas cercano al punto de interacción. Se encuentra conformado por 3 tipos de subdetectores, dos capas de pixel de silicio (Silicon Pixel Detectors), 2 capas de acumulación de silicio (Silicon Drift Detectors) y 2 capas de banda de Silicio (Silicon Strip Detectors). La función primaria del ITS es identificar y rastrear las partículas de bajo momentum transversal. El detector ITS en sus dos capas más internas están equipadas con sensores de silicio basados en píxeles híbridos. Para reemplazar esta tecnología de Píxeles, el detector ITS actual será reemplazado por un nuevo detector de una sola tecnología, ampliando su resolución espacial y mejorando el rastreo de trazas. Este nuevo detector constará de siete capas de sensores de píxeles activos monolíticos (MAPS), las cuales deberán satisfacer los requerimientos de presupuesto de materiales y ser tolerantes a mayores niveles de radiación para los nuevos escenarios de incrementos de luminosidad y mayores tasas de colisiones. Los sensores MAPS que integran el sensor de imagen y los circuitos de lectura se encuentran en la misma oblea de silicio, tienen grandes ventajas en una buena resolución de posición y un bajo presupuesto material en términos de bajo coste de producción. TowerJazz ofrece la posibilidad de una cuádruple-WELL aislando los transistores pMOS que se encuentran en la misma nWELL evitando la competencia con el electrodo de recolección, permitiendo circuitos mas complejos y compactos para ser implementados dentro de la zona activa y además posee una capa epitaxial de alta resistividad. Esta tecnología proporciona una puerta de óxido muy delgado limitando el daño superficial por la radiación haciéndolo adecuado para su uso denxiii Resúmen tro del experimento ALICE. En los últimos cuatro años se ha llevado a cabo una intensiva I+D en MAPS en el marco de la actualización del ITS de ALICE. Varios prototipos a pequeña escala se han desarrollado y probado exitosamente con rayos X, fuentes radioactivas y haces de partículas. La tolerancia a la radiación de ALICE ITS es moderada con una tolerancia de irradiación TID de 700 krad y NIEL de 1 × 1013 1 MeV neqcm¿2 , MAPS es una opción viable para la actualización del ITS. La contribución original de esta tesis es la implementación de una nueva arquitectura digital de lectura de píxeles para MAPS. Esta tesis presenta un codificador asíncrono de direcciones (arquitectura basada en la supresión de ceros transmitiendo la dirección de los píxeles excitados denominada PADRE) para la arquitectura ALPIDE, el autor también hizo una contribución significativa en el ensamblaje y veri- ficación de circuitos. PADRE es la principal investigación del autor, basada en un codificador de prioridad jerárquica de cuatro entradas y es una alternativa a la arquitectura de lectura rolling-shutter. Además de los prototipos a pequeña escala, también se han desarrollado prototipos a escala completa a las necesidades del detector ITS (15 mm y 30 mm) empleando un nuevo circuito de lectura basado en la versión personalizada del circuito PADRE. El pALPIDEfs fue el primer prototipo a escala completa y se caracterizó obteniendo un tiempo de lectura de la matriz por debajo de 4 µs y un consumo de energía en el orden de 80 mWcm¿2 . En general, los resultados obtenidos representan un avance significativo de la tecnología MAPS en cuanto al consumo de energía, velocidad de lectura, tiempo de recolección de carga y tolerancia a la radiación. El sensor pALPIDE2 ha demostrado ser una opción muy atractiva para el nuevo detector ITS, satisfaciendo los requerimientos en términos de eficiencia de detección, fake-hit rate y resolución de posición, ya que su rendimiento no puede alcanzarse mediante prototipos basados en la arquitectura de lectura tradicionales como es / El subdetector ITS (Inner Tracking System) del detector ALICE (A Large Ion Collider Experiment) és un detector de vèrtex i és el detector mes proper al punt d'interacció. Es troba conformat per 3 tipus de subdetectors, dues capes de píxel de silici (Silicon Pixel Detectors), 2 capes d'acumulació de silici (Silicon Drift Detectors) i 2 capes de banda de Silici (Silicon Strip Detectors). La funció primària del ITS és identificar i rastrejar les partícules de baix moment transversal. El detector ITS en les seues dues capes més internes estan equipades amb sensors de silici basats en píxels híbrids. Per a reemplaçar aquesta tecnologia de Píxels, el detector ITS actual serà reemplaçat per un nou detector d'una sola tecnologia, ampliant la seua resolució espacial i millorant el rastreig de traces. Aquest nou detector constarà de set capes de sensors de píxels actius monolítics (MAPS), les quals hauran de satisfer els requeriments de pressupost de materials i ser tolerants a majors nivells de radiació per als nous escenaris d'increments de lluminositat i majors taxes de col·lisions. Els sensors MAPS que integren el sensor d'imatge i els circuits de lectura es troben en la mateixa hòstia de silici, tenen grans avantatges en una bona resolució de posició i un baix pressupost material en termes de baix cost de producció. TowerJazz ofereix la possibilitat d'una quàdruple-WELL aïllant els transistors pMOS que es troben en la mateixa nWELL evitant la competència amb l'elèctrode de recol·lecció, permetent circuits mes complexos i compactes per a ser implementats dins de la zona activa i a més posseeix una capa epitaxial d'alta resistivitat. Aquesta tecnologia proporciona una porta d'òxid molt prim limitant el dany superficial per la radiació fent-ho adequat per al seu ús dins de l'- experiment ALICE. En els últims quatre anys s'ha dut a terme una intensiva R+D en MAPS en el marc de l'actualització del ITS d'ALICE. Diversos prototips a petita escala s'han desenvolupat i provat ix Resum reeixidament amb rajos X, fonts radioactives i feixos de partícules. La tolerància a la radiació d'ALICE ITS és moderada amb una tolerància d'irradiació TID de 700 krad i NIEL d'1× 1013 1MeV neqcm¿2 , MAPS és una opció viable per a l'actualització del ITS. La contribució original d'aquesta tesi és la implementació d'una nova arquitectura digital de lectura de píxels per a MAPS. Aquesta tesi presenta un codificador asíncron d'adreces (arquitectura basada en la supressió de zeros transmetent l'adreça dels píxels excitats denominada PADRE) per a l'arquitectura ALPIDE, l'autor també va fer una contribució significativa en l'assemblatge i verificació de circuits. PADRE és la principal recerca de l'autor, basada en un codificador de prioritat jeràrquica de quatre entrades i és una alternativa a l'arquitectura de lectura rolling-shutter. A més dels prototips a petita escala, també s'han desenvolupat prototips a escala completa a les necessitats del detector ITS (15 mm i 30 mm) emprant un nou circuit de lectura basat en la versió personalitzada del circuit PADRE. El pALPIDEfs va ser el primer prototip a escala completa i es va caracteritzar obtenint un temps de lectura de la matriu per sota de 4 µs i un consum d'energia en l'ordre de 80 mWcm¿2 . En general, els resultats obtinguts representen un avanç significatiu de la tecnologia MAPS quant al consum d'energia, velocitat de lectura, temps de recol·lecció de càrrega i tolerància a la radiació. El sensor pALPIDE2 ha demostrat ser una opció molt atractiva per al nou detector ITS, satisfent els requeriments en termes d'eficiència de detecció, fake-hit rate i resolució de posició, ja que el seu rendiment no pot aconseguir-se mitjançant prototips basats en l'arquitectura de lectura tradicionals com és el rolling-shutter dissenyat en la mateixa tecnologia. Per aquesta raó, la R+D en els prototips ALPIDE ha continuat amb l'objectiu d'optimitza / Marín Tobón, CA. (2017). PADRE pixel read-out architecture for Monolithic Active Pixel Sensor for the new ALICE Inner Tracking System in TowerJazz 180 nm technolog [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/86154

As the size of hybrid microelectronics is reduced, the power density increases and thermal interaction between heat-producing devices becomes significant. A nondimensional model is developed to investigate the effects of heat source interaction on a substrate. The results predict the maximum temperature created by a device for a wide range of device sizes, substrate thicknesses, device spacings, and external boundary conditions. They can be used to assess thermal interaction for preliminary design and layout of power devices on hybrid substrates. Previous work in this area typically deals with semi-infinite regions or finite regions with isothermal bases. In the present work, the substrate and all heat dissipating mechanisms below the substrate are modeled as two separate thermal resistances in series. The thermal resistance at the base of the substrate includes the bond to the heat sink, the heat sink, and convection to a cooling medium. Results show that including this external resistance in the model can significantly alter the heat flow path through the substrate and the spreading resistance of the substrate. Results also show an optimal thickness exists to minimize temperature rise when the Biot number is small and the device spacing is large. Tables are presented which list nondimensional values for maximum temperature and spreading resistance over a wide range of substrate geometries, device sizes, and boundary conditions. A design example is included to demonstrate an application of the results to a practical problem. The design example also shows the error that can result from assuming an isothermal boundary at the bottom of the substrate rather than a finite thermal resistance below the substrate. Several other models are developed and compared with the axisymmetric model. A one-dimensional model and two two-dimensional models are simpler than the axisymmetric model but prove to be inaccurate. The axisymmetric model is then compared with a full three-dimensional model for accuracy. The model proves to be accurate when sources are symmetrically spaced and when sources are asymmetrical under certain conditions. However, when the sources are asymmetrical the axisymmetric model does not always predict accurate results. / Master of Science

Neste trabalho é desenvolvido de forma inédita no Brasil um processo simples de fabricação de transistores FD SOI nMOSFET (Fully-Depleted Silicon-On-Insulator) com porta de silício policristalino, para servir como base para futuros desenvolvimentos e, também, com finalidade de educação em microeletrônica. É proposta uma sequência de etapas de fabricação necessárias para a obtenção do dispositivo FD SOI nMOSFET, usando apenas 3 etapas de fotogravação e usando o óxido enterrado, intrínseco à tecnologia SOI, como região de campo, objetivando a obtenção do processo mais simples possível e eficiente. São apresentados os procedimentos detalhados de todas as etapas de fabricação executadas. Para obtenção da tensão de limiar de 1V foram fabricadas amostras com 2 doses diferentes de implantação iônica, 1,0x1013cm-2 e 1,2x1013cm-2. Estas doses resultaram em tensões de limiar (VTH) de 0,72V e 1,08V; respectivamente. Como esperado, a mobilidade independente de campo (0) é maior na amostra com dose menor, sendo de 620cm²/Vs e, para a dose maior, 460cm²/Vs. A inclinação de sublimiar é calculada através da obtenção experimental do fator de acoplamento capacitivo () 0,22; para as duas doses, e resulta em 73mV/déc. O ganho intrínseco de tensão (AV) mostrou-se maior na amostra com maior dose em função da menor condutância de saída, sendo 28dB contra 26dB para a dose menor, no transistor com L=40m e W=12m. Desta forma foi possível implementar uma sequência simples de fabricação de transistores SOI, com resultados elétricos relevantes e com apenas 3 etapas de fotogravação, fato importante para viabilizar seu uso em formação de recursos humanos para microeletrônica. / In this work is developed in an unprecedented way in Brazil a simple process of manufacturing transistors FD SOI nMOSFET (Fully-Depleted Silicon-On-Insulator) with gate polysilicon, to serve as the basis for future developments and also with the purpose of education in microelectronics. A sequence of manufacturing steps necessary for obtaining FD SOI nMOSFET device is proposed, using only three photolithographic steps and using the buried oxide, intrinsic to SOI technology such as field region, aiming to get the simplest possible and efficient process. All the detailed manufacturing steps performed procedures are presented. To obtain the threshold voltage of 1V samples with 2 different doses of ion implantation (1.0x1013cm-2 and 1.2 x1013cm-2) were fabricated. These doses resulted in threshold voltages (VTH) of 0.72 V and 1.08 V, respectively. As expected, mobility independent of field (0) is higher in the sample with the lowest dose, 620cm²/Vs, and for the higher dose, 460cm²/Vs. The subthreshold slope is calculated by obtaining experimental capacitive coupling factor () 0.22, for both doses and results in 73mV/déc. The intrinsic voltage gain (AV) was higher in the sample with a higher dose due to lower output conductance, 28dB against 26dB to the lowest dose, to the transistor with L = W = 40m and 12m. This made it possible to implement a simple sequence of manufacturing SOI transistors with relevant electrical results and with only 3 steps photolithographic important fact to enable their use in training human resources for microelectronics.

Les circuits asynchrones se démarquent des circuits synchrones par une modularité quasi-parfaite, l'absence d'horloge, et le contrôle local. Ils tendent à constituer une sérieuse alternative pour pallier aux problèmes posés par l'intégration en silicium d'applications de plus en plus complexes. Le goulot d'étranglement principal pour l'adoption de la conception des circuits asynchrones se situe au niveau du manque de méthodologies et d'outils puissants pour ce type de conception. Ce travail de thèse porte sur la définition d'une méthodologie de conception de circuits intégrés asynchrones micropipeline. La synthèse micropipeline est une approche qui exploite à la fois les outils commerciaux de synthèse pour le chemin de données, et la synthèse de contrôleurs asynchrones pour le contrôle. La méthodologie générale pour la modélisation et la synthèse de circuits asynchrones est basée sur la spécification dite DTL (Data Transfer Level) qui définit une façon d'écrire les codes sources garantissant une synthèse rapide et systématique pouvant cibler plusieurs styles de circuits asynchrones. Cette méthode de conception part d'une spécification basée sur un langage de haut niveau (CHP ou Concurrent Hardware Processes). Elle permet en sortie de générer des circuits en portes logiques élémentaires et en portes de Muller. Il a été procédé à un prototypage de cette méthode de synthèse. Ce prototype est conçu pour être intégré dans l'outil de conception automatique de circuits asynchrones TAST (Tima Asynchronous Synthesis Tool) dont le synthétiseur génère des circuits asynchrones QDI, pour l'étendre à la génération de circuits micropipelines.