Switching frequency modulation techniques, an inductor current sensing circuit for fast switching converter, and a dual converter are proposed, and the simulation results and experimental results are drawn. The experimental results for monotonic and pseudo-random modulation techniques show that the switching noise peak was effectively reduced as much as -19 dBc. The inductor current sensing circuit accurately tracks the output current of the switching converter that switches up to 30MHz. This current sensing circuit is used to drive the slow converter in the dual converter. The dual converter consists of a fast converter and a slow converter. The fast converter provides only the high frequency conponents in the output current, and the slow converter provides the majority portion of the output current with a higher efficiency. Therefore, the dual converter can have a fast transient response without sacrificing its efficiency. All chips are fabricated in a standard CMOS 0.18um process.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Continuous-time (CT) Delta-Sigma Modulators (DSMs) have re-gained popularity recently for oversampling analog-to-digital conversion, because they are more suitable for low supply voltage implementation than their discrete-time (DT) counterparts, among other reasons. To the state of art at the low voltage front, a CT O.5-V audio-band DSM with a return-to-open feedback digital-to-analog converter has been reported. However, the O.5-V CT DSM has a limited performance of 74-dB SNDR due to clock jitters and other factors caused by the ultralow supply. / Finally, a O.5-V 2-1 cascaded CT DSM with SCR feedback is proposed. A new synthesis method is presented. Transistor-level simulations show that a 98dB SNDR is achieved over a 25-kHz signal bandwidth with a 6.4MHz sampling frequency and 350muW power consumption under a 0.5-V supply. / In this thesis, three novel ULV audio-band CT DSMs with high signal-to-noise-plus-distortion ratio (SNDR) are reported for a nominal supply of O.5V. The first one firstly realizes a switched-capacitor-resistor (SCR) feedback at O.5V, enabled by a fast amplifier at O.5V, for reduced clock jitter-sensitivity. Fabricated in a O.13mum CMOS process using only standard VT devices, the 3rd order modulator with distributed feedback occupies an active area of O.8mm2 . It achieves a measured SNDR of 81.2dB over a 25-kHz signal bandwidth while consuming 625muW at O.5-V. The measured modulator performance is consistent across a supply voltage range from O.5V to O.8V and a temperature range from -20°C to 90°C. Measurement results and thermal-noise calculation show that the peak SNDR is limited by thermal noise. / The scaling of the feature sizes of CMOS technologies results in a continuous reduction of supply voltage (VDD) to maintain reliability and to reduce the power dissipation per unit area for increasingly denser digital integrated circuits. The VDD for low-power digital circuits is predicted to drop to O.5V in about ten years. Ultra-low voltage (ULV) operation will also be required for the analog-to-digital converter, a universal functional block in mixed-signal integrated circuits, in situations where the benefits of using a single VDD out-weigh the overhead associated with multi-V DD solutions. / The second ULV CT DSM employs a feed-forward loop topology with SCR feedback. Designed in O.13mum CMOS process, the modulator achieves a post-layout simulation (thermal noise included) result of 89dB SNDR over a 25-kHz signal bandwidth. The 0.13mum CMOS chip consumes an active area of O.85mm2 and 682.5muW at O.5-V supply. It achieves an excellent measured performance of 87.8dB SNDR over a 25-kHz signal bandwidth and al02dB spurious-free dynamic range. To the best of our knowledge, this performance is the highest for DSMs in this supply voltage range. Thanks to the proposed adaptive biasing technique, the measured modulator performance is consistent across a supply voltage range from O.4V to O.75V and a temperature range from -20°C to 90°C. / Chen, Yan. / Adviser: Kong Pang Pun. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 127-135). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Graduation date: 1996

Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures. In this thesis, different combinations of delta-sigma and pipelined ADCs are explored and new techniques for designing oversampled ADCs are proposed. A Hybrid Delta-Sigma/Pipelined (HDSP) ADC is presented. This ADC uses a pipelined ADC as the quantizer of a single-loop delta-sigma modulator and benefits from the aggressive quantization of the pipelined quantizer at low OSRs. A Noise-Shaped Pipelined ADC is proposed which exploits a delta-sigma modulator as the sub-ADC of a pipeline stage to reduce the sensitivity to the analog imperfection. Three prototype ADCs were fabricated in 0.18μm CMOS technology to verify the effectiveness of the proposed techniques. The performance of these architectures is among the best reported for high bandwidth oversampled ADCs. / Graduation date: 2011

The research investigates several critical design issues of continuous-time (CT) [Sigma Delta] modulators. The first is to investigate the sensitivity of CT [Sigma Delta] modulators to high-frequency clock spurs. These spurs down-convert the high-frequency quantization noise, degrading the dynamic range of the modulator. The second is to study the robustness of continuous-time loop filters under large RC product variations. Large RC variations in the CMOS process strongly degrade the performance of continuous-time [Sigma Delta] modulators, and reduce the production yield. The third is to model the harmonic distortion of one-bit continuous-time [Sigma Delta] modulators due to the interaction between the first integrator and the feedback digital-to-analog converter (DAC). A closed-form expression of the 3'rd-order harmonic distortion is derived and verified. Conventional CT [Sigma Delta] modulators employ all active integrators: each integrator needs an active amplifier. The research proposes a 5th-order continuous-time [Sigma Delta] modulator with a hybrid active-passive loop filter consisting of only three amplifiers. The passive integrators save power, and introduce no distortion. The active integrators provide gain and minimize internal noise contributions. A single-bit switched-capacitor DAC is employed as the main feedback DAC for high clock jitter immunity. An additional current steering DAC stabilizes the loop with the advantage of simplicity. To verify the proposed techniques, a prototype continuous-time [Sigma Delta] modulator with 2-MHz signal bandwidth is designed in a 0.25-¹m CMOS technology targeting for GPS or WCDMA applications. The experimental results show that the prototype modulator achieves 68-dB dynamic range over 2-MHz bandwidth with a 150-MHz clock, consuming 1.8 mA from a 1.5-V supply.

Thesis (MEng)--Stellenbosch University, 2014. / ENGLISH ABSTRACT: Large close range environmental reflections or poor isolation between the transmit and receive paths of an FMCW radar can overload the receiver. The In phase and Quadrature phase (IQ) Reflected Power Canceller (RPC) provides a solution to the problem by cancelling any close range reflections. In this study a procedure to optimise the design of an RPC is developed and the performance limits of a practical RPC is investigated in depth. There are four focus areas in the evaluation and design of the IQ Reflected Power Canceller. First, an analysis was performed on a theoretical IQ Reflected Power Canceller, which provided insight into how the system functioned and made it possible to identify practical application issues that would arise during the design. The next focus area was the IQ Reflected Power Canceller’s dynamic range. Equations, based on the power and noise characteristics of each component in the canceller, were derived. From these equations, a system, with an optimised dynamic range, could be developed. Next, the IQ Reflected Power Canceller’s feedback loop stability was investigated. The canceller is an active negative feedback control system but, in order to obtain the negative feedback, the feedback signal has to be phase shifted by 180 degrees to the phase of the input signal. An analysis of the canceller’s RF phase contribution resulted in an equation that can be used to manage the nett RF phase in the feedback loop. The evaluation model of the IQ Reflected Power Canceller produced favourable results. The tests performed on the system included measuring the level of cancellation that can be achieved, whether the dynamic range corresponds to the predicted values and the amount of RF phase error that can be introduced in the feedback path while maintaining a stable system. The IQ Reflected Power Canceller was found to perform well in the evaluation. It provided a cancellation of more than 45 dB for close range reflections and the canceller remained stable across a wide range of RF centre frequencies (1 GHz). This means that the FMCW radar’s frequency modulation bandwidth will not be limited because of the IQ Reflected Power Canceller. The evaluation clearly showed that the modulator in the feedback loop is the critical element that determines the dynamic range of the radar with an RPC. / AFRIKAANSE OPSOMMING: Onvoldoende isolasie tussen die sender en ontvanger van ’n Frekwensie Gemoduleerde Kontinu Golf radar, sowel as groot weerkaatsings vanaf voorwerpe in die omgewing van die radar, veroorsaak dat die ontvanger versadig. Hierdie beperking veroorsaak dat die radar ’n verminderde dinamiese bereik het, en daarmee ook dat die radar se maksimum teiken-afstand verminder word. Die IQ Gereflekteerde Drywingskanselleerder kan as ’n oplossing gebruik word teen hierdie ongewenste refleksies. Hierdie navorsing poog om ’n kanselleerder te evalueer met die eind doel gestel daarop om ’n praktiese stelsel aanmekaar te sit. Die kanselleerder word geëvalueer deur na vier fokus areas te kyk. Eerstens word ’n ideale model opgestel, wat ’n beter begrip van die kanselleerder bewerkstellig. Uit hierdie ideale model, is daar praktiese oorwegings wat die kanselleerder affekteer, geïdentifiseer. Ten einde die dinamiese bereik van die radar ontvanger te verbeter, word ’n metode afgelei wat gebruik word om die kanselleerder se dinamiese bereik te optimeer. Hierdie metode neem die maksimum drywingsbeperkinge van die komponente in die kanselleerder in ag. Die kanselleerder is ’n aktiewe terugvoer beheerstelsel, en aangesien ’n sommeerder in die terugvoer lus gebruik word, moet die fase deur die lus met 180 grade geskuif word om sodoende ’n kansellerende sein by die ontvangde sein te tel. Die RF fase foute in die kanselleerder word geanaliseer deur ’n nie-ideale model van die kanselleerder op te stel. Hierdie nie-ideale model maak dit moontlik om die effek van ’n RF fase fout op die kanselleerder se stabiliteit te ondersoek. ’n Praktiese kanselleerder is ontwerp uit die inligting wat versamel is gedurende die evaluasie, en ’n werkende stelsel is aanmekaar gesit. Met hierdie praktiese kanselleerder is die hoeveelheid drywing-onderdrukking wat bereik kan word, gemeet. Die dinamiese bereik van die kanselleerder is ook bepaal en vergelyk met die teoreties berekende waardes. Die aannames oor die effek van die RF fase fout in die kanselleerder, is bevestig deur metings te neem. Goeie resultate is met die kanselleerder behaal. ’n Kansellasie van meer as 45 dB is gemeet vir naby-geleë refleksies. Die kanselleerder het ook stabiel gebly oor ’n wye band van senter-frekwensies (1 GHz). Dus sal die Frekwensie Gemoduleerde Kontinu Golf radar se modulasie bandwydte nie beperk word as gevolg van die kanselleerder nie. Uit die evaluasie is daar gevind dat die modulator die kritieke element in the kanselleerder se terugvoer lus is, dus bepaal die modulator die dinamiese bereik van die radar met ’n kanselleerder.

This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to the conventional active adder, the direct charge transfer (DCT) adder greatly saves power by keeping the feedback factor of the active adder unity. However, the inherent delay originated from the DCT adder will cause instability to the modulator and complex additional branches are usually needed to stabilize the loop. A simple and power-efficient technique is proposed to absorb the delay from the DCT adder and the instability issue is therefore solved. Another proposed low-power design technique is to feed differentiated inverted quantization noise to the input of the last integrator. The modulator noise-shaping order with this proposed technique is effectively increased from two to three without adding additional active elements. The delta-sigma ADC with the proposed architectural design techniques has been implemented in transistor-level and fabricated in 0.18 µm CMOS technology. Measurement results showed a SNDR of 99.3 dB, a DR of 101.3 dB and a SFDR of 112 dB over 20 kHz signal bandwidth, resulting in a very low figure-of-merit (FoM) in its application category. Finally, two new circuit ideas, low-power parasitic-insensitive switched-capacitor integrator for delta-sigma ADCs and switched-resistor tuning technique for highly linear Gm-C filter design are presented. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from June 9, 2012 - June 9, 2014

Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT structure, the DT ΔΣ ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT ΔΣ ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart. In this thesis, both DT and CT ΔΣ ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth. For DT ΔΣ ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT ΔΣ ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications. For CT ΔΣ ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT ΔΣ ADCs and it is promising to achieve low power dissipation for wideband applications. Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected. / Graduation date: 2010