The feasibility of developing test circuits to perform in-circuit testing of analog circuits is investigated in this thesis. A modular approach to analog testing has been adopted. Accordingly, the testing of an operational amplifier, which is a basic building block in analog circuits, is addressed. One convenient technique for measuring the frequency response of an op-amp requires a unity gain buffer to be inserted into its feedback loop. This buffer has to be simple in construction, small and accurate. Two buffer circuits that satisfy these requirements are described in this thesis. Enhanced slewing techniques are devised to achieve increased levels of performance. The buffers were integrated with an op-amp into a test chip. Digital logic is used to provide controllability and accessibility to each of the buffers and the op-amp so that they can characterized separately. The performance of the enhanced slewing buffers was verified with measurements performed on the test chip. The performance of the buffers conformed well with the simulated values. The buffers exhibited excellent settling times even while driving large capacitive loads. Their output swing and distortion performance were good for inputs as large as 2 V peak-to-peak values. / Graduation date: 1994

Low-power and small size analog to digital converters (ADCs) are the strategic building blocks in state of the art mobile wireless communication systems. Various techniques have been developed to reduce both power consumption and die area of the ADC. Among these, the opamp-sharing technique shows the most promise. In opamp-sharing, power and die area are saved by sharing one opamp between two successive pipeline stages. However, this technique suffers from the well-known memory effect drawback due to the absence of the reset phase that discharges the opamp's input parasitics. In this dissertation, this drawback is solved by introducing a discharge phase before the opamp is used for the pipeline stages without compromising speed and resolution of the ADC. Further power and area reduction is achieved by using a capacitor-sharing technique. This technique reduces the effective load capacitance of the opamp by reusing the charge on the feedback capacitor for the MDAC operation of the following stage, resulting in faster settling without increasing opamp power. The proposed low input-capacitance variable-gm opamp also helps to reduce the memory effect and improves the settling behavior of the stage output by increasing the bandwidth of the opamp while input parasitics of the opamp are kept small. The prototype designs of a 10-bit 50MSample/s pipelined ADC and a 14-bit 100MSample/s pipelined ADC implemented in 0.18¹m CMOS technology demonstrate the effectiveness of the proposed techniques. The first ADC achieves 56.2dB SNDR and 72.7dB SFDR for a Nyquist input at full sampling rate while consuming 12 mW from a 1.8-V supply. The FOM, defined as, [power/2[superscript ENOB].Fs], is 0.46 pJ/step with Fin = 24.5MHz at 50MS/s. The second ADC achieves 72.4dB SNR and 88.5dB SFDR at 100MS/s with a 46MHz input and consumes 230mW from a 3V supply. The FOM of the second ADC is 0.69 pJ/step with Fin = 46MHz at 100MS/s.

No description available.

Thesis (Ph. D.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2007. / Includes bibliographical references (p. 117-121).

Thesis (Ph. D.)--Washington State University, December 2008. / Title from PDF title page (viewed on Jan. 15, 2009). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 60-61).

Thesis (M.S.)--Rochester Institute of Technology, 1990. / Typescript. Includes bibliographical references (leaf [201]).

The effects of radiation on an operational amplifier were investigated through simulation. The μA 741 was simulated using Spice. Under normal conditions the 741 had the following properties: offset Voltage (Vos) of 0.8 mV, bias current (IB) of 27 nA, offset current (Ios) of 1 nA, and an open loop gain (A0.1.) of 112 dB. When exposed to neutron fluence of 5 x 10¹³ n/cm², these parameters changed to offset voltage of 45 mV, bias current of 1500 nA, offset current of 500 nA, and an open loop gain of 66 dB. A new circuit is proposed that provides improvements in the above parameters. The modified circuit gives a Vos of 3 mV, IB of 200 nA, Ios of 34 nA and A0.1. of 93 dB following exposure to a neutron fluence of 5 x 10¹³n/cm².

No description available.

No description available.

Ho Kin-Pui. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 92-95). / Abstracts in English and Chinese. / Abstract --- p.2 / 摘要 --- p.4 / Acknowledgements --- p.5 / Table of Contents --- p.6 / List of Figures --- p.10 / List of Tables --- p.14 / Chapter Chapter 1 --- Introduction --- p.15 / Overview --- p.15 / Objective --- p.17 / Thesis Organization --- p.17 / Chapter Chapter 2 --- Fundamentals of Operational Amplifier --- p.19 / Chapter 2.1 --- Definitions of Commonly Used Figures --- p.19 / Chapter 2.1.1 --- Input Differential Voltage Range --- p.19 / Chapter 2.1.2 --- Maximum Output Voltage Swing --- p.20 / Chapter 2.1.3 --- Input Common Mode Voltage Range --- p.20 / Chapter 2.1.4 --- Input Offset Voltage --- p.20 / Chapter 2.1.5 --- Gain Bandwidth Product --- p.21 / Chapter 2.1.6 --- Phase Margin --- p.22 / Chapter 2.1.7 --- Slew Rate --- p.22 / Chapter 2.1.8 --- Settling Time --- p.23 / Chapter 2.1.9 --- Common Mode Rejection Ratio --- p.23 / Chapter 2.2 --- Frequency Compensation of Operational Amplifier --- p.24 / Chapter 2.2.1 --- Overview --- p.24 / Chapter 2.2.2 --- Miller Compensation --- p.25 / Chapter Chapter 3 --- CMOS Current Feedback Operational Amplifier --- p.27 / Chapter 3.1 --- Introduction --- p.27 / Chapter 3.2 --- Current Feedback Operational Amplifier with Active Current Mode Compensation --- p.28 / Chapter 3.2.1 --- Circuit Description --- p.29 / Chapter 3.2.2 --- Small Signal analysis --- p.32 / Chapter 3.2.3 --- Simulation Results --- p.34 / Chapter Chapter 4 --- Reversed Nested Miller Compensation --- p.38 / Chapter 4.1 --- Introduction --- p.38 / Chapter 4.2 --- Frequency Response --- p.39 / Chapter 4.2.1 --- Gain-bandwidth product --- p.40 / Chapter 4.2.2 --- Right half complex plane zero --- p.40 / Chapter 4.2.3 --- The Pair of Complex Conjugate Poles --- p.42 / Chapter 4.3 --- Components Sizing --- p.47 / Chapter 4.4 --- Circuit Simulation --- p.48 / Chapter Chapter 5 --- Enhancement Technique for Reversed Nested Miller Compensation --- p.54 / Chapter 5.1 --- Introduction --- p.54 / Chapter 5.2 --- Working principle of the proposed circuit --- p.54 / Chapter 5.2.1 --- The introduction of nulling resistor --- p.55 / Chapter 5.2.2 --- The introduction of a voltage buffer --- p.55 / Chapter 5.2.3 --- Small Signal Analysis --- p.57 / Chapter 5.2.4 --- Sign Inversion of the RHP Zero with Nulling Resistor --- p.59 / Chapter 5.2.5 --- Frequency Multiplication of the Complex Conjugate Poles --- p.60 / Chapter 5.2.6 --- Stability Conditions --- p.63 / Chapter 5.3 --- Performance Comparison --- p.67 / Chapter 5.4 --- Conclusion: --- p.70 / Chapter 5.4.1 --- Circuit Modifications: --- p.70 / Chapter 5.4.2 --- Advantages: --- p.71 / Chapter Chapter 6 --- Physical Design of Operational Amplifier --- p.72 / Chapter 6.1 --- Introduction --- p.72 / Chapter 6.2 --- Transistor Layout Techniques --- p.72 / Chapter 6.2.1 --- Multi-finger Layout Technique --- p.72 / Chapter 6.2.2 --- Common-Centroid Structure --- p.73 / Chapter 6.3 --- Layout Techniques of Passive Components --- p.74 / Chapter 6.3.1 --- Capacitor Layout --- p.74 / Chapter 6.3.2 --- Resistor Layout --- p.75 / Chapter Chapter 7 --- Measurement Results --- p.77 / Chapter 7.1 --- Overview --- p.77 / Chapter 7.2 --- Measurement Results for the Current Feedback Operational Amplifier --- p.77 / Chapter 7.2.1 --- Frequency Response of the inverting amplifier --- p.77 / Chapter 7.3 --- Measurement Results for the Three-Stage Operational Amplifier --- p.80 / Chapter 7.3.1 --- Input Offset Voltage Measurement --- p.80 / Chapter 7.3.2 --- Input Common Mode Range Measurement --- p.80 / Chapter 7.3.3 --- Gain Band width Measurement --- p.81 / Chapter 7.3.4 --- DC Gain measurement --- p.85 / Chapter 7.3.5 --- Slew Rate Measurement --- p.87 / Chapter 7.3.6 --- Phase Margin --- p.88 / Chapter 7.3.7 --- Performance Summary --- p.89 / Chapter Chapter 8 --- Conclusions --- p.90 / Chapter Chapter 9 --- Appendix --- p.96