In recent years, the subject of wide-area synchronized measurements has gained a significant amount of attention from the power system researchers. All of this started with the introduction of the Phasor Measurement Unit (PMU), which added a new perspective in the field of wide-area measurement systems (WAMS). With the ever evolving technologies over the years and the need for a more cost effective solution for synchronized frequency measurements, the Frequency Monitoring Network (FNET) was developed and introduced by the Power IT laboratory at Virginia Tech. The FNET is comprised of many Frequency Disturbance Recorders (FDR) geographically distributed throughout the United States. The FDR is a dedicated data acquisition device deployed at the distribution level, which allows for a lower cost and easily deployable WAMS solution. With Internet connectivity and GPS timing synchronization, the FDR provides high accuracy frequency, voltage magnitude and voltage angle data to the remote servers. Although the current FDR design is up to the standard in terms of the measurement accuracy and portability, it is of interest to further the research into alternative architectures and leverage the ever advancing technologies in high speed computing. One of the purposes of this dissertation is to present novel design options for a new generation of FDR hardware design. These design options will allow for more flexibility and to lower reliance on some vendor specific components. More importantly, the designs seek to allow for more computation processing capabilities so that more accurate frequency and angle measurements may be obtained. Besides the fact that the accuracy of frequency and angle measurement is highly dependent on the hardware and the algorithm, much can be said about the role of timing synchronization and its effects on accurate measurements. Most importantly, the accuracy of the frequency and angle estimation is highly dependent on the sampling time of local voltage angles. The challenges to accurate synchronized sampling are two folds. One challenge has to do with the inherent fallbacks of the GPS receiver, which is relatively high cost and limited in availability when the satellite signal is degraded. The other challenge is related to the timing inaccuracies of the sampling pulses, which is attributed to the remainder that results from the imperfect division of the processor counter. This dissertation addresses these issues by introducing the implementation of the high sensitivity (indoor) GPS and network timing synchronization, which aims to increase the availability of frequency measurements in locations that would not have been possible before. Furthermore, a high accuracy timing measurement system is introduced to characterize the accuracy and stability of the conventional crystal oscillator. To this end, a new method is introduced in close association with some prior work in generating accurate sampling time for FDR. Finally, a new method is introduced for modeling the FDR based on the sampling time measurements and some results are presented in order to motivate for more research in this area. / Ph. D.

A G-quadruplex (GQ) is a type of noncanonical nucleic acid structure that can form in regions of nucleic acids rich in guanine nucleotides. The guanine bases form a square planar conformation via Hoogsteen hydrogen bonding. These stacked tetrads have inward-facing carbonyl oxygens, facilitating the coordination of ions. Improper GQ conformations can lead to improper regulation of gene expression, potentially resulting in genetic diseases or cancer. Here, we performed molecular dynamics simulations using the Drude polarizable force field (FF) to gain insight into factors contributing to the stability of two GQs. One is the bcl-2 promoter region GQ, which is implicated in several types of cancer including B-cell lymphoma, and the second is the sc1 RNA GQ, which binds to the Fragile-X Mental Retardation Protein (FMRP) and is implicated in the development of Fragile X Syndrome (FXS). Aberrant bcl-2 GQ conformations result in increased production of the BCL2 protein, which is an apoptosis inhibitor. As such, we aim to characterize the factors stabilizing the GQ for future small-molecule development to prevent apoptosis inhibition and therefore cancer. The FMRP protein functions as a regulator of sc1 conformation to control the translation of proteins required for frontal lobe development. FXS arises from a nonsense mutation that causes the deletion of the C-terminal region of FMRP, rendering it non-function. Therefore, we aim to simulate sc1 when FMRP is bound as well as unbound to provide insight into the types of interactions that must be maintained and therefore mimicked by a small molecule drug. / Master of Science in Life Sciences / DNA is commonly represented as a double helix and RNA is thought of as a simple single stranded, disordered molecule, but DNA and RNA can both adopt more complicated structures. An example of this is the G-quadruplex (GQ), a structure that can form in regions of DNA and RNA that are rich in guanine. These guanine bases form a stable core structure that can act as an "on-off" switch for different processes in the cell. Alterations to GQ structure can lead to dysfunction and different types of disease. Here, we perform atomistic computer simulations to further understand factors that contribute to GQ stability, focusing on two different GQs, one of plays a role in several types of cancer, and the other whose regulation is in Fragile X Syndrome (FXS). Furthermore, we study the Fragile X Mental Retardation Protein, which is what brain cells normally use to regulate expression of proteins needed for frontal lobe development by modulating specific GQ structure. The information from these simulations can be used to potentially develop drugs for these conditions.

The explosive growth in wireless communications has led to an increased demand for wireless products that are cheaper, smaller, and lower power. Recently there has been an increased interest in using CMOS, a traditional digital and low frequency analog IC technology, to implement RF components such as mixers, voltage controlled oscillators (VCOs), and low noise amplifiers (LNAs). Future mass-market RF links, such as BlueTooth, will require the potentially low-cost single-chip solutions that CMOS can provide. In order for such single-chip solutions to be realized, RF circuits must be designed that can operate in the presence of noisy digital circuitry. The voltage controlled oscillator (VCO), an important building block for RF systems, is particularly sensitive when exposed to an electrically noisy environment. In addition, CMOS implementations of VCOs have been hampered by the lack of high-quality integrated inductors. This thesis focuses on the design of a fully integrated 2.5 GHz LC CMOS VCO. The circuit is intended as a vehicle for future mixed RF/digital noise characterization. The circuit was implemented in a 0.35 μm single poly, 4 metal, 3.3 V, CMOS process available through MOSIS. The oscillator uses a complementary negative transconductance topology. This oscillator circuit is analyzed as a negative-resistance oscillator. Monolithic inductors are designed using full-wave electromagnetic field solver software. The design of an "inversion-mode" MOS (I-MOS) tuning varactor is presented, along with a discussion of the effects of varactor nonlinearity on VCO performance. I-MOS varactors are shown to have substantially improved tuning range (and tuning curve linearity) over conventional MOS varactors. Practical issues pertaining to CMOS VCO circuit design, layout, and testing are also discussed. The characterization of the VCO and the integrated passives is presented. The VCO achieves a best-case phase noise of -106.7 dBc/Hz at 100 kHz offset from a center frequency of 2.73 GHz. The tuning range is 425 MHz (17%). The circuit consumes 9 mA from a 3.3 V supply. This represents excellent performance for CMOS oscillator designs reported at this frequency. Finally, several recommendations for improvements in oscillator performance and characterization are discussed. / Master of Science

Master Oscillator Power Amplifiers (MOPA) are laser systems that utilize a seed and pump amplification system to boost the output power of high-quality lower power seeding signals. MOPAs can generate high gain while avoiding many of the nonlinearities that negatively affect resonance-based lasers that are known to feature higher internal intensities. Additionally, MOPAs provide an easy alternative to the construction of novel laser technologies for higher output power as they can be easily combined with existing laser sources to amplify their output power. This thesis outlines the design of an ytterbium-doped fiber laser (YDFL), featuring a MOPA architecture. The YDFL is constructed to amplify a continuous wave single mode signal, at 1064nm, from 366mW to 16.4W while maintaining high spectral purity and beam quality. This laser is being developed with the intention to seed a subsequent MOPA YDFL for amplification to 1.5kW, for use in following thermal blooming experiments. As a result, the laser being developed in this work must have high spectral purity, centered near 1064nm, and a narrow linewidth, less than 0.25nm. Methods for limiting instabilities within the MOPA amplification stages are developed and the final seed laser emission quality is demonstrated in this work.

<p>Random numbers are required for cryptographic applications such as IT security products, smart cards etc. Hardwarebased random number generators are widely employed. Cryptographic algorithms are implemented on FieldProgrammable Gate Arrays (FPGAs). In this work a True Random Number Generator (TRNG) employed for spaceapplication was designed, investigated and evaluated. Several cryptographic requirements has to be satisfied for therandom numbers. Two different noise sources was designed and implemented on the FPGA. The first design wasbased on ring oscillators as a noise source. The second design was based on astable oscillators developed on a separatehardware board and interfaced with the FPGA as another noise source. The main aim of the project was to analyse theimportant requirement of independent noise source on a physical level. Jitter from the oscillators being the source forthe randomness, was analysed on both the noise sources. The generated random sequences was finally subjected tostatistical tests.</p>

Random numbers are required for cryptographic applications such as IT security products, smart cards etc. Hardwarebased random number generators are widely employed. Cryptographic algorithms are implemented on FieldProgrammable Gate Arrays (FPGAs). In this work a True Random Number Generator (TRNG) employed for spaceapplication was designed, investigated and evaluated. Several cryptographic requirements has to be satisfied for therandom numbers. Two different noise sources was designed and implemented on the FPGA. The first design wasbased on ring oscillators as a noise source. The second design was based on astable oscillators developed on a separatehardware board and interfaced with the FPGA as another noise source. The main aim of the project was to analyse theimportant requirement of independent noise source on a physical level. Jitter from the oscillators being the source forthe randomness, was analysed on both the noise sources. The generated random sequences was finally subjected tostatistical tests.

La génération de signaux microondes à grande pureté spectrale est fondamentale pour différentes applications (systèmes RADAR, échantillonnage large bande). L’optique propose des solutions prometteuses pour la montée en fréquence des d’oscillateurs à bas bruit de phase. L’objectif de cette thèse est d’étudier différentes configurations d’oscillateurs optoélectroniques (OEO) à 10 GHz. Pour cela, nous avons développé puis validé expérimentalement un modèle décrivant le bruit de phase, que nous avons ensuite étendu aux OEOs à boucles multiples. Cet outil unique nous a permis de concevoir un OEO à double boucles à l’état de l’art avec un encombrement réduit (premier mode parasite avec un niveau de bruit de phase de -146 dBc/Hz à 187 kHz de la porteuse). Nous avons également étudié des OEOs à amplification optique qui permettent de lever les verrous associés aux amplificateurs RF lors de la montée en fréquence (contribution de bruit et bande passante) tout en conservant d’excellentes performances. Enfin, nous nous sommes intéressés aux oscillateurs optoélectroniques couplés (COEOs), qui associent un laser à verrouillage de modes à un OEO. Nous avons modélisé le bruit de phase du laser en tenant en compte pour la première fois la non-orthogonalité des modes de la cavité, puis initié un modèle pour le COEO. Après une étude expérimentale des paramètres clef, nous avons réalisé un COEO proche de l’état de l’art, dont le bruit phase au voisinage de la porteuse est amélioré par rapport aux OEOs pour des longueurs de boucle plus courtes. / High purity microwave signal generation is required in various applications (RADAR systems, wideband sampling). For high frequency operations, optics offer promising solutions to generate low noise oscillators. The objective of this thesis consists in studying various optoelectronic oscillator (OEO) configurations at 10 GHz. We first worked on a phase noise model and its experimental validation, further extended to multiple loop OEOs. This comprehensive model allowed the design of a state-of-the-art dual loop OEO with consideration to its compactness (first spur located at 187 kHz from the carrier with a phase noise level of 146 dBc/Hz).We then focused on all photonic gain OEOs to get rid of RF amplifiers whose bandwidth and noise contributions are a limit for high frequency operations. Finally, we studied coupled optoelectronic oscillators (COEOs) which may simply be described as a combination of a mode locked laser and an OEO. We worked on a phase noise model for active and harmonically mode locked laser taking into account for the first time the non-orthogonality of the cavity modes. This model is the basis to a COEO model we began to develop. After experimentally determining key parameters, we designed and optimized a low noise COEO exhibiting a close-to-carrier phase noise similar to the state-of-the-art.

No description available.

Advanced achievements in the area of RF circuit design led to a significant increase in availability of wireless communications in everyday life. However, the rapid growth in utilizing the RF equipment has brought several challenges in different aspects of RF circuit design. This has been motivating researchers to introduce solution to cope with these challenges and further improve the performance of the RF circuits. In this dissertation, we focus on the improvements in three aspects of the circuit design. High temperature and temperature compensated transmitter design, ultra-low phase noise signal generators, and compact and low complexity polar transmitter design. Increase in the ambient temperature can impact the performance of the entire communication system. However, the RF hardware is main part of the system that is under the impact of the temperature variations in which it can change the characteristics of the individual building blocks of the RF chain. Moreover, transistors are the main elements in the circuit whose performance variation must be consider when the design target is compensating the temperature effects. The influence of the temperature variation is studied on the transistors and the building blocks in order to find the most effective approaches to compensate these variations and stabilize the performance of the RF chain at temperatures up to 220 C. A temperature sensor is designed to sense these variations and adjust the characteristics of the circuit components (e.g. bias voltages), accordingly. Further, a new variable gain phase shifter (VGPS) architecture is introduced toward minimizing the temperature impact on its performance in a phased-array transmitter architecture. Finally, a power amplifier as the last stage in a transmitter chain is designed and the variation in its performance with temperature is compensated through the VGPS stage. The transmitter is prototyped to evaluate its performance in practice. Another contribution of this dissertation is to introduce a novel voltage-controlled oscillator (VCO) structure to reduce the phase noise level below state-of-the-art. The noise to phase noise mechanism in the introduced doubly tuned oscillator is studied using linear time-variant (LTV) theory to identify the dominant noise sources and either eliminate or suppress these noise sources by introducing effective mechanism such as impedance scaling. The designed VCO is fabricated and measurement results are carried out that justified the accuracy of the analyses and effectiveness of the introduced design approach. Lastly, we introduce a compact and simple polar transmitter architecture. This type of transmitters was firstly proposed to overcome the serious shortcomings in the IQ transmitters, such as IQ imbalance and carrier leakage. However, there is still several challenges in their design. We introduce a transmitter architecture that operates based on charge to phase translation mechanism in the oscillator. This leads to significantly reduction in the design complexity, die area, and power dissipation. Further, it eliminates a number of serious issues in the design such as sampling rate of the DACs. comprehensive post-layout simulations were also performed to evaluate its performance. / Doctor of Philosophy / To keep up with the ever-growing demand for exchanging information through a radio frequency (RF) wireless network, the specification of the communication hardware (i.e. transmitter and receiver) must be improved as the bottleneck of the system. This has been motivating engineers to introduce new and efficient approaches toward this goal. In this dissertation however, we study three aspects of the circuit design. First, variation in the ambient temperature can significantly degrade the performance of the communication system. Therefore, we study these variations on the performance of the transmitter at high temperature (i.e. above 200 C). Then, the temperature compensation approaches are introduced to minimize the impact of the temperature changes. The effectiveness of the introduced techniques are validated through measurements of the prototyped transmitter. Second, signal generators (i.e. oscillators) are the inseparable blocks of the transmitters. Phase noise is one of the most important specifications of the oscillators that can directly be translated to the quality and data rate of the communication. A new oscillator structure targeting ultra-low phase noise is introduced in the second part of this dissertation. The designed oscillator is fabricated and measured to evaluate its performance. Finally, a new polar transmitter architecture for low power applications is introduced. The transmitter offers design simplicity and compact size compared to other polar transmitter architectures while high performance.

Following the rise of Internet of Things (IoT), or just the technological advancements and expectations in a world where the things are or will be connected, new demands are put on Integrated Circuit (IC) for wireless connectivity. The use cases seem endless; smart home, healthcare, entertainment, and science are all areas that can benefit from connectivity of low power electronics. But there are obstacles to overcome. Meeting the specifications, especially the phase noise requirements of modern high-speed wireless standards can be a challenge for devices that run on low supply voltages and are allowed only very limited power consumption. The focus of this thesis is the exploration of modern LC-oscillator architectures for RF-transceivers, and the design and post-layout evaluation of a Digitally Controlled Oscillator (DCO) intended to be used in an All-Digital Phase Locked Loop (ADPLL) in a 22 nm FD-SOI process. The DCO specifications are set by an ADPLL for the Wi-Fi 6 (MCS 11) standard. The ADPLL is replacing the blocks that are usually implemented as noise-sensitive analog components with more robust digital blocks that are easier to integrate with baseband- and digital-circuitry. A dual-core class-C oscillator with a dynamic-biasing circuit is proposed and designed to meet the specification of -121 dBc/Hz phase noise at a 1 MHz offset from 7.8 GHz, a –7.18.6 GHz tuning range, and a frequency resolution of at most 35 kHz around 7.8 GHz. The phase noise specification is met; a phase noise of -121 dBc/Hz at the 1 MHz offset from 7.8 GHz is achieved in post-layout simulation along with a Figure of Merit (FoM) of 189.9, and an average tracking frequency step of 5.8 MHz. The tuning range specification was not met, but it is reasonable to believe that the specified range can be met after some redesign of the capacitor banks. Further work will be required. / Till följd av tillväxten inom Internet of Things (IoT), eller bara de teknologiska framgångar och förväntningar på en värld där dem flesta saker är eller kommer att bli uppkopplade, ställs nya krav på Integrated Circuit (IC)-komponenter för trådlös uppkoppling. Tillämningsområdena är oändliga; smart home, sjukvård och hälsa, underhållning och forskning är områden som som kan dra nytta av nya uppkopplingsmöjligheter med extremt strömsnål elektronik. Att leva upp till specifikationerna för moderna trådlösa höghastighetsuppkopplingar, speciellt när det kommer till fasbrus, kan dock vara en utmaning för enheter som måste klara sig med en väldigt begränsad effektåtgång. Fokus för denna avhandling är design och utvärdering på schematik och layout-nivå av en Digitally Controlled Oscillator (DCO) för en 22 nm Fully Depleted Silicon-On-Insulator (FD-SOI)-process avsedd att klara specifikationen satt av en given All-Digital Phase Locked Loop (ADPLL) för Wi-Fi 6 (MCS 11) standarden. En DCO och ADPLL ersätter block som tidigare tillämpats som analoga bruskänsliga komponenter med robustare digitala komponenter som är enklare att integrera med bas-band och digital logik-kretsar. En dubbelkärnig klass-C DCO med en dynamisk biaskrets föreslås för att nå kravet på fasbrus på maximalt -121 dBc/Hz mätt vid 1 MHz från en frekvens på 7.8 GHz, med ett frekvensomfång 7.1-8.6 GHz och en frekvensupplösning under 35 kHz. Fasbruset vid denna 1 MHz från 7.8 GHz uppmättes i simulering till -121 dBc/Hz, och en Figure of Merit (FoM) på 189.9 har uppnåtts, samt en genomsnittlig frekvensupplösning på 5.8 MHz nära 7.8 GHz. Designen klarar inte av att möta kraven på frekvensomfång, men det är sannolikt att en liknande design kan möta specifikationen efter ytterligare revision. Ytterligare arbete krävs.