At present, one of the main issues in electric power networks is the reduction in conventional generation and its replacement by low inertia renewable energy generation. The balance between generation and demand has a direct impact on the system frequency and system inertia limits the frequency rate of change until compensation action can be undertaken. Traditionally generation managed frequency. In future, loads may be required to do more than just be able to be switched off during severe under frequency events. This thesis focuses on the development and practical implementation of the control structure of a smart adaptive load for network power-frequency support applications. The control structure developed makes use of advanced demand side management of fan loads (powered by AC drives) used in heating, ventilation, and air conditioning systems; where a change in power at rated load has little effect on their speed due to the cubic relationship between speed and power. The AC drive implemented in this thesis is based on an induction motor and a two level voltage source converter. To achieve the smart adaptive load functionality, first a power-frequency multi-slope droop control structure (feedforward control) is developed; relating the frequency limits imposed by the network supplier and the fan power-speed profile (Chapter 2, Fig 2.19). Secondly, this control structure is combined with the control developed, in Chapter 3, for the AC drive powering the fan load. The full development of the control structure of the AC drive, its tuning process and its practical implementation is given; an equation is developed to find suitable tuning parameters for the speed control of the nonlinear load (fan load), i.e. Eq. (3.59).The analysis and simulation results provided in Chapter 4 conclude that a fast control of the active power drawn by the AC drive is possible by controlling the electromagnetic torque (hence current) of the induction motor without disturbing the fan load overly. To achieve this, changes between closed loop speed control and open loop torque control (power control) are performed when needed. Two main issues were addressed before the hardware implementation of the smart adaptive load: the estimation of the network frequency under distorted voltage conditions, and the recovery period of the network frequency. In this thesis two slew rate limiters were implemented to deal with such situations. Other possible solutions are also outlined. Finally, experimental results in Chapter 5 support results given in Chapter 4. A full power-frequency response is achieved by the smart adaptive load within 3s.

Orientadores: Sigmar Maurer Deckmann, Fernando Pinhabel Marafão / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-07T20:09:32Z (GMT). No. of bitstreams: 1 Padua_MarceloSuzartde_M.pdf: 2971342 bytes, checksum: f838d91f23e156c63fa9582c9c5c582e (MD5) Previous issue date: 2006 / Resumo: Este trabalho visa contribuir para os estudos sobre sincronismo em um Sistema Elétrico de Potência (SEP), com enfoque em Geração Distribuída (GD). Buscar-se-á analisar as condições para operação de um gerador distribuído em paralelo com a rede elétrica, bem como desenvolver metodologias de sincronismo para tal. Muitos algoritmos propostos para aplicações em Eletrônica de Potência e Qualidade da Energia Elétrica podem ser utilizados para este propósito. Inicialmente, será apresentadas uma síntese dos tipos de geração alternativa existentes e suas características. Considerando que o Brasil, até o momento, não possui legislação específica referente à GD, serão expostas as principais normas internacionais aplicáveis ao sincronismo e à conexão do gerador, além de aspectos de segurança, como condições de ilhamento. Cada um dos algoritmos escolhidos (PLL, TDFR e FK) será estudado com o objetivo de observar sua resposta dinâmica, precisão em regime e robustez na presença de distorções harmônicas e/ou transitórios nas tensões da rede, de acordo com o ajuste dos seus parâmetros. Finalmente, serão apresentados resultados de simulação de um sistema de GD característico. Uma carga, alimentada pela rede elétrica de distribuição, passará a receber energia também de um gerador local, que será conectado em paralelo com esta rede com auxílio dos algoritmos de sincronismo estudados. Resultados experimentais confirmarão a possibilidade de implementação dessas técnicas / Abstract: This dissertation presents a contribution to the study of synchronization in Electric Power Systems, focusing Distributed Generation. The conditions for operation of a distributed generator in parallel with the grid will be analyzed and applicable methodologies of synchronism will be presented. Different algorithms proposed for Power Electronics Applications and Power Quality Analysis can be used for this intention. Initially, this work presents a synthesis of the existing types of alternative generation and their characteristics. Considering that in Brazil, up to this moment, does not exist a specific legislation for distributed generation, the international main applicable norms about synchronization and connection of the generator will be exposed, including security aspects, such as islanding conditions. Each of the chosen algorithms will be studied to observe its dynamic response, accuracy and robustness in presence of harmonic distortions or transients in the utility voltage, according to the adjusted parameters. Finally, simulation results of a characteristic industrial plant will be presented. The utility system supplies a load, which will draw power also from a local generator, connected to this grid, with the aid of the studied synchronism algorithms. Experimental results will confirm the possibility of implementation of these techniques / Mestrado / Energia Eletrica / Mestre em Engenharia Elétrica

This thesis describes GSM communication, the method of its jamming and design of a jammer for this band. This document is mainly focused on design of the jammer with the variable bandwidth of jamming and the variable level of output power. Requested parameters of jamming are set by a control panel with a LCD display. In this document there is a detailed description of each function block and connection between them. At the end of this thesis there are released measured results of designed jammer.

This project deals with possibilities of using the software defined radio conception for radio amateur use in a short wave band and its subsequent implementation into properly designed hardware. The aim of this work is to design a transceiver that would be capable of working in AM, FM, SSB, and CW modes. Within a theoretical part of the project the architectures of software defined radios and their components are discussed. This part was focused mainly on analog parts of the chain, such as amplifiers, filters and converters. Signal processing algorithms for both receiver and transmitter working in desired modes are studied subsequently and their computer models are built. Designed algorithms are implemented into FPGA structure (Virtex -5).

This thesis proposes and demonstrates Time to Digital Converters (TDC) with high resolution realized in 65-nm digital CMOS. It is used as a phase detector in all digital PLL working with 5GHz DCO and 20MHz reference input for radio transmitters. Two kinds of high resolution TDC are designed on schematic level including Vernier TDC and parallel TDC. The Sensed Amplifier Flip Flop (SAFF) is implemented with less than 1ps sampling window to avoid metastability. The current starved delay elements are adopted in the TDC and the conversion resolution is equal to the difference of the delay time from these delay elements. Furthermore, the parallel TDC is realized on layout and finally achieves the resolution of 3ps meanwhile it consumes average power 442μW with 1.2V power supply. Measured integral nonlinearity and differential nonlinearity are 0.5LSB and 0.33LSB respectively.

With the advancement of CMOS process and fabrication, it has been a trend to maximize digital design while minimize analog correspondents in mixed-signal system designs. So is the case for PLL. PLL has always been a traditional mixed-signal system limited by analog part performance. Around 2000, there emerged ADPLL of which all the blocks besides oscillator are implemented in digital circuits. There have been successful examples in application of Bluetooth, and it is moving to improve results for application of WiMax and ad-hoc frequency hopping communication link. Based on the theoretic and measurement results of existing materials, ADPLL has shown advantages such as fast time-to-market, low area, low cost and better system integration; but it also showed disadvantages in frequency resolution and phase noise, etc. Also this new topic still opens questions in many researching points important to PLL such as tracking behavior and quantization effect. In this thesis, a non-linear phase domain model for all digital phase-locked loop (ADPLL) was established and validated. Based on that, we analyzed that ADPLL phase noise prediction derived from traditional linear quantization model became inaccurate in non-linear cases because its probability density of quantization error did not meet the premise assumption of linear model. The phenomena of bandwidth expansion and in-band phase noise decreasing peculiar to integer-N ADPLL were demonstrated and explained by matlab and verilog behavior level simulation test bench. The expression of threshold quantization step was defined and derived as the method to distinguish whether an integer-N ADPLL was in non-linear cases or not, and the results conformed to those of matlab simulation. A simplified approximation model for non-linear integer-N ADPLL with noise sources was established to predict in-band phase noise, and the trends of the results conformed to those of matlab simulation. Other basic analysis serving for the conclusions above covered: ADPLL loop dynamics, traditional linear theory and its quantitative limitations and numerical analysis of random number. Finally, a present measurement setup was demonstrated and the results were analyzed for future work.

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Un microscope à force atomique (AFM) est utilisé pour caractériser des matériaux isolant ou semi-conducteur avec une résolution pouvant atteindre l'échelle atomique. Ce microscope est constitué d'un capteur de force couplé à une électronique de contrôle pour pouvoir correctement caractériser ces matériaux. Parmi les différents modes (statique et dynamique), nous nous focalisons essentiellement sur le mode dynamique et plus particulièrement sur le fonctionnement sans contact à modulation de fréquence (FM-AFM). Dans ce mode, le capteur de force est maintenu comme un oscillateur harmonique par le système d'asservissement. Le projet ANR Pnano2008 intitulé : ”Cantilevers en carbure de silicium à piézorésistivité métallique pour AFM dynamique à très haute fréquence" a pour objectif d'augmenter significativement les performances d'un FM-AFM en développant un nouveau capteur de force très haute fréquence. Le but est d'augmenter la sensibilité du capteur et de diminuer le temps nécessaire à l'obtention d'une image de la surface du matériau. Le système de contrôle associé doit être capable de détecter des variations de fréquence de 100mHz pour une fréquence de résonance de 50MHz. Etant donné que les systèmes présents dans l'état de l'art ne permettent pas d'atteindre ces performances, l'objectif de cette thèse fut de développer un nouveau système de contrôle. Celui-ci est entièrement numérique et il est implémenté sur une carte de prototypage basée sur un FPGA. Dans ce mémoire, nous présentons le fonctionnement global du système ainsi que ses caractéristiques principales. Elles portent sur la détection de l'écart de fréquence de résonance du capteur de force. / An atomic force microscope (AFM) is used to characterize insulating materials or semiconductors with a resolution up to the atomic length scale. The microscope includes a force sensor linked to a control electronic in order to properly characterize these materials. Among the various modes (static and dynamic), we focus mainly on the dynamic mode and especially on the frequency modulation mode (FM-AFM). In this mode, the force sensor is maintained as a harmonic oscillator by the servo system. The research project ANR Pnano2008 entitled: "metal piezoresistivity silicon carbide cantilever for very high frequency dynamic AFM" aims to significantly increase the performance of a FM-AFM by developing new very high frequency force sensors. The goal is to increase the sensitivity of the sensor and to decrease the time necessary to obtain topography images of the material. The control system of this new sensor must be able to detect frequency variations as small as 100mHz for cantilevers with resonance frequencies up to 50MHz. Since the state-of-the-art systems doe not present these performances, the objective of this thesis was to develop a new control system. It is fully digital and it is implemented on a FPGA based prototyping board. In this report, we present the system overall functioning and its main features which are related to the cantilever resonant frequency detection. This detection is managed by a phase locked loop (PLL) which is the key element of the system.

Les circuits de récupération d'horloge et de données sont nécessaires au bon fonctionnement de plusieurs systèmes de communication sans fil. Les travaux effectués dans le cadre de cette thèse concernent le développement de ces circuits avec d'une part la réalisation, en technologie HCMOS9 0,13 μm de STMICROELECTRONICS, de circuits CDR analogiques à 1 et 54 Mbit/s, et d'autre part, la mise en œuvre de fonctions CDR numériques programmables à bas débit. Un circuit CDR fonctionnant à plus bas débit (1 Mbit/s) a été conçu dans le cadre de la gestion d'énergie d'un récepteur ULB impulsionnel non cohérent. Ces deux structures ont été réalisées à l'aide de PLL analogiques du 3ème ordre. Un comparateur de phase adapté aux impulsions issues du détecteur d'énergie a été proposé dans cette étude. Les circuits ont ensuite été dimensionnés dans le but d'obtenir de très bonnes performances en termes de jitter et de consommation. En particulier, les performances mesurées (sous pointes) du circuit CDR à 1 Mbit/s permettent d'envisager une gestion d'énergie efficace (réduction de plus de 97% de la consommation du récepteur). Dans le cadre d'une chaîne de télémesure avion vers sol, deux circuits CDR numériques ont également été réalisés durant cette thèse. Une PLL numérique du second degré a été implémentée en vue de fournir des données et une horloge synchrone de celles-ci afin de piloter une chaîne SOQPSK entièrement numérique. Un circuit ELGS a également mis au point pour fonctionner au sein d'un récepteur PCM/FM. / Clock and data recovery circuits are required in many wireless communication systems. This thesis is about development of such circuits with: firstly, the realization, in HCMOS9 0.13 μm of STMICROELECTRONICS technology, of 1 and 54 Mb/s analog CDR circuits, and secondly, the implementation of programmable digital circuits at low rates. In the aim of an impulse UWB transceiver dealing with video transmission, a CDR circuit at 54 Mb/s rate has been realized to provide clock signal synchronously with narrow pulses (their duration is about a few nanoseconds) from the energy detector. Another CDR circuit has been built at 1 Mb/s rate in a non-coherent IR- UWB receiver power management context. Both circuits have been implemented as 3rd order analog PLL. In this work, a phase comparator suitable for “RZ low duty cycle” data from the energy detector has been proposed. Circuits have been sized to obtain very good performances in terms of jitter and power consumption. Particularly, measured performances of the 1 Mb/s CDR circuit allow to plan an efficient power management (a decrease of more than 97% of the receiver total power consumption). In the context of a telemetry system from aircraft to ground, two digital CDR circuits have also been implemented. A second order digital PLL has been adopted in order to provide synchronous clock and data to an SOQPSK digital transmitter. Also, a digital ELGS circuit has been proposed to work in a PCM/FM receiver. For both CDR structures, the input signal rate is programmable and varies globally from 1 to 30 Mb/s.