Les récentes avancées des applications de télécommunication radio-fréquences (RF), l'augmentation des fréquences d'opération des microprocesseurs et les possibilités de stockage de données rapides ont pour conséquence une expansion exponentielle du volume de données échangées. Ce développement a été permis et a engendré une demande croissante de systèmes de télécommunication de plus en plus performants, que ce soit en terme de débit, de flexibilité des réseaux, et bien évidement de coût des systèmes.<br /><br />Tous les systèmes de communication modernes requièrent un signal périodique stable pour fournir une base de temps nécessaire à la synchronisation, à l'alignement des horloges d'échantillonnage, à la récupération d'horloge ou encore à la synthèse de fréquence. Le verrouillage de phase est une des principales techniques pour répondre à ces besoins.<br /><br />L'enjeu de ce travail de thèse est de concevoir, réaliser et caractériser une boucle à verrouillage de phase capable de s'intégrer dans un système de télécommunication développé en partenariat entre la société STMicroelectronics et l'Institut Matériaux Microélectronique Nanosciences de Provence (IM2NP). Ce système faible coût, faible consommation, réalisé en technologie CMOS est destiné à des applications de type réseaux personnels sans fils. Des contraintes fortes en terme de surface silicium, consommation, réactivité de la boucle et de précision fréquentielle sont les éléments directeurs de la conception de cette PLL. La boucle réalisée devra être capable de fonctionner en synthétiseur de fréquence et en modulateur FSK. Une attention particulière sera portée à l'oscillateur contrôlé en tension, véritable coeur de la PLL proposée.

<p>The goal of this thesis work is to enable an existing UHF radar to operate in the VHF band instead. In order to achieve this, new coherent local oscillators are required. Different options are suggested and one of them is implemented and analyzed.</p>

<p>The non-overlapping clock signal generator circuits are key elements in switched capacitor circuits since non-overlapping clock signals are generally required. Non-overlapping clock signals means signals running at the same frequency and there is a time between the pulses that none of them is high. This time (when both pulses are logic 0) takes place when the pulses are switching from logic 1 to logic 0 or from logic 0 to logic 1. In this thesis this type of clock signal generators are analyzed and designed for different requirements on the switched capacitor (S/C) circuits. Different analytical models for the delay in CMOS inverters are studied. The clock generators for digital circuits based on phase-locked loop and delay-locked loop are also studied. An algorithm, which can automatically size the non-overlapping clock generator circuits, was implemented.</p>

<p>Den här högskoleavhandlingen beskriver designen av ett IF-filter samt hårdvarukonstruktion av en ny 77 GHz FMCW-radar demonstrator. Syftet med demonstratorn är att illustrera hur kisel germanium-, SiGe, teknologi kan användas istället för den mer vedertagna men dyrare gallium arsenik-, GaAs, teknologin. Den gamla radar-prototypen vilken Acreo AB utvecklat är funktionell men behöver konstrueras om för att bättre kunna utvärdera radarprestandan. I avhandlingen presenteras grundläggande radarteori och ekvationer för att underlätta förståelsen av de olika systemblocken. Rapporten beskriver också systemarkitekturen och hur dess funktionalitet kommer att testas. Det omdesignade IF-filtret har simulerats i en PSpice-simulator och ett prototypkort av detta har tillverkats för mätningar. Ett 4-lagers kretskort av hela systemet har tagits fram i Orcad Layout. Slutligen innehåller rapporten förslag på förbättringar till nästa demonstratorversion.</p> / <p>This bachelor thesis describes the design of an IF-filter and the hardware construction of a new version of a 77 GHz FMCW-radar demonstrator. The purpose of the demonstrator is to illustrate how the silicon germanium-, SiGe, technology could be used instead of the more conventional but also much more expensive gallium arsenide-, GaAs, technology. The old radar prototype that Acreo AB has developed is fully functional but needs to be redesigned to be able to evaluate the radar performance in a better way. The thesis presents the basic radar theory and equations to help understanding the construction of the system blocks. The report also describes the system architecture and how its functionality should be tested. The redesigned IF-filter has been simulated in a PSpice simulator and a prototype has been manufactured and measured. A 4-layer PCB-board of the whole system was done in Orcad Layout. Finally the report is concluded with suggestions on improvements for the next demonstrator version.</p>

La demande croissante de toujours plus de débit pour les télécommunications entraine une augmentation de la fréquence de fonctionnement des liaisons séries. Cette demande se retrouve aussi dans les systèmes embarqués du fait de l'augmentation des performances des composants et périphériques. Afin de s'assurer que le train de données est bien réceptionné, un circuit de restitution d'horloge et de données est placé avant tout traitement du coté du récepteur. Dans ce contexte, les activités de recherche présentées dans cette thèse se concentrent sur la conception d'une CDR (Clock and Data Recovery). Nous détaillerons le comparateur de phase qui joue un rôle critique dans un tel système. Cette thèse présente un comparateur de phase ayant comme avantage d'avoir une mode de fenêtrage et une fréquence de fonctionnement réduite. La topologie spéciale utilisée pour la CDR est décrite, et la théorie relative aux oscillateurs verrouillés en injection est expliquée. L'essentiel du travail de recherche s'est concentrée sur la conception et le layout d'une restitution d'horloge dans le domaine millimétrique, à 80 Gbps. Pour cela plusieurs prototypes ont été réalisés en technologie BiCMOS 130 nm de STMicrolectronics.

With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time. The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spectrum. The Digital Delta-Sigma Modulator can be directly responsible for the generation of spur because of its inherent nonlinearity and periodicity. Many deterministic and stochastic techniques associated with the architecture of the DDSM have been developed to remove the principal causes responsible for production of spurs. The nonlinearities in a frequency synthesizer are another source for the generation of spurs. In this thesis we have predicted that specific nonlinearities in a fractional-N frequency synthesizer produce spurs at well-defined frequencies even if the output of the DDSM is spur-free. Different spur free DDSM architectures have been investigated for the analysis of spurious tones in the output spectrum of fractional-N frequencysynthesizers. The thesis presents simulation and experimental investigation of mechanisms for spur generation in a fractional-N frequency synthesizer. Simulations are carried out using the CppSim system simulator, MATLAB and Simulink while the experiments are performed on an Analog Devices ADF7021, a high performance narrow-band transceiver IC.

One of Saab Space’s products is the S19 guidance system for sounding rockets.Today this system is based on an inertial navigation system that blindly calculatesthe position of the rocket by integrating sensor readings with unknown bias. Thepurpose of this thesis is to integrate a Global Positioning System (GPS) receiverinto the guidance system to increase precision and robustness. There are mainlytwo problems involved in this integration. One is to integrate the GPS with sensorfusion into the existing guidance system. The seconds is to get the GPS satellitetracking to work under extremely high dynamics. The first of the two problems issolved by using an Extended Kalman filter (EKF) with two different linearizations.One of them is uses Euler angles and the other is done with quaternions. Theintegration technique implemented in this thesis is a loose integration between theGPS receiver and the inertial navigation system. The main task of the EKF isto estimate the bias of the inertial navigation system sensors and correct it toeliminate drift in the position. The solution is verified by computing the positionof a car using a GPS and an inertial measurement unit. Different solutions to theGPS tracking problem are proposed in a pre-study. / En av Saab Space produkter är navigationssystemet S19 som styr sondraketer.Fram till idag har systemet varit baserat på ett tröghetsnavigeringssystem somblint räknar ut position genom att integrera tröghetsnavigerinssystemets sensorermed okända biaser. Syftet med detta exjobb är att integrera en GPS med tröghetsnavigeringsystemetför att öka robusthet och precision. Det kan i huvudsak delasupp i två problem; att integrera en GPS-mottagare med det befintliga navigationsystemetmed användning utav sensorfusion, och att få satellitföljningen attfungera under extremt höga dynamiska förhållanden. Det första av de två problemenlöses genom ett Extended Kalman filter (EKF) med två olika linjäriseringar.Den första linjäriseringen är med Eulervinklar och är välbeprövad. Den andra ärmed kvaternioner. Integrationstekniken som implementeras i detta Examensarbeteär en lös integration mellan GPS-mottagaren och tröghetsnavigeringssystemet. Huvudsyftetmed EKF:en är att estimera bias i tröghetsnavigeringsystemets sensoreroch korrigera dem för att eliminera drifter i position. Lösningen verifieras genomatt räkna ut positionen för en bil med GPS och en inertiell mätenhet. Olika lösningartill satellitföljningen föreslås i en förstudie.

The goal of this thesis work is to enable an existing UHF radar to operate in the VHF band instead. In order to achieve this, new coherent local oscillators are required. Different options are suggested and one of them is implemented and analyzed.

The non-overlapping clock signal generator circuits are key elements in switched capacitor circuits since non-overlapping clock signals are generally required. Non-overlapping clock signals means signals running at the same frequency and there is a time between the pulses that none of them is high. This time (when both pulses are logic 0) takes place when the pulses are switching from logic 1 to logic 0 or from logic 0 to logic 1. In this thesis this type of clock signal generators are analyzed and designed for different requirements on the switched capacitor (S/C) circuits. Different analytical models for the delay in CMOS inverters are studied. The clock generators for digital circuits based on phase-locked loop and delay-locked loop are also studied. An algorithm, which can automatically size the non-overlapping clock generator circuits, was implemented.

Den här högskoleavhandlingen beskriver designen av ett IF-filter samt hårdvarukonstruktion av en ny 77 GHz FMCW-radar demonstrator. Syftet med demonstratorn är att illustrera hur kisel germanium-, SiGe, teknologi kan användas istället för den mer vedertagna men dyrare gallium arsenik-, GaAs, teknologin. Den gamla radar-prototypen vilken Acreo AB utvecklat är funktionell men behöver konstrueras om för att bättre kunna utvärdera radarprestandan. I avhandlingen presenteras grundläggande radarteori och ekvationer för att underlätta förståelsen av de olika systemblocken. Rapporten beskriver också systemarkitekturen och hur dess funktionalitet kommer att testas. Det omdesignade IF-filtret har simulerats i en PSpice-simulator och ett prototypkort av detta har tillverkats för mätningar. Ett 4-lagers kretskort av hela systemet har tagits fram i Orcad Layout. Slutligen innehåller rapporten förslag på förbättringar till nästa demonstratorversion. / This bachelor thesis describes the design of an IF-filter and the hardware construction of a new version of a 77 GHz FMCW-radar demonstrator. The purpose of the demonstrator is to illustrate how the silicon germanium-, SiGe, technology could be used instead of the more conventional but also much more expensive gallium arsenide-, GaAs, technology. The old radar prototype that Acreo AB has developed is fully functional but needs to be redesigned to be able to evaluate the radar performance in a better way. The thesis presents the basic radar theory and equations to help understanding the construction of the system blocks. The report also describes the system architecture and how its functionality should be tested. The redesigned IF-filter has been simulated in a PSpice simulator and a prototype has been manufactured and measured. A 4-layer PCB-board of the whole system was done in Orcad Layout. Finally the report is concluded with suggestions on improvements for the next demonstrator version.